JPS59214222A - High density circuit formation - Google Patents

High density circuit formation

Info

Publication number
JPS59214222A
JPS59214222A JP58089002A JP8900283A JPS59214222A JP S59214222 A JPS59214222 A JP S59214222A JP 58089002 A JP58089002 A JP 58089002A JP 8900283 A JP8900283 A JP 8900283A JP S59214222 A JPS59214222 A JP S59214222A
Authority
JP
Japan
Prior art keywords
resin
circuit
substrate
solvent
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58089002A
Other languages
Japanese (ja)
Inventor
Keiichi Nagase
永瀬 慶一
Masafumi Hayashi
林 雅史
Shinji Masaki
正木 信治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NAGASE SCREEN INSATSU KENKYUSHO KK
NANIWA KINEKI KK
Original Assignee
NAGASE SCREEN INSATSU KENKYUSHO KK
NANIWA KINEKI KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NAGASE SCREEN INSATSU KENKYUSHO KK, NANIWA KINEKI KK filed Critical NAGASE SCREEN INSATSU KENKYUSHO KK
Priority to JP58089002A priority Critical patent/JPS59214222A/en
Publication of JPS59214222A publication Critical patent/JPS59214222A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To obtain a continuous metal film without unevenness by a method wherein resin mixture of synthetic resin such as sulfide resin gold and a solvent is applied all over a substrate and dried and baked to form a metal film and photosensitive emulsion is applied on the metal film and exposed and developed. CONSTITUTION:Synthetic resin such as sulfide resin gold, rhodium resin, bismuth resin, chrome resin, nickel resin and ethylcellose are mixed with a solvent to make printing ink. This ink is applied all over a substrate and dried and baked. Then photosensitive emulsion is applied on the surface and exposed and baked. The solvent and the resin are burnt out during the baking and the remainder metals compose alloy so that a circuit composed of continuous alloy coupling surface is formed on the substrate.

Description

【発明の詳細な説明】 この発明はLSI等の回路を形成する為の高密度回路形
成法に関するものであり、その目的とするところI′i
、、g駄な金粉その他の貴金属の浪費を省き、而も、低
い抵抗1面7Nし、且つ、断線等の欠陥ケ有しない回路
を迅速に形成せんとするものである。
[Detailed Description of the Invention] The present invention relates to a high-density circuit formation method for forming circuits such as LSI, and its purpose is to
The purpose of this invention is to eliminate the waste of useless gold powder and other precious metals, and quickly form a circuit that has a low resistance of 7N per side and is free from defects such as disconnections.

従来、例えばLSI回路のシリコンウニターを製造する
に当っては、先ず、ウェアの片面に、写真製版感光液?
!−塗布した後、露光、現像し、各種導体金属?蒸着し
て甑敵細のLSI回路を作製した後、レーザー光線或は
ダイヤモンドカッターにて小片(5mm X 5 mm
等)ICカットし、その小片に顕畝鏡等?!−変用して
、エボギシ樹脂、その他の高分子樹脂で金箔の小片?1
Il−前記LSI回路の裏面に貼着し、その後400°
C乃至450°(]の雰囲気中で焼成していたのである
。このとき、スクリーン印刷によって回路を印刷する場
合は、例えば金粉→75〜80%、ガラスフリット→2
〜18%、エチルセルローズ等の樹脂及びブチルカルピ
トール等の浴剤→7〜28%にて印刷インクを作9、之
ICJ−って回路を印刷し、之を焼成して仕上げていた
のである。然るに、この工法によるときは、必要以上に
膜厚となり5例えば2〜8μにするこどは殆ど不可能と
されていた。従って、金の浪費が甚大で4、あった。又
、薄膜に形成する為に、蒸看法もあるが、之は電気的負
荷によって、綴々断線する現象が発生していたのである
。而も、例えば、1μ乃至2μ等の薄膜に形成せんとす
るときは、作業工程上多大の時間を要していたのである
。又、従来の工法は、何ルにしても、純金とガラス質と
によって回路を形成し、之を溶着せしめる工法である為
、ウェアーに対して完全な接着面を得られず、従って、
金相瓦間の連続性が不完全であp1故に電気的抵抗が増
大し、断線の原因となっていたのである。
Conventionally, for example, when manufacturing a silicon unit for an LSI circuit, one side of the ware was first coated with a photolithographic liquid.
! -After coating, exposing and developing various conductive metals? After producing a thin LSI circuit by vapor deposition, it is cut into small pieces (5 mm x 5 mm) using a laser beam or a diamond cutter.
etc.) Cut the IC and put a microscope on the small piece? ! - Small pieces of gold leaf made of Ebogishi resin or other polymer resin? 1
Il- pasted on the back side of the above LSI circuit, then 400°
It was fired in an atmosphere of C to 450 degrees (). At this time, when printing a circuit by screen printing, for example, gold powder → 75 to 80%, glass frit → 2
~18%, resins such as ethyl cellulose, and bath agents such as butyl calpitol → 7~28% to make printing ink9, printed a circuit called ICJ-, and finished it by firing. . However, when using this construction method, the film thickness becomes larger than necessary, and it is almost impossible to achieve a film thickness of 5, for example, 2 to 8 μm. Therefore, there was a huge waste of money. There is also a vaporization method for forming thin films, but this often causes wires to break due to electrical loads. However, when attempting to form a thin film of, for example, 1 μm to 2 μm, a large amount of time is required in the working process. In addition, in any case, the conventional construction method involves forming a circuit using pure gold and glass and welding them together, so it is not possible to obtain a perfect bonding surface to the wear.
The electrical resistance increased due to the imperfect continuity between the metal tiles, p1, which caused wire breakage.

この発明は、従来の叙述せる欠陥に鑑み、之等を解消せ
んとして提案せらt′Lにものであり、硫化樹脂金及び
aジューム樹脂並びにビスマス樹脂及びクロム+atj
凱ニッケル樹脂に合成樹脂又は天然樹脂と溶剤とt混合
して印刷用インクとし、この印刷用インクでセラミック
又はガラス或はシリコンウェアー等の基板上の全面に印
刷し、之を乾燥させた後焼成し、この上面に感光性乳剤
を塗布し。
This invention was proposed in view of the deficiencies described in the prior art in order to solve the above problems, and it was proposed to solve the problems described above.
A printing ink is made by mixing nickel resin with a synthetic resin or natural resin and a solvent, and this printing ink is used to print on the entire surface of a substrate such as ceramic, glass, or silicone ware, which is dried and then fired. A photosensitive emulsion is then applied to this top surface.

之を乾燥させた後、予め作製しているガラス又はフィル
ム回路のネガ又はポジ勿当てて露光して回路を現像し、
収て、回路を残存させ、之を王水等の環元剤液中に浸漬
して回路面以外の金属面を融解せしめることにより、基
板上に回路〒形成させる高密度回路形成法を提供せんと
するものである。
After this is dried, the negative or positive of the glass or film circuit prepared in advance is exposed to light and the circuit is developed.
The present invention provides a high-density circuit formation method in which circuits are formed on a substrate by immersing the circuit board in a cyclic agent solution such as aqua regia to melt the metal surface other than the circuit surface. That is.

以下、この発明の一実施例r詳述する。先ず。Hereinafter, one embodiment of the present invention will be described in detail. First.

硫化樹脂に金を反応させて硫比面脂金を作る。更に、硫
化樹脂とロジュームとt反応させて硫1ヒ樹脂ロジュー
ム塩を作る。之は一般に、ロジューム樹脂と称さ扛るも
のである。次に、硫化樹脂とビスマスとt反応させてビ
スマス樹脂を作り、更に、硫化樹脂とクロムと勿反応さ
せてクロム樹脂を作り、硫化樹脂とニッケルとt反応さ
せてニッケル樹脂を作る。以上の物質とエチルセルロー
ズ等の合成樹脂又は松脂等の天然樹脂と溶剤とt混合し
て印刷用インク盆作るのである。この印刷用インクによ
ってセラミック、ガラス又はシリコンウェアー等の基板
にスクリーン印刷又はタンポ印刷等によってベタ刷シす
る。従って、前記基板面には前記混合物が全面に印刷さ
往、之r乾燥させる。
Sulfurized resin is made by reacting gold with sulfurized resin. Furthermore, the sulfurized resin and rhodium are reacted to produce a sulfurized resin rhodium salt. This is generally referred to as rhodium resin. Next, the sulfurized resin is reacted with bismuth to produce a bismuth resin, the sulfurized resin is further reacted with chromium to produce a chromium resin, and the sulfurized resin is reacted with nickel to produce a nickel resin. The above substances are mixed with a synthetic resin such as ethyl cellulose or a natural resin such as pine resin and a solvent to make an ink basin for printing. This printing ink is printed all over a substrate such as ceramic, glass, or silicone ware by screen printing or pad printing. Therefore, the mixture is printed all over the surface of the substrate and is then allowed to dry.

この乾燥を促1位する為s 6iJ記混合物に紫外線硬
化性樹脂調合物5〜80重l辻チ〃)らなる紫外線硬[
ヒペース)k混合して印刷用インクとし、之によって前
記回路を印刷して之を乾燥する場合、紫外綜盆該回路に
照射することにより直ちに回路が乾燥するので、乾燥時
間が著しく短縮され、甑めてコストダウンにも寄与する
ことになるのである。斯(の明(シて乾燥し定前記印刷
面は焼成して仕上げらnるのである。この焼成温度は、
略45θ°Cであるが、この焼成中に於て、溶剤及び樹
脂分は250°C〜450°Cの間に於て熱分解して完
全に焼失し、残りの金稿が合金となり、溶融して拡散結
合して連続的合金の結合面r前記基板上に形成:  す
るに到るのである。即ち、金、ctジューム、クロム、
ビスマス、ニッケルは通常プライト金と称せらする合金
となって基板の表面に強固に燐層せられるのである0仄
に、この上面に、フォートレジスト等の感光性乳剤盆塗
布し、之を乾燥させた後、予め、作製しているガラス又
にフィルム回路のネガ又はポジを当てて露光して回路を
現像する。
In order to accelerate this drying, an ultraviolet curable [
When printing the circuit and drying it by mixing it with HYPACE) and drying it, the circuit is immediately dried by irradiating it with ultraviolet light, so the drying time is significantly shortened, and This will also contribute to cost reduction. After drying, the printed surface is finished by firing.The firing temperature is:
The temperature is approximately 45θ°C, but during this firing, the solvent and resin are thermally decomposed between 250°C and 450°C and are completely burned out, and the remaining metal becomes an alloy and melts. and diffusion bonding to form a bonding surface of a continuous alloy on the substrate. i.e. gold, ctdium, chromium,
Bismuth and nickel are usually formed into an alloy called prite gold, which forms a strong phosphorous layer on the surface of the substrate.Then, a photosensitive emulsion such as Fortresist is applied to the upper surface of the substrate, and this is dried. After that, the negative or positive of the film circuit is applied to the glass or glass that has been prepared in advance, and the circuit is developed by exposing it to light.

現像された回路以外の部分、即ち、未露光部分は、自然
に乳剤が洗い落される。従って回路面のみが残存し、と
の回路面以外の部分、即ち、前記乳剤が洗い落さrt友
部分は、前述の合金が表わ扛て(るのである。次に、之
を王水等の環元剤の中に浸漬する。然るときは、前記回
路面ケ残し2表面に表わ1ている合金は該環元剤によっ
て融解し、完全に回路面だけが基板上に残置するに到る
のである。後は、感光した乳剤膜勿除去する為に溶剤で
洗い落せば前記合金が基板上に形成せられることになる
のである。従って、この合金は、その焼成時に於て拡散
し乍ら結合するので連続的となり、従来のような断線の
原因とならず、性能が著しく増大するのである。而も、
合金の拡散結合は、史に、2μ8度の薄膜にも回路を形
成できるのである。又、2μあnばハンダ付けも充分可
能となる。
The emulsion is naturally washed off from areas other than the developed circuit, ie, unexposed areas. Therefore, only the circuit surface remains, and the above-mentioned alloy is exposed in the portion other than the circuit surface, that is, the portion where the emulsion has been washed away. At that time, the alloy shown on the surface of the remaining circuit surface 2 is melted by the cyclizing agent, so that only the circuit surface is completely left on the board. Afterwards, the alloy is formed on the substrate by rinsing it with a solvent to remove the exposed emulsion film.Therefore, this alloy is diffused during firing. However, since they are connected, they are continuous and do not cause disconnections like in the past, and the performance is significantly increased.
Diffusion bonding of alloys has historically made it possible to form circuits in thin films of 2μ8 degrees. Further, if the thickness is 2 μm, soldering is sufficiently possible.

本発明・は、叙述せる一実施例に於て詳述せる傾(%電
気良導体の金嘱膜によって、而も、凹凸面のない連続し
た金稿膜によって回路を形成できるので、金粉の無駄が
なくなり、抵抗1直の低い回路を形成でき、且つ、断線
現象がなくなる為、極めて著大なる効果を奏する高密度
回路形成法である。
The present invention will be described in detail in one embodiment.A circuit can be formed by using a gold film that is a good electrical conductor, and also by a continuous metal film without uneven surfaces, so that there is no waste of gold powder. This is a high-density circuit formation method that is extremely effective because it allows the formation of a low-resistance circuit with only one resistor and eliminates the disconnection phenomenon.

株式会社氷瀬スク 特t’f 出願人+)−ン印刷研究所 同     浪速金液株式会社 l−1゜ 代理人弁理士 林   孝 吉Hise School Co., Ltd. Special t’f Applicant +)-N Printing Institute Same as Naniwa Gold Liquid Co., Ltd. l-1゜ Representative Patent Attorney Takayoshi Hayashi

Claims (1)

【特許請求の範囲】 硫化樹脂金及びロジューム樹脂並びにビスマス樹脂及び
クロム樹脂、ニッケル樹脂に合成樹脂又は天然樹脂と溶
剤とt混合して印刷用インクとじ、この印刷用インクで
セラミック又はガラス或は、シリコンウェア等の基板上
の全面に印刷し、之を乾燥させた後焼成し、この上面に
感光性乳剤を僧布し、之7乾6(ムさせた後、予め作製
しているガラス又はフィルム回路のネガ又はポジを当て
て露光して回路【現像し、以て回路を残存させ、之を王
水邪の環尤剤液中[浸漬して回路面以外の金属面を融解
せしめることにより、基板上に回路を形成させることケ
特徴とする高密度回路形成法。
[Scope of Claims] Printing ink is produced by mixing sulfurized resin gold, rhodium resin, bismuth resin, chromium resin, nickel resin with synthetic resin or natural resin and a solvent, and this printing ink is used to print ceramics, glass, etc. Print on the entire surface of a substrate such as silicone ware, dry it, and then bake it, apply a photosensitive emulsion on the top surface, and dry it. The circuit is developed by applying a negative or positive of the circuit and exposing it to light, thereby leaving the circuit, and then immersing it in an aqua regia ring agent solution to melt the metal surface other than the circuit surface. A high-density circuit formation method characterized by forming circuits on a substrate.
JP58089002A 1983-05-20 1983-05-20 High density circuit formation Pending JPS59214222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58089002A JPS59214222A (en) 1983-05-20 1983-05-20 High density circuit formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58089002A JPS59214222A (en) 1983-05-20 1983-05-20 High density circuit formation

Publications (1)

Publication Number Publication Date
JPS59214222A true JPS59214222A (en) 1984-12-04

Family

ID=13958600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58089002A Pending JPS59214222A (en) 1983-05-20 1983-05-20 High density circuit formation

Country Status (1)

Country Link
JP (1) JPS59214222A (en)

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