JPS5921218B2 - Astable multi-circuit - Google Patents
Astable multi-circuitInfo
- Publication number
- JPS5921218B2 JPS5921218B2 JP53111189A JP11118978A JPS5921218B2 JP S5921218 B2 JPS5921218 B2 JP S5921218B2 JP 53111189 A JP53111189 A JP 53111189A JP 11118978 A JP11118978 A JP 11118978A JP S5921218 B2 JPS5921218 B2 JP S5921218B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- capacitor
- circuit
- voltage
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/282—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator astable
- H03K3/2826—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator astable using two active transistors of the complementary type
- H03K3/2828—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator astable using two active transistors of the complementary type in an asymmetrical circuit configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
Description
【発明の詳細な説明】
本発明は非安定マルチ回路に関するものであり、トラン
ジスタ２石の簡単な構成で、コンデンサ充電回路にダイ
オードを用い、充電々流と放電々流とを完全に分離する
ことにより、オン時間とオフ時間を独立して設定するこ
とができるようにしたものである。[Detailed Description of the Invention] The present invention relates to an unstable multi-circuit, which has a simple configuration of two transistors, uses a diode in the capacitor charging circuit, and completely separates the charging current and the discharging current. This allows on-time and off-time to be set independently.
以下、添付図面にもとづき本発明の一実施例について詳
述する。Hereinafter, one embodiment of the present invention will be described in detail based on the accompanying drawings.
図において１は直流電源、Ｒ１−Ｒ６は抵抗、２，３は
それぞれダイオード、コンデンサで、抵抗Ｒ２とともに
コンデンサ充電回路を構成している。In the figure, 1 is a DC power supply, R1-R6 are resistors, and 2 and 3 are diodes and capacitors, respectively, which together with the resistor R2 constitute a capacitor charging circuit.
Ｑｌは第１のトランジスタで、コレクタ端子には抵抗Ｒ
６を介して第２のトランジスタＱ２のベース端子に接続
されている。Ql is the first transistor, and the collector terminal has a resistor R
6 to the base terminal of the second transistor Q2.
第１のトランジスタＱ１のベース端子には、直流電源１
の電圧を屯及びＲ４で抵抗分割して得られる基準電圧が
与えられている。A DC power supply 1 is connected to the base terminal of the first transistor Q1.
A reference voltage obtained by resistance-dividing the voltage by R4 and R4 is given.
また、このベース端子と第２のトランジスタＱ２のコレ
クタ端子には抵抗Ｒ５が接続されており、トランジスタ
Ｑ２がオンになると、抵抗Ｒ５とＲ４は並列接続された
形になり基準電圧は下がる。Further, a resistor R5 is connected to this base terminal and the collector terminal of the second transistor Q2, and when the transistor Q2 is turned on, the resistors R5 and R4 are connected in parallel, and the reference voltage decreases.
さらにトランジスタＱ２のコレクタ端子は抵抗Ｒ１とＲ
２の接続点に接続されている。Furthermore, the collector terminal of transistor Q2 is connected to resistor R1 and R
It is connected to the second connection point.
なお出力はトランジスタＱ２のコレクタ端子から取って
いる。Note that the output is taken from the collector terminal of transistor Q2.
第２図及び第３図は、それぞれ、コンデンサ３の端子電
圧波形Ｖｏ及び出力電圧波形を示す。2 and 3 show the terminal voltage waveform Vo and output voltage waveform of the capacitor 3, respectively.
上記構成において、直流電源が与えられると、トランジ
スタＱ１のベースには基準電圧Ａ７Ａが印加され、エミ
ッタ電圧、即ちコンデンサ３の端子電圧Ｖｏはそれより
も低いので、トランジスタＱ１はオフの状態にある。In the above configuration, when DC power is applied, the reference voltage A7A is applied to the base of the transistor Q1, and the emitter voltage, that is, the terminal voltage Vo of the capacitor 3 is lower than that, so the transistor Q1 is in an off state.
従って第２のトランジスタＱ２もオフの状態にある。Therefore, the second transistor Q2 is also in an off state.
コンデンサ３は抵抗Ｒ１，Ｒ２及びダイオード２を通し
て充電され、第２図に示すように、コンデンサ３の端子
電圧Ｖｃが、基準電圧ｖＡに達すると、第１のトランジ
スタＱ、のエミッタからベースへ電流が流れ始める。The capacitor 3 is charged through the resistors R1 and R2 and the diode 2, and as shown in FIG. 2, when the terminal voltage Vc of the capacitor 3 reaches the reference voltage vA, a current flows from the emitter to the base of the first transistor Q. It starts to flow.
これと同時にエミッタからコレクタに百数十倍の電流を
流すので、第２のトランジスタＱ２は急速にオンになり
、基準電圧、即ち第１のトランジスタＱ１のベース電圧
は急速にＶＢに低下する。At the same time, a hundred-and-odd times more current flows from the emitter to the collector, so the second transistor Q2 is rapidly turned on, and the reference voltage, that is, the base voltage of the first transistor Q1, rapidly drops to VB.
さらにこの時、抵抗Ｒ１とＲ２の接続点の電圧はＯｌこ
なるので、ダイオード２は逆バイアスされ、コンデンサ
３の充電々流は停止する。Furthermore, at this time, since the voltage at the connection point between resistors R1 and R2 becomes O1, the diode 2 is reverse biased and the charging current of the capacitor 3 is stopped.
以上第１のトランジスタＱ、及び第２のトランジスタＱ
２がオンになるまでの出力波形は第３図に示すようにＩ
ＨＪで、オンになると同時に「Ｌ」に変化する。The first transistor Q and the second transistor Q
The output waveform until I turns on is as shown in Figure 3.
At HJ, it changes to "L" at the same time as it turns on.
次にコンデンサ３に蓄えられた電荷は、殆んど、抵抗Ｒ
６を通して放電し、コンデンサ３の端子電圧は徐々に下
降する。Next, most of the charge stored in capacitor 3 is transferred to resistor R
6 and the terminal voltage of capacitor 3 gradually decreases.
そして基準電圧ｖＢまで達すると、第１のトランジスタ
Ｑ１のエミッタからベースへ電流は流れなくなり、トラ
ンジスタＱ１はオフになる。When the reference voltage vB is reached, current no longer flows from the emitter to the base of the first transistor Q1, and the transistor Q1 is turned off.
それと同時にトランジスタＱ２もオフになるので、基準
電圧■８から再び■いに復帰する。At the same time, the transistor Q2 is also turned off, so that the reference voltage returns from 8 to 2 again.
従って、抵抗Ｒ１とＲ２の接続点も初期状態にもどり、
再びコンデンサ３は充電されるようになる。Therefore, the connection point between resistors R1 and R2 also returns to its initial state,
Capacitor 3 becomes charged again.
以上出力電圧波形はｒＬＪの状態からｒＨＪの状態に復
帰する。The output voltage waveform returns from the rLJ state to the rHJ state.
このような動作を繰り返し、出力には第３図に示すよう
な方形波出力が得られる。By repeating this operation, a square wave output as shown in FIG. 3 is obtained.
なお、コンデンサ３の充電々流は抵抗Ｒ２を、放電々流
は抵抗Ｒ６を通るようにして、充電路と放電路を全く分
離独立させているので、出力波形のｒＨＪの時間及びｒ
ＬＪの時間は、それぞれ抵抗Ｒ２及びＲ６の抵抗値を変
えることにより任意に設定することができる。Note that the charging current and discharging current of the capacitor 3 pass through the resistor R2, and the discharging current passes through the resistor R6, so that the charging path and the discharging path are completely separated and independent, so the rHJ time and r
The LJ time can be arbitrarily set by changing the resistance values of the resistors R2 and R6.
上述したように、本発明によれば簡単に非安定マルチ回
路が構成でき信頼性が高く、出力波形のオン・オフ巾を
独立して設定することができ、回路設計が容易になるも
のである。As described above, according to the present invention, an unstable multi-circuit can be easily constructed, the reliability is high, and the on/off width of the output waveform can be set independently, making circuit design easy. .
第１図は本発明の一実施例を示す非安定マルチ回路図、
第２図はコンデンサの端子電圧波形図、第３図は回路の
出力波形図である。
１・・・・・・直流電源、２・・・・・・ダイオード、
３・・・・・・コンデンサ、Ｑｌ、Ｑ２・・・・・・ト
ランジスタ、Ｒ１−Ｒ６・・・・・・抵抗。FIG. 1 is an unstable multi-circuit diagram showing an embodiment of the present invention.
FIG. 2 is a diagram of the terminal voltage waveform of the capacitor, and FIG. 3 is a diagram of the output waveform of the circuit. 1...DC power supply, 2...Diode,
3... Capacitor, Ql, Q2... Transistor, R1-R6... Resistor.
Claims (1)
するコンデンサ充電回路を接続するとともに、前記コン
デンサの端子電圧と所定の基準電圧とを比較してスイッ
チング動作を行う第１のトランジスタと、この第１のト
ランジスタの出力でスイッチング動作を行う第２のトラ
ンジスタとにより前記コンデンサの放電路を形成し、こ
の第２のトランジスタのオン動作により、前記基準電圧
を下げると同時に、前記コンデンサの充電々流を側路さ
せ、前記ダイオードを逆バイアスし前記コンデンサの充
電々流を停止させることを特徴とする非安定マルチ回路
。1. A capacitor charging circuit that forms a charging path with a resistor and a diode is connected to a DC power supply, and a first transistor that performs a switching operation by comparing the terminal voltage of the capacitor with a predetermined reference voltage; A discharge path for the capacitor is formed by a second transistor that performs a switching operation using the output of the transistor, and by turning on the second transistor, the reference voltage is lowered and the charging current of the capacitor is turned to the side. An astable multi-circuit characterized in that the diode is reverse-biased to stop the charging current of the capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53111189A JPS5921218B2 (en) | 1978-09-08 | 1978-09-08 | Astable multi-circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53111189A JPS5921218B2 (en) | 1978-09-08 | 1978-09-08 | Astable multi-circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5538734A JPS5538734A (en) | 1980-03-18 |
| JPS5921218B2 true JPS5921218B2 (en) | 1984-05-18 |
Family
ID=14554743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53111189A Expired JPS5921218B2 (en) | 1978-09-08 | 1978-09-08 | Astable multi-circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5921218B2 (en) |
-
1978
- 1978-09-08 JP JP53111189A patent/JPS5921218B2/en not_active Expired
Non-Patent Citations (1)
| Title |
|---|
| WORLD PATENT ABSTRACTS JOURNAL * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5538734A (en) | 1980-03-18 |
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