JPS59210381A - Testing circuit of integrated circuit device - Google Patents
Testing circuit of integrated circuit deviceInfo
- Publication number
- JPS59210381A JPS59210381A JP58085283A JP8528383A JPS59210381A JP S59210381 A JPS59210381 A JP S59210381A JP 58085283 A JP58085283 A JP 58085283A JP 8528383 A JP8528383 A JP 8528383A JP S59210381 A JPS59210381 A JP S59210381A
- Authority
- JP
- Japan
- Prior art keywords
- test
- circuit
- terminal
- output
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は集積回路装置の試験回路に関し、特に集積回路
装置に内蔵できる試験回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test circuit for an integrated circuit device, and more particularly to a test circuit that can be built into an integrated circuit device.
従来、集積回路装置（以下ＩＣという）の試験を行なう
ためにはＩＣ内に実用上は使用しない試験用の余分な外
部端子を複数個設けこの外部端子からの信号をＩＣ内で
受取り様々な試験を行なうのが普通である。Conventionally, in order to test an integrated circuit device (hereinafter referred to as IC), a plurality of extra external terminals for testing that are not actually used are provided inside the IC, and signals from these external terminals are received within the IC and used for various tests. It is common to do this.
第１図は従来の試１験回路を内蔵するＩＣの一例のブロ
ックである。FIG. 1 is a block diagram of an example of an IC incorporating a conventional test circuit.
ＩＣＩの中に外部端子４から接続される本来の機能を有
する本回路２と試験用外部端子５（以下テスト端子とい
う）から接続されているデコーダ３があり、デコーダ３
の出力が本回路２に接続されている。Inside the ICI, there is a main circuit 2 which has an original function and which is connected to an external terminal 4, and a decoder 3 which is connected to an external terminal 5 for testing (hereinafter referred to as a test terminal).
The output of is connected to this circuit 2.
本来の機能を行なう場合は、テスト端子５をデコーダ３
の出力が試験のモード（以下テストモードという）にな
らないような値に保持しておく。When performing the original function, connect test terminal 5 to decoder 3.
The output is kept at a value that does not cause it to enter test mode (hereinafter referred to as test mode).
これが通常のモードである。This is the normal mode.
一方、試験を行なう場合は、テスト端子にデコーダ３の
出力が試験を行なおうとする状態となるような値を加え
デコーダ３から本回路２にかかるテストモード用の信号
が送ら３１％テスト用の動作を行なう。On the other hand, when performing a test, add a value to the test terminal so that the output of the decoder 3 is in the state in which the test is to be performed, and the decoder 3 sends a test mode signal to this circuit 2 for the 31% test. Perform the action.
このような試験回路を内蔵した場合にはテスト端子が数
個必要であるという欠点がある。例えば。When such a test circuit is built-in, there is a drawback that several test terminals are required. for example.
３つのテストモードが必要ならば２個のテスト端子％
７つのテストモードが必要ならば３個のテス上端子とい
うように数個のテスト用端子が必要となる。ところで、
この端子の数というものはＩＣにとっては以下のような
点で大きな問題となってくる。第１に、端子数によりＩ
Ｃのパッケージが制限されたり、また端子数が増えたこ
とにより実装に於ても製造コストが増えたりすることが
ある。If three test modes are required, two test terminals%
If seven test modes are required, several test terminals, such as three test terminals, are required. by the way,
The number of terminals poses a major problem for ICs in the following respects. First, depending on the number of terminals, I
The number of C packages may be limited, and the increased number of terminals may increase manufacturing costs for mounting.
第２に、ＩＣのチップに於ても端子が増えるとこの端子
用の接続部（以後パッドとよぶ）を増やすことが必要と
なるが、このパッドの大きさはかなり大きく、かつ型造
設備との関連で容易に小さくできない。ＩＣパターンの
微細化に伴ない、この端子を増やすよりは多少回路が増
えてもパッドを省くことによりチップ面積を小さくし得
る。Second, as the number of terminals increases in an IC chip, it becomes necessary to increase the number of connection parts (hereinafter referred to as pads) for these terminals, but the size of these pads is quite large, and molding equipment is required. cannot be easily made smaller due to As IC patterns become finer, the chip area can be reduced by omitting pads, even if the number of circuits increases somewhat, rather than by increasing the number of terminals.
このようなことから従来の試験回路を内蔵せしめたとき
は、ＩＣの端子数が増加し、パッケージの制限、コスト
の上昇、ＩＣチップの面積の増大を招くという欠点があ
った・
本発明は上記欠点を除去し、テスト端子を一つしか必要
とせず、しかも従来と同様な試験を行うことが可能であ
る集積回路装置の試験回路を提供するものである。For this reason, when a conventional test circuit is built-in, the number of terminals of the IC increases, resulting in package limitations, cost increases, and an increase in the area of the IC chip. An object of the present invention is to provide a test circuit for an integrated circuit device that eliminates the drawbacks, requires only one test terminal, and can perform tests similar to conventional tests.
本発明の集積回路装置の試験回路は、テスト用に設けら
れた一つの外部端子をクロック入力とするカウンタと、
該カウンタの出力を人力とし、その内容をデコードした
データを出力する論理回路とを含んで構成される。A test circuit for an integrated circuit device according to the present invention includes a counter whose clock input is one external terminal provided for testing;
It is configured to include a logic circuit that uses the output of the counter manually and outputs data obtained by decoding the contents.
前記試験回路は試験される集積回路装置と共に同一半導
体基板に集積形成することが望ましい。It is preferable that the test circuit and the integrated circuit device to be tested be integrated on the same semiconductor substrate.
次に１本発明の実施例について図面を用いて説明する。Next, an embodiment of the present invention will be described with reference to the drawings.
第２図は本発明の一実施例のブロック図である。FIG. 2 is a block diagram of one embodiment of the present invention.
外部端子４は通常の外部端子として本回路２に接続され
ている。外部端子５はテスト端子でありカウンタ７のク
ロック入力となっておりこの出力はデコーダ３の入力に
接続され、デコーダされた出力は本回路に入力されてい
る。The external terminal 4 is connected to the main circuit 2 as a normal external terminal. External terminal 5 is a test terminal and serves as a clock input for counter 7, and its output is connected to the input of decoder 3, and the decoded output is input to this circuit.
ここで、テストを行なう場合はテスト端子５からクロッ
クを入力しカウンタ７の値を変化させ、かかるカウンタ
７の出力をデコーダ３でデコードし、希望するテストの
モードの出力をデコーダから出力する。Here, when performing a test, a clock is input from the test terminal 5 to change the value of the counter 7, the output of the counter 7 is decoded by the decoder 3, and the output of the desired test mode is output from the decoder.
このようにテスト時にはテスト端子５からクロックを希
望するだけ加えるだけで、その入力数に対応するテスト
出力が得られる。また、テスト端子としては一つだけで
試験回路を構成できると同時に、このカウンタはＤ型フ
リップフロップなど様々な小規模の回路構成で実現でき
、従来例のようにテスト端子用パッドも必要としないこ
とからチップ面積も小さくすることも可能である。In this way, at the time of testing, by simply adding as many clocks as desired from the test terminal 5, a test output corresponding to the number of inputs can be obtained. In addition, the test circuit can be configured with only one test terminal, and at the same time, this counter can be realized with various small-scale circuit configurations such as a D-type flip-flop, and there is no need for test terminal pads as in conventional examples. Therefore, it is also possible to reduce the chip area.
以上詳細に説明したように本発明によれば、テスト用端
子の数が最小限の１個ですみチップ面積も従来例と同等
かそれ以下とすることのできる集積回路装置の試験回路
が得られるのでその効果は大きい。As described in detail above, according to the present invention, it is possible to obtain a test circuit for an integrated circuit device that requires only one test terminal and has a chip area that is equal to or smaller than that of the conventional example. So the effect is big.
第１図は従来の試験回路を内蔵したＩＣの一例のブロッ
ク図、第２図は本発明の一実施例のブロック図である。
１・・・・・・ＩＣ，２・・・・・・本回路、吐・曲デ
コーダ。
４・・・・・・外部端子、５・・・由テスト用外部端子
、６・・・・・・パワーオンクリア回路、７・曲・カウ
ンタ。
？
３
ｎ ／ 図
鵠 ２図
４９７−FIG. 1 is a block diagram of an example of an IC incorporating a conventional test circuit, and FIG. 2 is a block diagram of an embodiment of the present invention. 1...IC, 2...This circuit, output/music decoder. 4...External terminal, 5...External terminal for test, 6...Power-on clear circuit, 7. Song/counter. ? 3 n / Figure 2 497-
Claims (1)
するカウンタと、該カウンタの出力を入力とし、その内
容をデコードしたデータを出力する論理回路とを含むこ
とを特徴とする集積回路装置の試験回路。Testing of an integrated circuit device characterized by including a counter that uses one external terminal provided for testing as a clock input, and a logic circuit that uses the output of the counter as an input and outputs data obtained by decoding its contents. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58085283A JPS59210381A (en) | 1983-05-16 | 1983-05-16 | Testing circuit of integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58085283A JPS59210381A (en) | 1983-05-16 | 1983-05-16 | Testing circuit of integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59210381A true JPS59210381A (en) | 1984-11-29 |
Family
ID=13854239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58085283A Pending JPS59210381A (en) | 1983-05-16 | 1983-05-16 | Testing circuit of integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59210381A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04243158A (en) * | 1991-01-17 | 1992-08-31 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
-
1983
- 1983-05-16 JP JP58085283A patent/JPS59210381A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04243158A (en) * | 1991-01-17 | 1992-08-31 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
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