JPS59208862A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59208862A
JPS59208862A JP8273983A JP8273983A JPS59208862A JP S59208862 A JPS59208862 A JP S59208862A JP 8273983 A JP8273983 A JP 8273983A JP 8273983 A JP8273983 A JP 8273983A JP S59208862 A JPS59208862 A JP S59208862A
Authority
JP
Japan
Prior art keywords
neutrons
boron
semiconductor device
resin
rays
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8273983A
Other languages
Japanese (ja)
Other versions
JPH0324785B2 (en
Inventor
Michiko Tsuchimoto
槌本 道子
Hiroshi Doi
土井 紘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP8273983A priority Critical patent/JPS59208862A/en
Publication of JPS59208862A publication Critical patent/JPS59208862A/en
Publication of JPH0324785B2 publication Critical patent/JPH0324785B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To obtain a semiconductor device, a memory therein generates no malfunction due to a soft-error, by preventing the soft-error by neutrons by reacting neutrons and boron and converting neutrons and boron into alpha-rays. CONSTITUTION:Boron is made contain in a semiconductor device material such as a package material, boron <10>B in said material and neutrons are catalytically reacted, and neutrons are converted into alpha-rays. A semiconductor chip 1 to which circuits, such as a memory circuit, a logical circuit, etc. are formed is coated with a polyimide group resin 2 in not less than several dozen mum thickness, and a sealing body 30 is formed by a molding resin containing boron <10>B such as epoxy resin so as to wrap the chip 1 and the resin 2. A semiconductor device preventing a soft-error due to neutrons is obtained by reacting neutrons with boron <10>B and converting neutrons into alpha-rays.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は中性子によるソフトエラーを防止した半導体装
置に関し、特に宇宙線を地上より強く浴びるロケット搭
載用メモリや原子炉近辺で使用するメモリなどのメモリ
素子の中性子によるソフトエラーを防止した半導体記憶
装置に関する。
[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device that prevents soft errors caused by neutrons, and is particularly applicable to memory devices used in rocket-mounted memories and memories used near nuclear reactors, which are exposed to cosmic rays more strongly than on the ground. The present invention relates to a semiconductor memory device that prevents soft errors caused by neutrons.

〔背景技術〕[Background technology]

半導体記憶装置においてメモリを誤動作させるいわゆる
ソフトエラーは、ウラン(U)やトリウム(Th)など
の放射性元素から放出されるα線により生じると考えら
れる。その防止対策は、例えば特願昭54−50290
号に示される半導体チップ表面にポリイミド系樹脂など
の高分子材料をコーティングする方法あるいは特願昭5
6−70734号に示される半導体基板中にPN接合に
よって区画されたP型ウェル領域を形成してソフトエラ
ーを防止する方法など各種の対策が既に検討されてきて
いる。
So-called soft errors that cause memory to malfunction in semiconductor storage devices are thought to be caused by alpha rays emitted from radioactive elements such as uranium (U) and thorium (Th). For example, Japanese Patent Application No. 54-50290
The method of coating the surface of a semiconductor chip with a polymeric material such as polyimide resin or the patent application of
Various countermeasures have already been considered, such as a method of preventing soft errors by forming P-type well regions partitioned by PN junctions in a semiconductor substrate, as shown in Japanese Patent No. 6-70734.

しかし、宇宙線を地上より強く浴びるロケット塔載用メ
モリや原子炉近辺で使用するメモリは、中性子の影響を
強く受けて、ソフトエラーを発生するであろうことが推
定できる。
However, it can be assumed that memory mounted on rocket towers and memory used near nuclear reactors, which are exposed to cosmic rays more strongly than on the ground, will be strongly affected by neutrons and will generate soft errors.

このような、半導体記憶装置の中性子によるソフトエラ
ーの防止対策については未だ報告されていない。従来か
ら、半導体装置のパッケージ材料やコーティング材料や
封止材料として用いられているアルミナ、シリカ(St
)、セラミック、Mキレート、ポリイミド樹脂などの構
成元素は、中性子との衝突断面積が非常に小さく(例え
ばM3=0.24 barn  、 S i(0゜QQ
lbarn)、中性子によるソフトエラーな防止できな
い。
Measures to prevent such soft errors caused by neutrons in semiconductor memory devices have not yet been reported. Alumina and silica (St
), ceramic, M chelate, polyimide resin, etc., have very small collision cross sections with neutrons (for example, M3=0.24 barn, Si(0°QQ
lbarn), soft errors caused by neutrons cannot be prevented.

〔発明の目的〕[Purpose of the invention]

本発明は半導体装置における中性子によるソフトエラー
の防止という新規な課題を解決することを目的としたも
ので、ソフトエラーによりメモリが誤動作を生じない半
導体装置を提供するものである。
The present invention aims to solve the novel problem of preventing soft errors caused by neutrons in semiconductor devices, and provides a semiconductor device in which a memory does not malfunction due to soft errors.

また、本発明の他の目的ならびに新規な特徴は以下の本
明細書の記述および図面からあきらかになるであろう。
Further, other objects and novel features of the present invention will become apparent from the following description and drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、本発明は、中性子例えば宇宙線中の中性子や
原子炉で発生する中性子を、当該中性子との衝突断面積
の大きいホウ素(+013存在比19.65、当該面積
4017±32 barn )と反応〔10B(”tα
)’Li)させてリチウム()Li)とし、α線に転換
して、中性子によるソフトエラーを防止せんとするもの
である。
That is, the present invention reacts neutrons, such as neutrons in cosmic rays or neutrons generated in nuclear reactors, with boron (+013 abundance ratio 19.65, area 4017±32 barn), which has a large collision cross section with the neutrons [ 10B(”tα
)'Li) to form lithium ()Li) and convert it into alpha rays to prevent soft errors caused by neutrons.

〔実施例〕〔Example〕

本発明の詳細な説明する。 The present invention will be described in detail.

本実施例は半導体装置材料例えばパッ゛ケージ材料中に
ホウ素を含ませ、当該材料中のホウ素1033と中性子
とを接触反応させて、中性子をα線に変換するものであ
る。
In this embodiment, boron is contained in a semiconductor device material, such as a package material, and boron 1033 in the material is brought into contact with neutrons to convert the neutrons into alpha rays.

第1図は本発明による、中性子に関連するソフトエラー
を防止した半導体装置の断面図である。
FIG. 1 is a sectional view of a semiconductor device in which soft errors related to neutrons are prevented according to the present invention.

この半導体装置はメモリ回路や論理回路などが形成され
た半導体チップ1に、ポリイミド系樹脂2を数十μm以
上に厚く被着し、これを包み込むようにホウ素1013
含有のモールドレジン例えばエポキシ樹脂で封止して封
止体30を形成してなる。尚第1図にて、4はリードフ
レームを示し、当該フレームのタブ5には接合材料6を
介して半導体チップ1が接着されている。上記ポリイミ
ド系樹脂としては、例えば日立化成(株)製のPIQ(
登録商標)樹脂が良い。
In this semiconductor device, a polyimide resin 2 is adhered to a thickness of several tens of micrometers or more on a semiconductor chip 1 on which a memory circuit, a logic circuit, etc. are formed, and boron 1013 is applied so as to enclose the polyimide resin 2.
The sealed body 30 is formed by sealing with a mold resin containing, for example, an epoxy resin. In FIG. 1, reference numeral 4 indicates a lead frame, and the semiconductor chip 1 is bonded to a tab 5 of the frame via a bonding material 6. As the polyimide resin, for example, PIQ (manufactured by Hitachi Chemical Co., Ltd.) is used.
(Registered trademark) Resin is good.

次に、モールドレジ/中にホウ素+033を含ませる方
法を説明する。その−例としては、例えば封止材料とし
てのモールドレジン中に酸化ホウ素(820m)を含有
せしめることが例示される。
Next, a method of incorporating boron +033 into the mold register will be explained. An example of this is the inclusion of boron oxide (820m) in a mold resin as a sealing material.

この酸化ホウ素を得るには、後掲の第1表に示すような
ホウ素キレート化合物を使用することが推奨される。ま
ず第1表に示す反応式の左辺に示すように三ハロゲン化
ホウ素と適当なエーテルとを反応させ右辺に示すような
ホウ素キレート化合物を得る。(CxHs)tO・BF
3の沸点は128C。
To obtain this boron oxide, it is recommended to use boron chelate compounds as shown in Table 1 below. First, boron trihalide is reacted with a suitable ether as shown on the left side of the reaction formula shown in Table 1 to obtain a boron chelate compound as shown on the right side. (CxHs)tO・BF
The boiling point of 3 is 128C.

(CzHs)tO・BC4,の融点は56Cと低いので
、ホウ素キレート化合物は低い反応温度で得られる。第
1表に示す化合物はA[キレートのALと似た性質をも
つホウ素のキレート化合物である。
Since the melting point of (CzHs)tO.BC4 is as low as 56C, a boron chelate compound can be obtained at a low reaction temperature. The compounds shown in Table 1 are boron chelate compounds with properties similar to A[chelate AL].

このホウ素キレート化合物は適度な温度処理でB、03
となる。このホウ素キレート化合物をモールドレジンの
原料中に、酸化ホウ素(Btus)の割合が結果的に全
体に対し10〜15%となるように加える。
This boron chelate compound can be converted to B, 03 by moderate temperature treatment.
becomes. This boron chelate compound is added to the raw material of the mold resin so that the proportion of boron oxide (Btus) becomes 10 to 15% based on the total.

ホウ素はレジンとなじみやすくレジンの特性は従来のそ
れと殆んど変らない。
Boron is compatible with resin, and the properties of resin are almost the same as conventional ones.

レジン材料である有機高分子材の主要構成要素であるH
(水素)、C(炭素)、0(酸素)、N(窒素)等は、
中性子との衝突面積が小さく、中性子に対して透明であ
る。また、これ以外の元素も同様である。従って、本実
施例による半導体装置に入射した中性子nは、レジン中
のホウ素10Bと反応し、α線を放出してリチウム丁L
iとなるつ(soB(n、α)?Lす。ホウ素IOBの
中性子との衝突断面積は4017±32 barnと大
きく、中性子は大部分α線となる。このα線はポリイミ
ド系樹脂2に阻止され、半導体チップ1に達することは
ない。
H is the main component of the organic polymer material that is the resin material.
(hydrogen), C (carbon), 0 (oxygen), N (nitrogen), etc.
The collision area with neutrons is small and it is transparent to neutrons. The same applies to other elements. Therefore, the neutrons n incident on the semiconductor device according to this example react with boron 10B in the resin, emit α rays, and lithium ions are released.
i (soB(n, α)?L) The collision cross section of boron IOB with neutrons is as large as 4017±32 bars, and most of the neutrons become α rays. It is blocked and does not reach the semiconductor chip 1.

なお、ホウ素1°Bの同位体であるホウ素11Bの中性
子との衝突断面積は5 m barn (ミリパーン)
と小さい。自然界に存在する天然のホウ素中、ホウ素t
oBは約19.6%を占め、他の大部分はホウ素IIB
である。したがって、上記酸化ホウ素(n*Os)中の
ホウ素も、約19.6%は10B、他はttBである。
Furthermore, the collision cross section of boron 11B, which is an isotope of boron 1°B, with a neutron is 5 mbarn (millipane).
And small. Among the natural boron that exists in nature, boron t
oB accounts for about 19.6%, and most of the rest is boron IIB
It is. Therefore, about 19.6% of the boron in the boron oxide (n*Os) is 10B, and the rest is ttB.

しかし、上述のように両者の衝突断面積は約6桁も異な
るので問題はなく、殆んどの中性子がα線となる。特に
中性子の入射が多いときには、ホウ素を精製しホウ素1
°Bのみを含む酸化ホウ素を用いればよい。
However, as mentioned above, the collision cross sections of the two differ by about six orders of magnitude, so there is no problem, and most neutrons become alpha rays. Especially when there are many neutrons incident, boron is refined and boron 1
Boron oxide containing only °B may be used.

第   1   表 m、p、43C b、p、191c +H++4H,0 +2HC1 〔実施例2〕 第2図はホウ素キレート化合物を含有する高分子樹脂を
ホウ素を含まないエポキシ系レジンよりなる封止体31
表面にオーバーコートして成る半導体装置の断面図であ
り、図中7がオーバーコート層である。図中、第1図と
同一の部分については同一の符号を付してその説明を省
略する。
Table 1 m, p, 43C b, p, 191c +H++4H,0 +2HC1 [Example 2] Figure 2 shows a sealed body 31 made of a polymer resin containing a boron chelate compound and an epoxy resin that does not contain boron.
It is a cross-sectional view of a semiconductor device formed by overcoating the surface, and 7 in the figure is an overcoat layer. In the figure, the same parts as in FIG. 1 are given the same reference numerals, and the explanation thereof will be omitted.

オーバーコート層7は第1表に例示するホウ・素キレー
ト化合物を含有する高分子樹脂をコートした層である。
The overcoat layer 7 is a layer coated with a polymer resin containing a boron chelate compound as shown in Table 1.

このコートした樹脂層を熱処理してほぼ均一な膜厚のB
、0.含有膜を得る。このBtus含有膜により中性子
はα線に転換され、このα線は厚いモールドレジンで阻
止され、半導体チップ1に達することはない。
This coated resin layer is heat-treated to achieve a nearly uniform film thickness.
,0. Obtain a containing membrane. This Btus-containing film converts neutrons into alpha rays, which are blocked by the thick mold resin and do not reach the semiconductor chip 1.

〔効果〕〔effect〕

(1)中性子をホウ素soBと反応させてα線に転換す
ることにより、中性子によるソフトエラーを防止した半
導体装置が得られる。
(1) By reacting neutrons with boron soB and converting them into alpha rays, a semiconductor device that prevents soft errors caused by neutrons can be obtained.

(2)  反応温度の低い化学反応のみで容易にホウ素
toBを半導体装置内に導入できるので、容易かつ安価
な手段で中性子によるソフトエラーを防止できる。
(2) Since boron toB can be easily introduced into a semiconductor device only by a chemical reaction at a low reaction temperature, soft errors caused by neutrons can be prevented with easy and inexpensive means.

(3)中性子が入射した結果書られるα線がチップに達
することのないように、厚い高分子樹脂膜あるいはエポ
キシ樹脂領域を設けているので、前記α線によるソフト
エラーはもちろん、他からのα線によるソフトエラーも
防止できる。
(3) A thick polymer resin film or epoxy resin area is provided to prevent alpha rays written as a result of incident neutrons from reaching the chip, so not only soft errors due to the alpha rays but also α rays from other sources can occur. Soft errors caused by lines can also be prevented.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。
Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

例えば実施例2において、封止体31にB2O3を含有
せしめたり、第1図に示すα線防止層2を形成し℃もよ
い。
For example, in Example 2, the sealing body 31 may contain B2O3, or the α-ray prevention layer 2 shown in FIG. 1 may be formed at a temperature of .degree.

また、封止材料として、他の封止材料例えばセラミック
やガラスエポキシを用いてもよい。
Further, other sealing materials such as ceramic or glass epoxy may be used as the sealing material.

また、半導体チップ上に被着するα線防止材料としてポ
リイミド系合成樹脂を例示したが、他の高分子材料など
であってもよい。
Further, although polyimide-based synthetic resin has been exemplified as the α-ray preventing material to be deposited on the semiconductor chip, other polymeric materials may be used.

〔利用分野〕[Application field]

本発明は、例えば2μm以下のメモリ、3μm以下のメ
モリでロケットなどに搭載用のもの、原子炉近辺での中
性子束密度の高い場所で使用されるものの中性子による
ソフトエラーを防止するのに有効であり、特に50〜1
00Fft以下と現状よりも素子のより低α化が要求さ
れるメモリ素子に有効である。
The present invention is effective in preventing soft errors caused by neutrons in, for example, memories of 2 μm or less, memories of 3 μm or less that are mounted on rockets, or used in places with high neutron flux density near nuclear reactors. Yes, especially 50-1
This is effective for memory devices that require a lower α of 00Fft or less than the current level.

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である半導体装置のメモリ
に適用した場合について説明したが、それに限定される
ものではなく、中性子によるソフトエラーを防止する必
要のある他の記憶媒体に適用しても差支えない。
The above explanation has mainly been about the case where the invention made by the present inventor is applied to the memory of a semiconductor device, which is the field of application that is the background of the invention, but it is not limited to this, and the invention is not limited to this. It may be applied to other storage media as required.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の半導体装置の実施例を示す断面図、 第2図は本発明半導体装置の他の実施例を示す断面図で
ある。 1・・・メモリ回路などが形成された半導体チップ、2
・・・α線防止層(ポリイミド系合成樹脂)、30・・
・酸化ホウ素を含むレジン、31・・・レジン、4・・
・外部リード、5・・・タブリード、6・・・接着材、
7・・・酸化ホウ素を含むオーバーコート層。 代理人 弁理士  高 橋 明 夫
FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the invention, and FIG. 2 is a sectional view showing another embodiment of the semiconductor device of the invention. 1... Semiconductor chip on which a memory circuit etc. is formed, 2
...α-ray prevention layer (polyimide synthetic resin), 30...
・Resin containing boron oxide, 31...Resin, 4...
・External lead, 5...Tab lead, 6...Adhesive material,
7... Overcoat layer containing boron oxide. Agent Patent Attorney Akio Takahashi

Claims (1)

【特許請求の範囲】[Claims] 1、中性子をホウ素と反応させてα線に転換することに
よって中性子によるソフトエラーを防止することを特徴
とする半導体装置。
1. A semiconductor device characterized by preventing soft errors caused by neutrons by reacting neutrons with boron and converting them into alpha rays.
JP8273983A 1983-05-13 1983-05-13 Semiconductor device Granted JPS59208862A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8273983A JPS59208862A (en) 1983-05-13 1983-05-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8273983A JPS59208862A (en) 1983-05-13 1983-05-13 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59208862A true JPS59208862A (en) 1984-11-27
JPH0324785B2 JPH0324785B2 (en) 1991-04-04

Family

ID=13782780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8273983A Granted JPS59208862A (en) 1983-05-13 1983-05-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59208862A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267504A (en) * 1992-03-18 1993-10-15 Shin Etsu Chem Co Ltd Resin composition and semiconductor device sealed or covered with resin composition
US6255719B1 (en) 1998-06-05 2001-07-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including thermal neutron absorption material
JP2008172054A (en) * 2007-01-12 2008-07-24 Sumitomo Bakelite Co Ltd Semiconductor sealing resin composition and semiconductor device
JP2008195756A (en) * 2007-02-08 2008-08-28 Sumitomo Bakelite Co Ltd Resin composition for sealing semiconductor, and semiconductor device
EP2850656A4 (en) * 2012-05-15 2015-11-11 Cypress Semiconductor Corp Soft error resistant circuitry
EP2997595A4 (en) * 2013-05-16 2017-01-25 National Institute Of Aerospace Associates Radiation hardened microelectronic chip packaging technology
US10262951B2 (en) 2013-05-16 2019-04-16 National Institute Of Aerospace Associates Radiation hardened microelectronic chip packaging technology

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Publication number Priority date Publication date Assignee Title
JP7138481B2 (en) * 2018-05-30 2022-09-16 株式会社トクヤマ Hexagonal boron nitride powder and method for producing the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267504A (en) * 1992-03-18 1993-10-15 Shin Etsu Chem Co Ltd Resin composition and semiconductor device sealed or covered with resin composition
US6255719B1 (en) 1998-06-05 2001-07-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including thermal neutron absorption material
JP2008172054A (en) * 2007-01-12 2008-07-24 Sumitomo Bakelite Co Ltd Semiconductor sealing resin composition and semiconductor device
JP2008195756A (en) * 2007-02-08 2008-08-28 Sumitomo Bakelite Co Ltd Resin composition for sealing semiconductor, and semiconductor device
EP2850656A4 (en) * 2012-05-15 2015-11-11 Cypress Semiconductor Corp Soft error resistant circuitry
EP3780090A1 (en) * 2012-05-15 2021-02-17 Cypress Semiconductor Corporation Soft error resistant circuitry
EP2997595A4 (en) * 2013-05-16 2017-01-25 National Institute Of Aerospace Associates Radiation hardened microelectronic chip packaging technology
US10262951B2 (en) 2013-05-16 2019-04-16 National Institute Of Aerospace Associates Radiation hardened microelectronic chip packaging technology

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