JPS59186895U - Display device signal processing circuit - Google Patents

Display device signal processing circuit

Info

Publication number
JPS59186895U
JPS59186895U JP8149783U JP8149783U JPS59186895U JP S59186895 U JPS59186895 U JP S59186895U JP 8149783 U JP8149783 U JP 8149783U JP 8149783 U JP8149783 U JP 8149783U JP S59186895 U JPS59186895 U JP S59186895U
Authority
JP
Japan
Prior art keywords
display device
processing circuit
signal processing
device signal
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8149783U
Other languages
Japanese (ja)
Inventor
曽根田　光生
祐司 林
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP8149783U priority Critical patent/JPS59186895U/en
Publication of JPS59186895U publication Critical patent/JPS59186895U/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は液晶ディスプレイ装置の説明のための
図、第３図は本考案の一例の構成図、第４図はその説明
のための図、第５図は他の例の説明のための図である。 １．２はクランプ回路、１３は利得制御回路、１５はピ
ークホールド回路、１６はボトムホールド回路、１７．
２１は誤差アンプである。Figures 1 and 2 are diagrams for explaining a liquid crystal display device, Figure 3 is a configuration diagram of an example of the present invention, Figure 4 is a diagram for explaining it, and Figure 5 is a diagram for explaining another example. This is a diagram for 1.2 is a clamp circuit, 13 is a gain control circuit, 15 is a peak hold circuit, 16 is a bottom hold circuit, 17.
21 is an error amplifier.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 映像信号のピーク値を保持する手段と、ボトム値を保持
する手段と、上記ボトム値が所定値となるように上記映
像信号のクランプを行う回路と、上記ピーク値とボトム
値との差が所定値となるように上記映像信号の利得制御
を行う回路とを有し、上記クランプ及び利得制御された
信号をディスプレイ装置に供給するようにしたディスプ
レイ装置の信号処理回路。means for holding the peak value of the video signal; means for holding the bottom value; a circuit for clamping the video signal so that the bottom value becomes a predetermined value; a signal processing circuit for a display device, the signal processing circuit comprising: a circuit for performing gain control of the video signal so that the video signal has a fixed value; and supplying the clamped and gain-controlled signal to the display device.
JP8149783U 1983-05-30 1983-05-30 Display device signal processing circuit Pending JPS59186895U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8149783U JPS59186895U (en) 1983-05-30 1983-05-30 Display device signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8149783U JPS59186895U (en) 1983-05-30 1983-05-30 Display device signal processing circuit

Publications (1)

Publication Number Publication Date
JPS59186895U true JPS59186895U (en) 1984-12-11

Family

ID=30211463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8149783U Pending JPS59186895U (en) 1983-05-30 1983-05-30 Display device signal processing circuit

Country Status (1)

Country Link
JP (1) JPS59186895U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63276034A (en) * 1987-05-08 1988-11-14 Hitachi Ltd Liquid crystal display device
JPH05257124A (en) * 1992-03-13 1993-10-08 Hitachi Ltd Liquid crystal display

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63276034A (en) * 1987-05-08 1988-11-14 Hitachi Ltd Liquid crystal display device
JPH05257124A (en) * 1992-03-13 1993-10-08 Hitachi Ltd Liquid crystal display

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