JPS5834453U - SQD circuit - Google Patents

SQD circuit

Info

Publication number
JPS5834453U
JPS5834453U JP12645681U JP12645681U JPS5834453U JP S5834453 U JPS5834453 U JP S5834453U JP 12645681 U JP12645681 U JP 12645681U JP 12645681 U JP12645681 U JP 12645681U JP S5834453 U JPS5834453 U JP S5834453U
Authority
JP
Japan
Prior art keywords
circuit
sqd
data quality
quality display
display signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12645681U
Other languages
Japanese (ja)
Inventor
喜多村 正毅
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP12645681U priority Critical patent/JPS5834453U/en
Publication of JPS5834453U publication Critical patent/JPS5834453U/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Prevention Of Errors In Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例のブロック図、−第2図は従来例による
タイミングチャート、第3図は従来例をマルチポイント
システムに用いた場合の説明図、第4図は本考案の実施
例のブロック図、第5図は本考案の実施例を説明するた
めのタイミングチャートである。 8・・・従来のSQD回路、9・・・積分回路、10・
・・判定器、30・・・保持回路。
Fig. 1 is a block diagram of the conventional example, - Fig. 2 is a timing chart of the conventional example, Fig. 3 is an explanatory diagram when the conventional example is used in a multi-point system, and Fig. 4 is a block diagram of the embodiment of the present invention. FIG. 5 is a timing chart for explaining an embodiment of the present invention. 8... Conventional SQD circuit, 9... Integrating circuit, 10.
... Judgment device, 30... Holding circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] モデムの復号判定時に得られる判定誤差電圧からデータ
品質表示信号を得るSQD回路において、SQD回路本
体の出力側に、受信信号の終端時点のデータ品質表示信
号を保持する保持回路を設けたことを特徴とするSQD
回路。  。
An SQD circuit that obtains a data quality display signal from a judgment error voltage obtained during modem decoding judgment, characterized in that a holding circuit is provided on the output side of the SQD circuit body to hold the data quality display signal at the end of the received signal. SQD to be
circuit. .
JP12645681U 1981-08-28 1981-08-28 SQD circuit Pending JPS5834453U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12645681U JPS5834453U (en) 1981-08-28 1981-08-28 SQD circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12645681U JPS5834453U (en) 1981-08-28 1981-08-28 SQD circuit

Publications (1)

Publication Number Publication Date
JPS5834453U true JPS5834453U (en) 1983-03-05

Family

ID=29920242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12645681U Pending JPS5834453U (en) 1981-08-28 1981-08-28 SQD circuit

Country Status (1)

Country Link
JP (1) JPS5834453U (en)

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