JPS59165460A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS59165460A JPS59165460A JP4023883A JP4023883A JPS59165460A JP S59165460 A JPS59165460 A JP S59165460A JP 4023883 A JP4023883 A JP 4023883A JP 4023883 A JP4023883 A JP 4023883A JP S59165460 A JPS59165460 A JP S59165460A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- layer
- resistance semiconductor
- resistance
- high resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 229910017401 Au—Ge Inorganic materials 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はマイク波帯領域での増巾器、高速論理管２へ婬
々
回路等に用いられる半導体装 関するも である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device used in amplifiers in the microwave band region, high-speed logic tubes 2, and other circuits.
従来例の構成とその問題点
Ｇ ａ Ａ ｔｓの如き化合物半導体は、電子の移動度
が大きい、半絶縁性基板が得られる等の理由で高速。Conventional Structures and Problems Compound semiconductors such as Ga Ats are high-speed because of their high electron mobility and the ability to form semi-insulating substrates.
高周波領域の半導体装置に用いられている。かがる半導
体装置としてはショットキ障壁ゲート型電界効果トラン
ジスタが通常用いられる。ショットキ障壁ゲート型電界
効果トランジスタと同様ＭＩＳ（Ｍｅｔａｌ−Ｉｎｓｕ
ｌａｔｏｒ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ ）型電界効
果トランジスタも高速、高周波領域の半導体装置として
有用なデバイスであるが、Ｇ ａ Ａ ｓの如き化合物
半導体では、単体半導体であるＳｔのＳｉＯ２の如き良
好な絶縁膜が得られていない。Ｇ ａ Ａ ｓを例にと
ると絶縁膜の形成方法として陽極酸化法。Used in semiconductor devices in the high frequency range. A Schottky barrier gate field effect transistor is commonly used as a semiconductor device to be used. Similar to Schottky barrier gate field effect transistors, MIS (Metal-Insuction Transistors)
(lator Sem1conductor) type field effect transistor is also a useful device as a semiconductor device in the high-speed, high-frequency region, but compound semiconductors such as GaAs cannot produce good insulating films such as SiO2 of St, which is an elemental semiconductor. do not have. Taking GaAs as an example, the anodic oxidation method is used to form an insulating film.
プラズマ酸化法、高温酸化法等によるＧ ａ Ａ ｓの
直接酸化、ＣＶＤ法（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ
Ｄｅｐｏｓｉｔｉｏｎ）。Direct oxidation of GaAs by plasma oxidation method, high temperature oxidation method, etc., CVD method (Chemical Vapor
Deposition).
ＰＶＤ法（Ｐｌａｓｍａ Ｖａｐｏｒ Ｄｅｐｏｓｉｔ
ｉｏｎ）等による５ＩＯ２，Ｓｉ３Ｎ４．Ａｌ２Ｏ３等
の堆積が行われている。これらの絶縁膜ばＧ ａ Ａ
ｓとの界面電荷密度が多く、ＭＩＳ型電界効果トランジ
スタとして良好な動作をしない。PVD method (Plasma Vapor Deposit
5IO2, Si3N4. Deposition of Al2O3 etc. is being carried out. These insulating films are G a A
Since the interface charge density with s is high, it does not operate well as a MIS type field effect transistor.
第１図は従来のＭＩＳ型電界効果トランジスタである。FIG. 1 shows a conventional MIS type field effect transistor.
第１図で１は半絶縁性ＧａＡｓ、２はチャネルとなるｎ
千生導体層、３，４はそれぞれソース、ドレイン領域と
なるｎ千生導体層、５はプラズマ酸化法で形成したＧａ
、Ａｓのゲート酸化膜。In Figure 1, 1 is semi-insulating GaAs, and 2 is n, which is the channel.
Senshu conductor layers, 3 and 4 are n Senshu conductor layers that become source and drain regions, respectively, and 5 is Ga formed by plasma oxidation method.
, As gate oxide film.
６．７はソース、ドレイン電極となるべき例えばＡ ｕ
−Ｇ ｅからなるオーミック電極である。８はゲート
電極となるべき例えばＡｌの金属層をそれぞれ示してい
る。6.7 should be the source and drain electrodes, for example A u
- It is an ohmic electrode made of Ge. Reference numeral 8 indicates a metal layer of, for example, Al, which is to serve as a gate electrode.
この様なＭＩＳ型電界効果トランジスタに於ては、Ｇ
ａ Ａ ｓ半導体層２と絶縁膜６との界面での界面電荷
密度が１０１３〜１ｏ１５ＣＩｒＬ−２と多いだめ、高
周波特性で最大発振周波数が向上しない、高速論理回路
等に用いた場合伝播遅延時間の短縮化が困難となる。In such MIS type field effect transistor, G
Since the interfacial charge density at the interface between the a As semiconductor layer 2 and the insulating film 6 is as high as 1013 to 1015CIrL-2, the maximum oscillation frequency cannot be improved in high frequency characteristics, and the propagation delay time will be reduced when used in high-speed logic circuits. It becomes difficult to shorten the length.
発明の目的 を目的とする。purpose of invention With the goal.
発明の構成
本発明は導電性半導体に高抵抗半導体をイオン注入法等
にて形成し、導電性半導体と高抵抗半導体層の界面を利
用することにより、界面電荷密度を減少せしめることに
より良好なＭＩＳ構造を可能とするものである。Structure of the Invention The present invention forms a high-resistance semiconductor on a conductive semiconductor by ion implantation or the like, and utilizes the interface between the conductive semiconductor and the high-resistance semiconductor layer to reduce the interfacial charge density, thereby achieving a good MIS. structure.
実施例の説明
第２図（ａ）〜（ｄ）は本発明の一実施例のＧａＡｓＦ
ＥＴの製造工程の概略図である。DESCRIPTION OF EMBODIMENTS FIGS. 2(a) to 2(d) show GaAsF of an embodiment of the present invention.
It is a schematic diagram of the manufacturing process of ET.
半絶縁性Ｇ ａ Ａ Ｓ基板１１に、選択イオン注入法
を用いて注人種としてＳｌをそれぞれ加速電圧１２０Ｋ
ｅＶ及び１５０ＫｅＶ で注入量３ Ｘ １ ｏ１２ｃ
ｍ ”。Sl was implanted into the semi-insulating GaAs substrate 11 using selective ion implantation at an accelerating voltage of 120K.
Injection dose 3 x 1 o12c at eV and 150KeV
m”.
１０ 儒 注入し、Ａｓ圧下で８５０℃、２０分熱処理
して、チャネル領域となるｎ型半導体層１２゜ソース、
ドレインとなるｎ士卒導体層１３．１４を形成する（ａ
）。The n-type semiconductor layer 12° source,
Form conductor layers 13 and 14 that will become drains (a
).
次に、チャネル領域となるｎ型半導体層ｊ２の表面より
、Ｂを５０ＫｅＶ で５ｘ１．０ｃＩｒＬ イオン注
入し、７０ｏ℃で１０分間熱処理し、半導体層１２の一
部に高抵抗半導体層１５を形成する。この高抵抗半導体
層１５の抵抗は１ｏ〜１ｏΩ−儂であった０））。しか
るのち絶縁膜としてＳ ｉ０２１’ ６をＣＶＤ法を用
いて４ｏ○℃で１０００人堆積する（ｃ）。Next, 5x1.0cIrL ions of B are implanted at 50KeV from the surface of the n-type semiconductor layer j2, which will become the channel region, and heat treated at 70°C for 10 minutes to form a high-resistance semiconductor layer 15 in a part of the semiconductor layer 12. . The resistance of this high-resistance semiconductor layer 15 was 10 to 10Ω-I0)). Thereafter, Si021'6 is deposited as an insulating film using the CVD method at 4°C for 1000 times (c).
次に、Ａｕ−Ｇｅからなる金属を用いてオーミック電極
を形成し、ソース電極１７．ドレイン電極１８とする。Next, an ohmic electrode is formed using a metal made of Au-Ge, and the source electrode 17. This is assumed to be the drain electrode 18.
Ａｌからなるゲート電極１９を設ける（ｄ）。こうして
、ゲート電極１９に印加する電圧により高抵抗半導体層
１６．絶縁膜１６を介して 。A gate electrode 19 made of Al is provided (d). In this way, the voltage applied to the gate electrode 19 causes the high resistance semiconductor layer 16. via the insulating film 16.
半導体層１５の導電度を制御するＭＩＳＦＥＴ を得る
ことができる。
１本発明の電界効果トランジスタは高抵抗半導体層と導
電性半導体層との界面を利用することにより、界面電荷
密度を減少せしめるものである。実 。A MISFET that controls the conductivity of the semiconductor layer 15 can be obtained.
1. The field effect transistor of the present invention reduces the interfacial charge density by utilizing the interface between a high-resistance semiconductor layer and a conductive semiconductor layer. fruit .
流側の界面電荷密度は１ｏ 〜１ｏｃｒｒＬ で従
来 ノ例に比して２〜３桁界面電荷密度Ａ・減少し
だ。界面電荷密度の減少した理由は明らかではないが、
チャネルとなるｎ型半導体層とＢをイオン注入して形成
した高抵抗半導体層とは四−〇 ａ Ａ ｓで組成的に
は連続しており、それにより界面電荷密度が減少すると
考えられる。そして界面電荷密度は高抵抗半導体層の深
い不純物準位に帰因していると考えている。The interfacial charge density on the flow side is 1o to 1ocrrL, which is a decrease of 2 to 3 orders of magnitude A compared to the conventional example. Although the reason for the decrease in interfacial charge density is not clear,
The n-type semiconductor layer serving as the channel and the high-resistance semiconductor layer formed by ion-implanting B are compositionally continuous at 4-0 a As, which is thought to reduce the interfacial charge density. We believe that the interfacial charge density is attributable to the deep impurity level of the high-resistance semiconductor layer.
実施例では基板として半絶縁性Ｇ ａ Ａ ｓで説明し
たが、Ｉｎｐ、ＩｎＧａＡｓ 等を用いても良い。ま
た、チャネル、ソース、ドレイン領域の形成にイオン注
入法を用いたがたとえばＣｒ ドープのエビタクシャ
ル法を用いて形成しても良い。高抵抗半導体１＠の形成
知性人種としてＢを用いたが、Ｈ＋ （プロトン）、Ｃ
ｒ（クローム）、Ｆｅ（鉄）等を用ハても良い。絶縁膜
としてＳ ｉ Ｏ２を用いたがＳｉ３Ｎ４．Ａｌ２Ｏ３
等を用いても良いし、陽極酸化。In the embodiment, semi-insulating GaAs is used as the substrate, but InP, InGaAs, etc. may also be used. Furthermore, although the ion implantation method is used to form the channel, source, and drain regions, they may also be formed using, for example, a Cr doped epitaxial method. B was used as an intelligent species for forming high-resistance semiconductor 1@, but H+ (proton), C
R (chromium), Fe (iron), etc. may also be used. Although SiO2 was used as the insulating film, Si3N4. Al2O3
etc., or anodic oxidation.
司温酸化等の直接酸化法により基板の酸化膜を形成して
も良い。高抵抗半導体層の形成後絶縁膜を杉成しだが、
絶縁膜を形成した後、この絶縁膜を介してイオン注入し
て高抵抗半導体層を形成して、 も良い。又高抵抗半導
体層表面如絶縁膜を形成しだが、高抵抗半導体層の抵抗
値、デバイスの目的によって絶縁膜は形成しなくとも良
い。The oxide film on the substrate may be formed by a direct oxidation method such as cold oxidation. After forming the high-resistance semiconductor layer, an insulating film is formed.
After forming an insulating film, ions may be implanted through the insulating film to form a high-resistance semiconductor layer. Although an insulating film is formed on the surface of the high-resistance semiconductor layer, the insulating film may not be formed depending on the resistance value of the high-resistance semiconductor layer and the purpose of the device.
発明の効果
以上の様に本発明は、チャネルとなる導電性半導体層に
高抵抗層をイオン注入法にて高抵抗半導体層を形成する
ことにより、界面電荷密度の少ない電界効果トランジス
タの形成が可能となり、電界効果トランジスタの最高発
振周波数の向上、高速論理回路の素子として用いた場合
、伝播遅延時間が短縮する等の工業的価値が大きい。Effects of the Invention As described above, the present invention makes it possible to form a field effect transistor with low interfacial charge density by forming a high resistance semiconductor layer by ion implantation in a conductive semiconductor layer that becomes a channel. Therefore, it has great industrial value, such as improving the maximum oscillation frequency of field effect transistors and shortening propagation delay time when used as an element in high-speed logic circuits.
第１図は従来の電界効果トランジスタの模式的な断面図
、第２図（ａ）〜（ｄ）は本発明の一実施例を説明する
だめの電界効果トランジスタの製造工程の概略図である
。
１１・・・・・半絶縁性Ｇ ａ Ａ ｓ基板、１２−・
・・・・チャネルとなるｎ型半導体層、１３・・・−・
ソース領域となる高濃度ｎ型半導体層、１４・・・・・
・ドレイン領域となる高濃度ｎ型半導体層、１５・・・
・・・高抵抗半導体層、１６・・・・・５１０２．１９
・・・・・・ゲート電極。FIG. 1 is a schematic sectional view of a conventional field effect transistor, and FIGS. 2(a) to 2(d) are schematic views of the manufacturing process of a temporary field effect transistor to explain an embodiment of the present invention. 11...Semi-insulating GaAs substrate, 12-...
...N-type semiconductor layer serving as a channel, 13...-
Highly doped n-type semiconductor layer serving as a source region, 14...
・High concentration n-type semiconductor layer, 15... which becomes a drain region
...High resistance semiconductor layer, 16...5102.19
・・・・・・Gate electrode.
Claims (4)
層と、前記導電性半導体層に形成された高抵抗半導体層
と、前記高抵抗半導体層上に形成された導電体とを有し
、前記導電体への印加電圧により前記高抵抗半導体層を
介して前記導電性半導体層の導電度を制御することを特
徴とする半導体装置。(1) having a conductive semiconductor layer formed on a semi-insulating compound semiconductor, a high resistance semiconductor layer formed on the conductive semiconductor layer, and a conductor formed on the high resistance semiconductor layer; A semiconductor device, wherein the conductivity of the conductive semiconductor layer is controlled via the high-resistance semiconductor layer by applying a voltage to the conductor.
とを特徴とする特許請求の範囲第１項に記載の半導体装
置。(2) The semiconductor device according to claim 1, characterized in that an insulating film is interposed between the conductor and the high-resistance semiconductor.
ｇ、１ 成し、前記禽巷徳半導体層にイオン注入法を用いノて高
抵抗半導体層を形成し、前記高抵抗半導体層上に導電体
を形成することを特徴とする半導体装置の製造方法。(3) Forming a conductive semiconductor layer on a semi-insulating compound semiconductor
g.1. A method for manufacturing a semiconductor device, comprising: forming a high-resistance semiconductor layer on the high-resistance semiconductor layer using an ion implantation method; and forming a conductor on the high-resistance semiconductor layer. .
とする特許請求の範囲第３項に記載の半導体装置の製造
方法。(4) The method for manufacturing a semiconductor device according to claim 3, characterized in that an insulating film is formed on the conductive semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4023883A JPS59165460A (en) | 1983-03-10 | 1983-03-10 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4023883A JPS59165460A (en) | 1983-03-10 | 1983-03-10 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59165460A true JPS59165460A (en) | 1984-09-18 |
Family
ID=12575135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4023883A Pending JPS59165460A (en) | 1983-03-10 | 1983-03-10 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59165460A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6196770A (en) * | 1984-10-17 | 1986-05-15 | Nec Corp | Semiconductor device |
| JPH01208867A (en) * | 1988-02-16 | 1989-08-22 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH01251664A (en) * | 1988-03-31 | 1989-10-06 | Nec Corp | Field effect transistor |
-
1983
- 1983-03-10 JP JP4023883A patent/JPS59165460A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6196770A (en) * | 1984-10-17 | 1986-05-15 | Nec Corp | Semiconductor device |
| JPH01208867A (en) * | 1988-02-16 | 1989-08-22 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH01251664A (en) * | 1988-03-31 | 1989-10-06 | Nec Corp | Field effect transistor |
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