GB2137019A - Semiconductor Device and Method for Manufacturing - Google Patents
Semiconductor Device and Method for Manufacturing Download PDFInfo
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- GB2137019A GB2137019A GB08405871A GB8405871A GB2137019A GB 2137019 A GB2137019 A GB 2137019A GB 08405871 A GB08405871 A GB 08405871A GB 8405871 A GB8405871 A GB 8405871A GB 2137019 A GB2137019 A GB 2137019A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 130
- 238000000034 method Methods 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 claims description 3
- 229910001092 metal group alloy Inorganic materials 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 14
- 230000007547 defect Effects 0.000 description 13
- 239000012535 impurity Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000010276 construction Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
In order to lower collector series resistance a semiconductor device including collector 65, 85, base 61, 93, and emitter 63, 89 regions further includes a layer 55, 95 made of a material, such as highly doped polycrystalline silicon, metal alloy or organic conductive material, that differs from that of semiconductor layer 39, 87. <IMAGE>
Description
SPECIFICATION
Semiconductor Device and Method for
Manufacturing the Same
The present invention relates to a semiconductor device provided with an improved high density layer so as to lower the collector series resistance value in the bipolar transistor and a method for manufacturing the semiconductor device.
The conventional NPN type transistor has the construction as shown in Fig. 1, for example.
More specifically, formed on a P type semiconductor substrate 1 is an N type semiconductor layer 3, in which an N type collector region 5, a P type base region 7 and a high density N type emitter region 9 are formed. A high density N type embedded layer 11 is further formed between the semiconductor substrate 1 and the semiconductor layer 3, and a high density layer 1 3 is still further formed extending from the surface of the semiconductor layer 3 to the high density embedded layer 11. The NPN type transistor thus formed is electrically separated from other islands by a separating region 15.
In the case of a semiconductor device having the construction as described above, the high density embedded layer 11 and the high density layer 13 are provided to lower the collector series resistance. Generally, the N type impurity density in the high density layer 13 has surface concentration ranging from 1 019#1 020 cm-3. The high density layer 13 is conventionally formed by thermal diffusion. As shown in Fig. 2, for example, an oxide film (SiO3) 17 which has been formed on a wafer by light etching is removed at its certain area to form an opening 19. A high density N+ material such as POCI3 (phosphorus oxychloride), for example, is then deposited on the wafer at a temperature of 900--1,1000C, as shown in Fig.
3. Thereafter, it is subjected to thermal diffusion in -riitrogen gas at 900-1 ,2O00C to form'the high density layer 13.
In the case of the above described conventional method of forming the high density layer 13, however, crystal defects such as dislocation, precipitation and slip were caused in the vicinity of the high density layer 13 because impurities were diffusion-treated at high temperature. Also in the case of the method of forming the high density layer 13 in such a way that' impurities are thermally-diffused, it was difficult to make the high density layer 13 have a sufficiently low resistance ratio.
Still also in the case where the high density layer 13 is formed after the formation of the base and emitter regions 7 and 9, junction faces between collector and base, and between emitter and base change, as shown by broken lines in Fig.
1 , for example, because of high temperature treatment. This means that control was lacking in the PN junction faces. In addition, yield of the.
semiconductor devices manufactured according to this method dropped because crystal defects appeared and because the PN junction faces
changed. Still also in the case of the semiconductor device manufactured according to the conventional method, that is, the semiconductor device having the high density
layer 13 formed by thermal diffusion in a part of the monocrystal semiconductor layer 3, neither the resistance of the high density layer 13, nor the collector series resistance is small enough. In
addition, crystal defects such as dislocation,
precipitation and slip are present in the vicinity of the high density layer 13. A semiconductor device
having such crystal defects allows the leakage
current to increase.Withstand voltages between
the high density layer 13 and the base region 7,
between the high density layer 13 and the emitter
region 9, and between the islands separated by the isolation region 15 are low. Separation
between these layers, regions and islands is not
sufficient. In addition, the crystal defects can
become a source for generating noise. Further,
because the leakage current increases while the
withstand voltage decreased because of the crystal
defects, it is impossible to form a high density
layer 13 sufficiently adjacent to the base region 7,
thus leading the grade of integration low.
In order to prevent these crystal defects from
being formed, the density of impurities to be
diffused and the temperature at the time of the
diffusion-treatment should be low. If this is done,
however, it will become difficult to lower the
collector series resistance.
The present invention is therefore intended to
eliminate the above-described drawbacks.
An object of the present invention is to provide
a semiconductor device which has small collector
series resistance, which is free from crystal
defects which can cause current to leak, and
which can make both the insulating withstand
voltage and the grade of integration high.
Another object of the present invention is to
provide a method for manufacturing a
semiconductor device which has small collector
series resistance, which is free from crystal
defects, which is uniform in its properties and
which is the grade of integration and yield are
high.
According to the present invention, therefore, a 'semiconductor device comprises: a semiconductor substrate of first conductivity type;
a semiconductor layer of second conductivity type
formed on the semiconductor substrate; a
collector region formed in the semiconductor
layer; a base region formed adjacent to the
collector region in the semiconductor layer; an
emitter region formed in the base region; an
embedded layer of second conductivity type
formed at a certain area between the
semiconductor substrate and the semiconductor
layer; and a high density layer made of a material
different from that of the semiconductor layer and
extending from the surface of the semiconductor
layer at least to the collector region.
According to the present invention, a method
for manufacturing a semiconductor device
comprises: a step of forming an embedded layer of second conductivity type at a certain area in the upper portion of a semiconductor substrate of first conductivity type; a step of forming a semiconductor layer of second conductivity type on the semiconductor substrate and the embedded layer; forming a base region of first conductivity type in said semiconductor layer in such a way that said base region has a surface substantially flush with that of said semiconductor layer, thereby forming a collector region second conductivity type which encloses said base region; forming an emitter region of said second conductivity type in said base region in such a way that the emitter region has a surface substantially flush with that of said base region; forming a groove of a predetermined depth in a specified area of said semiconductor layer, this step being carried after one of said steps of forming a semiconductor layer, forming a base region and forming an emitter region; and depositing material other than that of said semiconductor layer in said groove, this step being carried after said step of forming a groove.
According to the semiconductor device of the present invention, the following effects can be achieved. Any material sufficiently small in its resistance ratio can be selected to form the high density layer, thus enabling the collector series resistance to be made small sufficiently. No crystal defect is caused in the vicinity of high density layer. Therefore, the leakage current between regions or between the collector and the base, for example, in the semiconductor device can be reduced while the withstand voltage therebetween can be increased, thus makeing the semiconductor device more reliable. Because the leakage current is reduced and the withstand voltage is increased, as described above, a high density layer can be formed nearer to the base region, thus enabling the grade of integration to also be improved.
According to the method for manufacturing the semiconductor device, a high density layer can be formed using a material sufficiently small in its resistance ratio, thus enabling the semiconductor device to have a small collector series resistance.
Also according to the method of the present invention, it is unnecessary to form the high density layer by thermal diffusion at a high temperature. Therefore, no crystal defect is caused in the vicinity of the high density layer, thus enabling the yield of the semiconductor devices to be improved. Further, because there are no crystal defects, the high density layer can be formed nearer to the base region providing a semiconductor device which has high integration density. Furthermore, because it is unnecessary to form the high density layer by diffusing impurities at a high temperature, the controllability relating to PN junctions such as those between the emitter and the base, and between the base and the collector can be improved.
This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
Fig. 1 is a sectional view showing the construction of a conventional semiconductor device;
Figs. 2 and 3 are sectional views showing the processes of manufacturing the conventional semiconductor device;
Figs. 4 through 9 are sectional views showing the processes of manufacturing a semiconductor device according to the present invention; Fig.10 is a sectional view showing the construction of a semiconductor device according to the present invention;
Fig. 11 is a graph showing the relationship between frequency and noise figure (NF) obtained by comparing the conventional semiconductor device with one of the present invention;;
Fig. 12 is a sectional view showing a process of another method for manufacturing'the semiconductor device according to the present invention; Fig.13 is a sectional view showing the construction of another semiconductor device according to the present invention;
Fig. 14 is a sectional view showing the process of manufacturing a further example of a semiconductor device according to the present invention; and
Fig. 15 is a sectional view showing the construction of a still further example of a semiconductor device according to the present invention.
An embodiment of the present invention will be described referring to the drawings. In Fig. 4: an N type high density embedded layer 33; and P type high density regions 35, 37 which are formed by diffusion in the upper portion of a P type silicon semiconductor substrate 31. An N type semiconductor layer 39 is grown on them by epitaxial growth, and an oxide film (SiO2) 41 is formed on the semiconductor layer 39. It is assumed that the semiconductor layer 39 is 5 ym thick and resistivity is 1.5-2.0 Q m~'. In order to form the isolation regions under the conditions shown in Fig. 4, the oxide film 41 is photo-etched in certain areas to form openings 43 and 45, as shown in Fig. 5. P type impurities such as boron, for example, are then diffused through the openings 43 and 45 to form the isolation regions 47 and 49, as shown in Fig. 6. Separation may be achieved by other methods such as oxide film separation. The oxide film 41 is selectively photoetched in the area where a high density layer is to be formed to lower the collector series resistance, thus forming an opening 51, as shown in Fig. 7.
Plasma is generated in a mixed gas of, for example, SiCI4, Cl2, and H2, by active ion etching so selectively etch off the semiconductor layer 39,
The oxide film 41 is then used as a mask. A groove 53 is thus formed in the semiconductor layer 39 and under the opening 51. The depth of this groove 53 is substantially the same as the thickness of the semiconductor layer 39; the groove 53 extends to the N type high density embedded layer 33. A material different from the monocrystalline semiconductor layer 39 is then deposited in the groove 53, as shown in Fig. 8.
The material is of a conductivity type. This can be realized depositing polycrystalline silicon material both in the groove 53 and on the oxide film 41 according to chemical vapor deposition (CVD), where said polycrystalline silicon has an N type high density impurity. More specifically, SiH4, (silane) gas, for example, and doping gas (PH3,
AsH3, for example) are flowed at the same time at a temperature of 500-7000C to perform pyrolysis so as to form polycrystalline silicon layers 55 and 57 in which the density of N type impurities is high. Thermal treatment is carried out to make the polycrystalline silicon layer 55 in the groove 53 active electrically. An oxide film is then formed on the polycrystalline silicon layer 57. This oxide film is selectively etched to leave an oxide film 59 on the polycrystalline silicon layer 55.The silicon layer 57 is etched using the oxide film 59 as a resist, as shown in Fig. 9. A Player (base) 61 for the NPN transistor is formed according to the well-known method, as shown in
Fig. 10. An N±layer (emitter) 63 is then formed in the P layer 61. Another region 65 in the semiconductor layer serves as a collector. The base, emitter and collector electrodes 67, 69 and 71 are further formed.
A semiconductor device having such a construction as shown in Fig.10 is manufactured by a series of the above-described processes. In short, the N type silicon semiconductor layer 39 is formed on the P type silicon semiconductor substrate 31. The collector region 65 is formed in the semiconductor layer 39. The P type base region 61 is formed in the upper portion of the collector region 65. The N type high density region 63 is formed, as an emitter, in the base region 61. The N type high density embedded layer 33 is formed between the semiconductor layer 39 and the semiconductor substrate 31 in the lower portion of the collector region 65.The high density layer 55 is made of the polycrystalline silicon to which the N type impurity is added in high density, and the high density layer 55 is formed extending from the surface of the semiconductor layer 39 to the embedded layer 33. The high density layer 55 is different in material from the monocrystalline semiconductor layer 39. The elements which form the NPN type transistor are electrically separated from other islands by P type isolation regions 47 and 49. The surface of the semiconductor layer 39 is coated by the oxide film 41. The base, emitter and collector electrodes 67, 69 and 71 are formed in the base and emitter regions 61. 63 and in the high density layer 55, respectively.
In the case of the bipolar transistor thus formed, the collector series resistance is small because the high density layer 55 of the polycrystalline silicon is deposited in the groove 53. In addition, the high density layer 55 of polycrystalline silicon is formed without diffusing the high density impurity or without heat-treating it at a high temperature, thus preventing crystal defects. Therefore, the leakage current decrease and withstand voltage of the elements can be improved thus resulting in high productivity.
While the conventional yield ranged from 60% to 70% the present invention has improved it to the extent of about 95%.
Noise figure 1/f was compared to the conventional semiconductor device and to the one of the present invention. The results are plotted in Fig. 11. The characteristic represented by (a) in Fig. 11 was obtained from the conventional semiconductor device, while the characteristic represented by (b) in Fig. 11 was obtained from the one of the present invention. The measuring condition was Rg=1 0 KQ and Ic=500 yA. It can be found from Fig. 11 that the characteristics of the semiconductor device of the present invention are better than that of the conventional one.
It should be understood that the method for manufacturing the semiconductor device is not limited to the above-described one. For example in Fig. 12 it may be arranged that the groove 53 is formed after the base and the emitter regions 61 and 63 are formed, and that the high density layer 55 is then formed with polycrystalline silicon.
Formation of the polycrystalline silicon high density layer 55 may be done after the formation of the P-layer (base) 61 at the same time when the polycrystalline silicon high density layer 73 which is used as the material for emitter diffusion is formed.
Although the groove 53 was been formed by reactive ion etching method in the abovedescribed embodiment of the present invention, it may also be formed by ion milling method or wet etching method, for example, said ion milling method being used to etch silicon with ionic nuclides.
Although the N type high density layer 55 of polycrystalline silicon has been formed as a high density layer by CVD, it may also be formed by other methods such as a method plasma excitation, sputtering, or impurity ion injection after the polycrystalline silicon is deposited by
CVD. The high density layer 55 is made of polycrystalline silicon in the groove 53, but aluminum (Al); aluminum and silicon; aluminum, silicon and copper; aluminum and copper; aluminum alloy made of aluminum and deviation metal or the like; molybdenum; molybdenum alloy made of molybdenum and silicide or the like; tungsten; platinum; and other metals may be deposited in the groove 53 by metal CVD, sputtering, evaporating or the like, instead of by high density polycrystalline silicon. Any one of the organic conductive materials may be deposited in the groove 53 by a spin-on manner or the like.
It is unnecessary for the high density layer 55 of polycrystalline silicon to reach the high density embedded layer 33, as shown in Fig. 13. The depth of the high density layer 55 may be selected according to the value of the collector resistance or the like.
Although the present invention has been described as it relates to the NPN type semiconductor device and its manufacturing method, it can be also applied to a PNP type ve tical transistor, for example. A method for manufacturing the PNP type vertical transistor will be described referring to Figs. 14 and 15.
As shown in Fig. 14, an N type high density embedded layer 83 is diffusion-formed in the upper portion of a P type semiconductor substrate 81. A P type high density collector region 85 is diffusion-formed in the high density layer 83. An
N type semiconductor layer 87 is then formed on the semiconductor substrate 81 by epitaxial growth or the like. A P type emitter region 89 is formed in the upper portion of the semiconductor layer 87, as shown in Fig. 1 5. After or before the emitter region 89 is formed, a groove 91 is formed according to the already described manner, extending from the surface of the semiconductor layer 87 to the collector region 85.
The multi-crystal silicon of P type is then deposited in the groove 91 according to the already described manner. Electrodes and others are formed as described above.
As shown in Fig. 1 5, the semiconductor device thus formed has the following construction. The monocrystalline silicon semiconductor layer 87 of
N type is formed on the P type semiconductor substrate 81. The high density embedded layer 83 of N type is formed between the semiconductor substrate 81 and the semiconductor layer 87. The high density collector region 85 of P type is formed in the upper portion of the high density embedded layer 83. A part 93 of the semiconductor layer 87 on the collector region 85 serves as a base region. A
P type emitter region 89 is formed in the upper portion of the base region 93. High density layer 95 of P type is formed extending from the surface of the semiconductor layer 87 to the collector region 85. The high density layer 95 is of polycrystalline silicon and is different in material from the monocrystalline silicon' layer 87. The high density layer 95 is also formed in a circle enclosing the base region 93 in the case of this embodiment. An oxide film 97 is formed on the semiconductpr layer 87. Base, emitter and collector electrodes 99, 101 and 103 are formed ON the base and emitter regions 93, 89 and'in the high density layer 95, respectively; The highdensity layer 95 is not limited to polycrystalline.
silicon of P type, but may be made of any of the above-mentioned metals. It is unnecessary the high density layer 95 to enclose the base region 93, but to enclose it partially.
Claims (18)
1. A semiconductor device comprising:
a semiconductor substrate of first conductivity type;
a semiconductor layer of second conductivity type formed on said semiconductor substrate;
a collector region formed in said semiconductor layer;
a base region formed in contact with said
collector region in said semiconductor layer;
an emitter region formed in said base region;
a embedded layer of second conductivity type
formed in a predetermined region between said
semiconductor substrate and said semiconductor
layer; and
a high density layer in a specified area of said
semiconductor layer extending from the surface
of said semiconductor layer to at least said
collector region and made of material different
from that of said semiconductor layer.
2. A semiconductor device according to claim
1, wherein said first conductivity type is P type,
said second conductivity type is N type, said
collector region is of N type, said base region is
formed in said collector region and is of P type,
said emitter region is of N type, and said high
density layer extends from the surface of said
semiconductor layer to said embedded layer.
3. A semiconductor device according to claim
1, wherein said first conductivity type is P type,
said second conductivty type is N type, said
collector region is formed in the upper portion of said embedded layer and is of P type, said base
region is of N type, said emitter region is of P type, and said high density layer extends from the surface of said semiconductor layer to said collector region.
4. A semiconductor device according to claim
1, wherein said high density layer is made of
polycrystalline silicon.
5. A semiconductor device according to claim 1 , wherein said high density layer is made of
metal.
6. A semiconductor device according to claim
1, wherein said high density layer is made of
organic conductive material.
7. A method for manufacturing a
semiconductor device, comprising the steps of:
forming an embedded layer of second
conductivity type in a semiconductor substrate of first conductivity type in such a way that said
enibedded layer has a surface substantially flush
with that of said semiconductor substrate;
forming a semiconductor layer of second conductivity type on said semiconductor
substrate and embedded layer; forming a base region of first conductiyity type in said semiconductor layer in such a way that said base region has a surface substantialiyflush with that of said semiconductor layer, thereby forming a collector region of second conductivity type which encloses said base region;;
forming an emitter region of said second
conductivity type in said base region in such a# way that the emitter region has a surface
substantially flush with that of said base region;
forming a groove of a predetermined depth in a specified area Of said semiconductor layer, this
step being carried after one of said steps of forming a semiconductor layer, forming a base
region and forming an emitter region; and
depositing material other than that of said semiconductor layer in said groove, this step being carried after said step of forming a groove.
8. A method according to claim 7, wherein said step of forming a groove is reactive ion etching.
9. A method according to claim 7, wherein said step of depositing material is to deposit polycrystalline silicon in said groove.
10. A method according to claim 7, wherein said step of depositing material is to deposit metal in said groove.
11. A method according to claim 7, wherein said step of depositing material is chemical vapor deposition.
12. A method for manufacturing a semiconductor device, comprising the steps of:
forming an embedded layer of second conductivity type in a semiconductor substrate of first conductivity type in such a way that said embedded layer has a surface substantially flush with that of the semiconductor substrate;
forming a collector region of first conductivity type in said embedded layer in such a way that said collector region has a surface substantially flush with that of said embedded layer;
forming a semiconductor layer of second conductivity type on said semiconductor substrate, embedded layer and collector region;
forming an emitter region of first conductivity type in said semiconductor layer in such a way that said emitter region has a surface substantially flush with that of said semiconductor layer;;
forming a groove in a specified area of said semiconductor layer, this step being carried after one of the steps of forming a semiconductor layer and forming an emitter region, said groove extending from the surface of said semiconductor layer to said collector region; and
depositing material other than that of said semiconductor layer in said groove, this step being carried after said step of forming a groove.
13. A method according to claim 12, wherein said step of forming a groove is reactive ion etching.
14. A method according to claim 12, wherein said step of depositing material is to deposit polycrystalline silicon in said groove.
15. A method according to claim 12, wherein said step of depositing material is to deposit metal in said groove.
16. A method according to claim 12, wherein said step of depositing material is chemical vapor deposition.
17. A semiconductor device, substantially as hereinbefore described with reference to the Figs.
10,11,13 and 15 of the accompanying drawings.
18. A method for manufacturing a semiconductor device, substantially as hereinbefore described with reference to the Figs.
4 to 15 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3954283A JPS59165455A (en) | 1983-03-10 | 1983-03-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8405871D0 GB8405871D0 (en) | 1984-04-11 |
| GB2137019A true GB2137019A (en) | 1984-09-26 |
Family
ID=12555937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08405871A Withdrawn GB2137019A (en) | 1983-03-10 | 1984-03-06 | Semiconductor Device and Method for Manufacturing |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS59165455A (en) |
| DE (1) | DE3408552A1 (en) |
| GB (1) | GB2137019A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2181889A (en) * | 1985-10-19 | 1987-04-29 | Plessey Co Plc | Improvements relating to bipolar transistors |
| EP0460861A2 (en) * | 1990-05-31 | 1991-12-11 | Canon Kabushiki Kaisha | Device separation structure and semiconductor device improved in wiring structure |
| GB2245425A (en) * | 1990-06-22 | 1992-01-02 | Gen Electric Co Plc | A verticle pnp transistor |
| CN109643686A (en) * | 2016-06-23 | 2019-04-16 | 力特保险丝公司 | The semiconductor devices of trench plug with side diffusion |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166071A (en) * | 1985-01-17 | 1986-07-26 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS63215068A (en) * | 1987-03-04 | 1988-09-07 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
| JPH04123076U (en) * | 1991-04-24 | 1992-11-06 | 船井電機株式会社 | parallel jumper wire |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1460124A (en) * | 1974-01-03 | 1976-12-31 | Motorola Inc | Integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector including fabrication method therefor |
| GB1534896A (en) * | 1975-05-19 | 1978-12-06 | Itt | Direct metal contact to buried layer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA928863A (en) * | 1970-01-19 | 1973-06-19 | Rca Corporation | Semiconductor integrated circuit device |
| DE2106540A1 (en) * | 1970-02-13 | 1971-08-19 | Texas Instruments Inc | Semiconductor circuits and processes for their manufacture |
| US3847687A (en) * | 1972-11-15 | 1974-11-12 | Motorola Inc | Methods of forming self aligned transistor structure having polycrystalline contacts |
-
1983
- 1983-03-10 JP JP3954283A patent/JPS59165455A/en active Pending
-
1984
- 1984-03-06 GB GB08405871A patent/GB2137019A/en not_active Withdrawn
- 1984-03-08 DE DE19843408552 patent/DE3408552A1/en not_active Ceased
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1460124A (en) * | 1974-01-03 | 1976-12-31 | Motorola Inc | Integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector including fabrication method therefor |
| GB1534896A (en) * | 1975-05-19 | 1978-12-06 | Itt | Direct metal contact to buried layer |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2181889A (en) * | 1985-10-19 | 1987-04-29 | Plessey Co Plc | Improvements relating to bipolar transistors |
| EP0460861A2 (en) * | 1990-05-31 | 1991-12-11 | Canon Kabushiki Kaisha | Device separation structure and semiconductor device improved in wiring structure |
| EP0460861A3 (en) * | 1990-05-31 | 1992-09-02 | Canon Kabushiki Kaisha | Device separation structure and semiconductor device improved in wiring structure |
| US5200639A (en) * | 1990-05-31 | 1993-04-06 | Canon Kabushiki Kaisha | Semiconductor device with isolating groove containing single crystalline aluminum wiring |
| US5665630A (en) * | 1990-05-31 | 1997-09-09 | Canon Kabushiki Kaisha | Device separation structure and semiconductor device improved in wiring structure |
| GB2245425A (en) * | 1990-06-22 | 1992-01-02 | Gen Electric Co Plc | A verticle pnp transistor |
| CN109643686A (en) * | 2016-06-23 | 2019-04-16 | 力特保险丝公司 | The semiconductor devices of trench plug with side diffusion |
| EP3475974A4 (en) * | 2016-06-23 | 2020-03-04 | Littelfuse, Inc. | Semiconductor device having side-diffused trench plug |
| US10943975B2 (en) | 2016-06-23 | 2021-03-09 | Littelfuse, Inc. | Method of manufacturing a semiconductor device having side-diffused trench plug |
| US11688763B2 (en) | 2016-06-23 | 2023-06-27 | Littelfuse, Inc. | Semiconductor device having side-diffused trench plug |
| CN109643686B (en) * | 2016-06-23 | 2023-08-29 | 力特保险丝公司 | Semiconductor device with laterally diffused trench plugs |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8405871D0 (en) | 1984-04-11 |
| DE3408552A1 (en) | 1984-09-20 |
| JPS59165455A (en) | 1984-09-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |