JPS59161014A - Crystallization of semiconductor thin film - Google Patents

Crystallization of semiconductor thin film

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Publication number
JPS59161014A
JPS59161014A JP58034890A JP3489083A JPS59161014A JP S59161014 A JPS59161014 A JP S59161014A JP 58034890 A JP58034890 A JP 58034890A JP 3489083 A JP3489083 A JP 3489083A JP S59161014 A JPS59161014 A JP S59161014A
Authority
JP
Japan
Prior art keywords
width
main body
thin film
region
region part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58034890A
Other languages
Japanese (ja)
Inventor
Masafumi Shinpo
新保　雅文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP58034890A priority Critical patent/JPS59161014A/en
Publication of JPS59161014A publication Critical patent/JPS59161014A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02425—Conductive materials, e.g. metallic silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Abstract

PURPOSE:To contrive to enhance performance, and to reduce cost of a semiconductor thin film by a method wherein the island type semiconductor thin film consisting of an additional region part and a main body region part is formed, a beam is projected at first to the additonal region to convert into a single crystal, and the main body region part is crystallized in succession. CONSTITUTION:A semiconductor device such as TFT, etc. is formed in the future in a main body region part 2, and a sufficient area necessary therefore is provided thereto. An additional region part 3 has sufficiently narrow width W to facilitate conversion into a single crystal when it is recrystallized, and moreover has sufficient length L to reduce a thermal influence to be generated owing to existence of the main body part 2. The narrower width W becomes, the more it is desirable, and width is selected typically to 5mum or less, length L is to width W or more, and moreover desirably 10mum or more is selected. This device is applied to a system wherein after a converged laser beam 10 is scanned in a high speed in the (x) direction, the beam is displaced smaller than beam width D in the (y) direction, and scanned in a high speed in parallel with the (x) axis again. In any case, it is necessary to form arrangement as to make the additional region part 3 to be annealed faster than the main body region part 2.

Description

【発明の詳細な説明】 本発明は、半導体薄膜トランジスタ（以下１”ＦＴと称
す）を有する巣積回路中のＴＦＴサイズの島状半導体薄
膜を結晶化する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for crystallizing a TFT-sized island-shaped semiconductor thin film in a stacked circuit having semiconductor thin film transistors (hereinafter referred to as 1"FT).

従来、絶縁物基板上の半導体薄膜の結晶化方法は、主に
レーザ、電子線、ランプ、ヒーター等のビームアニール
技術を利用したグラフオ・エピタキシー、グレイン成長
、ブリッジングエビタキシー、ＳＯＳなどがある。グラ
フオ・エピタキシーは、基板に周期的な凹凸（レリーフ
）を設けて、再結晶核の安定位置を与えかつ方位をそろ
えて薄膜を単結晶化しようとするものである。この方法
では、基板に凹凸を設ける工程が必要であり、薄膜表面
に凹凸を生じてしまう。また、ブリッジングエビタキシ
ーは、単結晶基板上に開孔を有する絶縁膜を設け、その
上の薄膜を開孔部の基板を種結晶として結晶化するもの
であるが、基板には単結晶材料を用いなければならない
。さらに５ＯＳ（５ｉｌｉｃｏｎ　ｏｎ　５ａｐｐｈｉ
ｒｅまたは５ｐｉｎｅｌ　）　　では、基板に高価なサ
ファイアやスピネルの単結晶基板を必要とする。Conventionally, methods for crystallizing semiconductor thin films on insulating substrates include grapho-epitaxy, grain growth, bridging epitaxy, SOS, etc., which mainly utilize beam annealing techniques such as laser, electron beam, lamp, and heater. Grapheo-epitaxy is a technique in which periodic reliefs are provided on a substrate to provide stable positions for recrystallized nuclei and to align their orientations to form a thin film into a single crystal. This method requires a step of providing unevenness on the substrate, resulting in unevenness on the surface of the thin film. Bridging epitaxy is a method in which an insulating film with holes is provided on a single-crystal substrate, and a thin film on top of the insulating film is crystallized using the substrate in the hole as a seed crystal. must be used. Furthermore, 5OS (5ilicon on 5apphi
(re or 5pinel) requires an expensive single crystal substrate of sapphire or spinel.

これらに対し、グレイン成長は溶融石英やガラスなど非
晶質の基板を用いること力りでき、かつ表面は平担でよ
い。しかし、単に平担な基板上の半導体薄膜をビームア
ニールしただけでは単結晶膜にはならない。そこで、種
々の方法が試みられている。例えば、基板（Ｓｉｎ２／
Ｓｉ単結晶）全面に堆積した多結晶８１層を０ＷＡｒレ
ーザでアニールすると、粒径が数μｍ以上になるのに対
し、多結晶層を島状にすると２×２０μ情２の場合には
単結晶、２５Ｘ２５μ惧２以上では数μ情の粒径になる
（　Ａｐｐｌｉｅｄ　Ｐｈｙｓ　Ｌｅｔｔｅｒｓ　　５
３巻７７５頁　１９７８年及び６４巻８３１頁　１９７
９年）。また、ヒーターやランプを用いた帯域溶融法に
おいては、基板上の８１薄膜を端から数圏の単結晶層を
得ている。（例えば、ＡｐｐｌｉｅｄＰｈｙｓ　Ｌｅｔ
ｔｅｒｓ　　３７巻　４５４頁　１２８０年及び４１巻
　８２４頁　１２層２年）しかし、これら帯域溶融法で
は基板を１０００〜１２００℃に予熱しておくため、低
融点のガラス基板の如きものは使えない。さらに、三次
元集積回路に適用しようとすれば、基板内につくられた
不純物添加領域が大きく再分布してしまう。In contrast, grain growth can be achieved by using an amorphous substrate such as fused silica or glass, and the surface may be flat. However, simply beam annealing a semiconductor thin film on a flat substrate does not result in a single crystal film. Therefore, various methods have been tried. For example, the board (Sin2/
When a polycrystalline 81 layer deposited on the entire surface (Si single crystal) is annealed with a 0 WAr laser, the grain size becomes several μm or more, whereas when the polycrystalline layer is made into an island shape, it becomes a single crystal in the case of 2×20 μm. , 25×25 μm or more, the particle size becomes several μ (Applied Phys Letters 5
Volume 3, page 775, 1978 and Volume 64, page 831, 197
9 years). In addition, in the zone melting method using a heater or a lamp, a single crystal layer of several circles from the edge of the 81 thin film on the substrate is obtained. (For example, AppliedPhys Let
ters, Vol. 37, p. 454, 1280 and Vol. 41, p. 824, 12 layers, 2 years) However, in these zone melting methods, the substrate is preheated to 1000 to 1200° C., so materials such as glass substrates with low melting points cannot be used. Furthermore, when applied to three-dimensional integrated circuits, the impurity doped regions created within the substrate will be significantly redistributed.

本発明は、以上の様な状況に鑑みなされたもので、特に
島状薄膜のグレイン成長方法を改善するものである。本
発明では、特に小さな島状薄膜が溶融再結晶によって単
結晶化することを利用し、それを種結晶として大きな島
状薄膜を結晶化するものである。そのため、本発−明に
おいては半導体薄膜を島状にする際、幅が充分狭い小面
積の領域（付加領域部）と面積の大きい本体領域部から
成る島状半導体薄膜とし、ビームアニール等で溶融再結
晶する場合に付加領域に先にビームを照射し単結晶化し
、引き続いて横方向エピタキシーを利用して本体領域部
を結晶化するものである。The present invention was made in view of the above-mentioned circumstances, and particularly aims to improve the method of growing grains in island-shaped thin films. In the present invention, a particularly small island-like thin film is made into a single crystal by melt recrystallization, and this is used as a seed crystal to crystallize a large island-like thin film. Therefore, in the present invention, when forming a semiconductor thin film into an island shape, the island-shaped semiconductor thin film is made up of a small area (additional area) with a sufficiently narrow width and a main body area with a large area, and is melted by beam annealing or the like. When recrystallizing, the additional region is first irradiated with a beam to form a single crystal, and then the main region is crystallized using lateral epitaxy.

以下に図面を用いて本発明を詳述する。第１図には、本
発明の実施例が模式的に平面図で示される。第１図（α
）では、島状半導体薄膜（例えば非晶質Ｓ１・・・α−
８１）１は幅Ｗ、長さ−の付加領域部３と幅Ｗ。をもつ
本体領域部２から成り、直径モジくはビーム幅りをもつ
アニール用ビーム１０がＸ方向に走査される例が示され
ている。島状α−８１膜１は、酸化膜（Ｓｉｎ２）や窒
化膜（８１ｇＮ４）等絶縁物で表面を被覆されたＳｌや
金属、または石英、ガラス、セラミックス、等絶縁物の
基板上に衆知のフォトリソグラフィ等で形成される。本
体領域部２には将来ＴＰＴ等の半導体デバイスが形成さ
れ、それに必要な充分の面積をもっている。付加領域部
６は、再結晶化する際単結晶となりやすくするため充分
狭い幅Ｗをもち、かつ本体領域部２があるための熱的影
響を少なくするため充分な長さＬを有している。幅Ｗは
狭い程望ましく、典型的には５μ形以下、長さＬは幅Ｗ
以上、さらに望ましくは１０層餌以上が選ばれる。勿論
幅Ｗは、ビーム幅りより狭いが、本体領域部２の幅Ｗ０
は必ずしもビーム幅りよりも狭い必要はない。第１図（
α）の例は、例えば絞られたレーザ・ビーム１０がＸ方
向に高速で走査された後、ｙ方向にビーム幅りよりも小
さく変位して再びＸ軸と平行に高速走査する方式に適用
して本発明の効果が大きい場合であ、る。とにかく付加
領域部３が本体領域部２よりも早くアニールされる様な
配置をとる必要がある。第１１ｆｆｌ（Ａ）は、第１図
（α）と同様方式のビームアニールに適用した例であり
、本体領域部２と付加領域部３の間に幅が徐々に変化す
る領域４を設けたものである。第１図（Ｃ，）は、ビー
ム幅りに対し本体領域部２の幅Ｗ。が小さいときには、
付加領域部３は本体領域部２の幅方向の中央部近くにつ
けられることを示す。The present invention will be explained in detail below using the drawings. FIG. 1 schematically shows an embodiment of the invention in a plan view. Figure 1 (α
), island-shaped semiconductor thin films (e.g. amorphous S1...α-
81) 1 is the width W, the length - of the additional area portion 3 and the width W. An example is shown in which an annealing beam 10 consisting of a main body region 2 having a diameter and a beam width varying in diameter is scanned in the X direction. The island-like α-81 film 1 is formed by forming a well-known photo film on a substrate of an insulating material such as Sl, metal, quartz, glass, ceramics, etc. whose surface is coated with an insulating material such as an oxide film (Sin2) or a nitride film (81gN4). It is formed by lithography or the like. The main body region 2 will be formed with a semiconductor device such as a TPT in the future, and has a sufficient area for this purpose. The additional region 6 has a sufficiently narrow width W to easily form a single crystal during recrystallization, and has a sufficient length L to reduce the thermal influence due to the main body region 2. . The narrower the width W, the more desirable it is, typically 5μ or less, and the length L is the same as the width W.
More preferably, a bait with 10 layers or more is selected. Of course, the width W is narrower than the beam width, but the width W0 of the main body region 2
does not necessarily have to be narrower than the beam width. Figure 1 (
Example α) is applied, for example, to a method in which a focused laser beam 10 is scanned at high speed in the X direction, then displaced in the y direction by a smaller amount than the beam width, and then scanned again at high speed in parallel to the X axis. This is the case where the effect of the present invention is large. In any case, it is necessary to take an arrangement in which the additional region 3 is annealed faster than the main region 2. 11ffl (A) is an example in which the same method as in FIG. 1 (α) is applied to beam annealing, and a region 4 whose width gradually changes is provided between the main body region 2 and the additional region 3. It is. FIG. 1 (C,) shows the width W of the main body region 2 relative to the beam width. When is small,
The additional area 3 is shown to be attached near the center of the main body area 2 in the width direction.

第２図には、Ｘ軸方向にビームを高速走査し、ｙ方向に
ステップまたは低速走査する場合、島状領域１の左右ど
ちら側からビームが走査されても本発明の目的を達成で
きる例を示した。第２図（α）は、本体領域部２の両側
のＸ軸方向に延在する様に２つの付加領域部３，３′を
設けた例、第２図（ｂ）はさらに付加領域部６．３′の
幅を徐々にかえた例である。FIG. 2 shows an example in which the object of the present invention can be achieved regardless of whether the beam is scanned from either the left or right side of the island-like area 1 when the beam is scanned at high speed in the X-axis direction and scanned in steps or at low speed in the y direction. Indicated. FIG. 2(α) shows an example in which two additional regions 3 and 3' are provided so as to extend in the X-axis direction on both sides of the main body region 2, and FIG. 2(b) shows an example in which additional regions 6 This is an example in which the width of .3' is gradually changed.

第３図では、付加領域６をさらに種結晶形成領域６αと
結合領域３ｈ（種結晶形成領域６αと本体領域部２の間
の連結）とから成り立たせた例が示される。第３図（ａ
）では、種結晶形成領域３αは幅’１＋”２としてビー
ム幅り及び本体領域部２の幅Ｗ０より狭く、かつ単結晶
化しゃすい様極力小面積であり、また結合領域３ｂは前
記Ｗ１より細い幅で長さＬより成る例を示した。結合領
域３ｂは、種結晶形成領域６αの単結晶化に本体領域部
２が影響を与えない様に設けたものである。種結晶形成
領域６αは極力小面積になる様に、例えば５μ惜×５μ
情に選ばれ、結合領域６ｈの幅は２μｍ、長さ１０μ情
程度に選ばれる。FIG. 3 shows an example in which the additional region 6 further includes a seed crystal forming region 6α and a coupling region 3h (connection between the seed crystal forming region 6α and the main body region portion 2). Figure 3 (a
), the seed crystal forming region 3α has a width of '1+'2, which is narrower than the beam width and the width W0 of the main body region 2, and has an area as small as possible to facilitate single crystallization, and the bonding region 3b has a width of '1+'2, which is smaller than the width W0 of the main body region 2. An example is shown in which the bonding region 3b has a narrow width and a length L.The bonding region 3b is provided so that the main body region 2 does not affect the single crystallization of the seed crystal forming region 6α.The seed crystal forming region 6α For example, 5μ x 5μ so that the area is as small as possible.
The width of the bonding region 6h is selected to be approximately 2 μm, and the length is approximately 10 μm.

第３図Ｃｂ）の例では、結合領域３ｂに幅の傾斜をもた
せている。この様にすれば、さらに種結晶形成領域３α
の単結晶化が容易である。In the example shown in FIG. 3Cb), the bonding region 3b has a width slope. In this way, the seed crystal formation region 3α
single crystallization is easy.

第４図は、本発明を応用した例を示し、複数の本体領域
２，１２，２２，３２．・・・・・・が付加領域５．１
′５，２３，３３．・・・・・・をそれぞれ有し、かつ
互いにＸ軸（スキャン方向）に連結している。FIG. 4 shows an example in which the present invention is applied, in which a plurality of main body regions 2, 12, 22, 32 . ...is the additional area 5.1
'5, 23, 33. . . . and are connected to each other in the X axis (scanning direction).

ビームアニールで形成された最初の付加領域６（または
６′）の結晶面、結晶方向は全本体領域２、・・・・・
・、３２．・・・・・・で同じにできる利点を有す。The crystal plane and crystal direction of the first additional region 6 (or 6') formed by beam annealing are the entire main body region 2,...
・, 32. It has the advantage that it can be made the same with...

しかも細い付加領域１３，２３，３３．・・・・・・の
存在のため、たとえ１つの本体領域に欠陥が生じても、
他の本体領域に伝播しにくいことも他の利点である。Moreover, the thin additional areas 13, 23, 33. Due to the existence of..., even if a defect occurs in one body area,
Another advantage is that it is less likely to propagate to other body regions.

第５図は、ビーム幅りが充分広いとき、例えばランプや
ヒーター等による帯域溶融法の場合に適用した例を示す
。この場合、ビーム幅りは充分広いので、付加領域３の
長さ方向とスキャン方向（Ｘ方向）は必ずしも平行であ
る必要はなく１また矩形の本体領域２の各端部もスキャ
ン方向と平行または直角である必要は必ずしもない。即
ち、ビーム幅りが島状領域１の大きさに比し充分大きけ
れば、第１図から第４図の例においても、Ｘ軸と平行に
ビーム走査する必要がないことを示した。FIG. 5 shows an example of application when the beam width is sufficiently wide, for example, in the case of a zone melting method using a lamp or a heater. In this case, since the beam width is sufficiently wide, the length direction of the additional area 3 and the scan direction (X direction) do not necessarily have to be parallel, and each end of the rectangular main body area 2 may also be parallel to or parallel to the scan direction. It does not necessarily have to be a right angle. That is, it has been shown that if the beam width is sufficiently large compared to the size of the island region 1, there is no need to scan the beam parallel to the X axis even in the examples shown in FIGS. 1 to 4.

以上の様に本発明によれば、島状薄膜領域１がたとえ２
５Ｘ２５μｆＩＬ２より大面積でも容易に単結晶化でき
ること、アニール用のビーム径が小さくても基板上の全
島状薄膜を単結晶化可能なこと、また本発明適用におい
て従来工程より工数は増えないこと等の利点をもつ。以
上の実施例においては、特に半導体薄膜上にキャップと
称する絶縁膜を設ける例を示さなかったが、これは勿論
利用できる。半導体薄膜としてα−８１を例にとったが
、多結晶Ｓ１膜、他の半導体材料例えばＧｏ。As described above, according to the present invention, even if the island-like thin film region 1 is
It is possible to easily form a single crystal even in a larger area than 5X25μf IL2, it is possible to form a single crystal of the entire island-shaped thin film on the substrate even if the beam diameter for annealing is small, and the number of man-hours does not increase compared to the conventional process when applying the present invention. have advantages. In the above embodiments, an example in which an insulating film called a cap was not particularly provided on the semiconductor thin film was not shown, but this can of course be used. Although α-81 is used as an example of the semiconductor thin film, polycrystalline S1 films and other semiconductor materials such as Go may also be used.

ＧａＡｓ等ｍ−ｖ化合物、ＩＩ−ＶＩ化合物にも適用さ
れる。本発明で設けた付加領域部３は、デバイス製作に
おいては配線の一部等に利用できるし、場合によっては
除去してもよいので、格別の不都合は生じない。It is also applied to m-v compounds such as GaAs and II-VI compounds. The additional area portion 3 provided in the present invention can be used as a part of wiring in device manufacturing, and may be removed depending on the case, so no particular inconvenience occurs.

本発明は、上記の如く簡単な方法で絶縁物上に結晶薄膜
が得られるので、半導体装置の性能向上、低価格化に大
きく寄与する。The present invention makes it possible to obtain a crystal thin film on an insulator using a simple method as described above, and thus greatly contributes to improving the performance and reducing the cost of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（α）から（Ｃ）、第２図（α）と（ｂ）、第６
５図（α）と（ｂ）、第４図及び第５図はそれぞれ本発
明の詳細な説明するための模式的平面図である。 １・・・・・・島状半導体薄膜領域 ２・・・・・・本体領域部 ６・・・・・・付加領域部 １０・・・ビーム Ｘ・・・・・・ビーム主走査軸 以上 出願人　株式会社第二精工舎 代理人　弁理士　最上　　務Figure 1 (α) to (C), Figure 2 (α) and (b), Figure 6
FIGS. 5(α) and 5(b), FIGS. 4 and 5 are schematic plan views for explaining the present invention in detail, respectively. 1... Island semiconductor thin film region 2... Main body region 6... Additional region 10... Beam X... Beam main scanning axis or above application Person Daini Seikosha Co., Ltd. Agent Patent Attorney Tsutomu Mogami

Claims (1)

【特許請求の範囲】 （１）　　少なく共表面が絶縁物よりなる基板上に、本
体領域部と、該領域部より幅が狭く該領域部に連続する
付加領域部とから成る島状半導体薄膜領域を形成する工
程と、前記薄膜領域をビームでアニール走査して結晶化
する際に前記付加領域部の幅よりも広いビーム幅で、し
かも前記付加領域部を前記本体領域部より先に前記ビー
ムで照射する工程とより成る半導体薄膜結晶化方法。 （２）　　前記付加領域の幅が５μ倶以下、長さが前記
幅以上であることを特徴とする特許請求の範囲第１項記
載の半導体薄膜結晶化方法。 （８）前記薄膜領域が複数個あり、前記付加領域によっ
て互いに連結されていることを特徴とする特許請求の範
囲第１項あるいは第２項記載の半導体薄膜結晶化方法。[Scope of Claims] (1) An island-shaped semiconductor thin film region consisting of a main body region and an additional region narrower in width than the region and continuous to the region, on a substrate whose co-surfaces are made of an insulator. When the thin film region is annealed and scanned with a beam for crystallization, the beam width is wider than the width of the additional region, and the additional region is irradiated with the beam before the main body region. A semiconductor thin film crystallization method comprising a step of irradiation. (2) The semiconductor thin film crystallization method according to claim 1, wherein the width of the additional region is 5 μm or less, and the length is greater than or equal to the width. (8) A method for crystallizing a semiconductor thin film according to claim 1 or 2, wherein there are a plurality of thin film regions and the thin film regions are connected to each other by the additional region.
JP58034890A 1983-03-03 1983-03-03 Crystallization of semiconductor thin film Pending JPS59161014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58034890A JPS59161014A (en) 1983-03-03 1983-03-03 Crystallization of semiconductor thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58034890A JPS59161014A (en) 1983-03-03 1983-03-03 Crystallization of semiconductor thin film

Publications (1)

Publication Number Publication Date
JPS59161014A true JPS59161014A (en) 1984-09-11

Family

ID=12426748

Family Applications (1)

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JP58034890A Pending JPS59161014A (en) 1983-03-03 1983-03-03 Crystallization of semiconductor thin film

Country Status (1)

Country Link
JP (1) JPS59161014A (en)

Cited By (15)

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JPS61202418A (en) * 1985-03-05 1986-09-08 Hitachi Ltd Formation of thin film semiconductor element
WO1999031719A1 (en) * 1997-12-17 1999-06-24 Matsushita Electric Industrial Co., Ltd. Semiconductor thin film, method of producing the same, apparatus for producing the same, semiconductor device and method of producing the same
US6057183A (en) * 1994-04-22 2000-05-02 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of drive circuit of active matrix device
US6096581A (en) * 1994-03-09 2000-08-01 Semiconductor Energy Laboratory Co., Ltd. Method for operating an active matrix display device with limited variation in threshold voltages
US6496171B2 (en) 1998-01-23 2002-12-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
US6538632B1 (en) 1998-04-28 2003-03-25 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor circuit and a semiconductor display device using the same
US6549184B1 (en) 1998-03-27 2003-04-15 Semiconductor Energy Laboratory Co., Ltd. Driving circuit of a semiconductor display device and the semiconductor display device
US6723590B1 (en) 1994-03-09 2004-04-20 Semiconductor Energy Laboratory Co., Ltd. Method for laser-processing semiconductor device
US6831299B2 (en) 2000-11-09 2004-12-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US6872607B2 (en) 2000-03-21 2005-03-29 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
JP2005347765A (en) * 1999-08-31 2005-12-15 Sharp Corp Semiconductor device and manufacturing method therefor, and method of forming silicon thin film
JP2007067431A (en) * 2001-08-30 2007-03-15 Sharp Corp Semiconductor device
US7205184B2 (en) * 1997-10-14 2007-04-17 Samsung Electronics Co., Ltd. Method of crystallizing silicon film and method of manufacturing thin film transistor liquid crystal display
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57180118A (en) * 1981-04-30 1982-11-06 Toshiba Corp Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57180118A (en) * 1981-04-30 1982-11-06 Toshiba Corp Manufacture of semiconductor device

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JPS61202418A (en) * 1985-03-05 1986-09-08 Hitachi Ltd Formation of thin film semiconductor element
US6509212B1 (en) 1994-03-09 2003-01-21 Semiconductor Energy Laboratory Co., Ltd. Method for laser-processing semiconductor device
US6723590B1 (en) 1994-03-09 2004-04-20 Semiconductor Energy Laboratory Co., Ltd. Method for laser-processing semiconductor device
US6096581A (en) * 1994-03-09 2000-08-01 Semiconductor Energy Laboratory Co., Ltd. Method for operating an active matrix display device with limited variation in threshold voltages
US7027022B2 (en) 1994-04-22 2006-04-11 Semiconductor Energy Laboratory Co., Ltd. Drive circuit of active matrix type display device having buffer with parallel connected elemental circuits and manufacturing method thereof
US6057183A (en) * 1994-04-22 2000-05-02 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of drive circuit of active matrix device
US7015057B2 (en) 1994-04-22 2006-03-21 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a drive circuit of active matrix device
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US8450743B2 (en) 1994-08-19 2013-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having parallel thin film transistors
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US7205184B2 (en) * 1997-10-14 2007-04-17 Samsung Electronics Co., Ltd. Method of crystallizing silicon film and method of manufacturing thin film transistor liquid crystal display
WO1999031719A1 (en) * 1997-12-17 1999-06-24 Matsushita Electric Industrial Co., Ltd. Semiconductor thin film, method of producing the same, apparatus for producing the same, semiconductor device and method of producing the same
US6528397B1 (en) 1997-12-17 2003-03-04 Matsushita Electric Industrial Co., Ltd. Semiconductor thin film, method of producing the same, apparatus for producing the same, semiconductor device and method of producing the same
US6806498B2 (en) 1997-12-17 2004-10-19 Matsushita Electric Industrial Co., Ltd. Semiconductor thin film, method and apparatus for producing the same, and semiconductor device and method of producing the same
US6496171B2 (en) 1998-01-23 2002-12-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
US6549184B1 (en) 1998-03-27 2003-04-15 Semiconductor Energy Laboratory Co., Ltd. Driving circuit of a semiconductor display device and the semiconductor display device
US7304625B2 (en) 1998-03-27 2007-12-04 Semiconductor Energy Laboratory Co., Ltd. Driving circuit of a semiconductor display device and the semiconductor display device
US8054270B2 (en) 1998-03-27 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Driving circuit of a semiconductor display device and the semiconductor display device
US7315296B2 (en) 1998-03-27 2008-01-01 Semiconductor Energy Laboratory Co., Ltd. Driving circuit of a semiconductor display device and the semiconductor display device
US7042432B2 (en) 1998-04-28 2006-05-09 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistor circuit and a semiconductor display using the same
US6538632B1 (en) 1998-04-28 2003-03-25 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor circuit and a semiconductor display device using the same
US7746311B2 (en) 1998-04-28 2010-06-29 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistor circuit and a semiconductor display using the same
JP2005347765A (en) * 1999-08-31 2005-12-15 Sharp Corp Semiconductor device and manufacturing method therefor, and method of forming silicon thin film
US6872607B2 (en) 2000-03-21 2005-03-29 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US7384832B2 (en) 2000-03-21 2008-06-10 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US7229864B2 (en) 2000-03-21 2007-06-12 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US7652289B2 (en) 2000-11-09 2010-01-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US6831299B2 (en) 2000-11-09 2004-12-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8217395B2 (en) 2000-11-09 2012-07-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7208763B2 (en) 2000-11-09 2007-04-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9099362B2 (en) 2000-11-09 2015-08-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2007067431A (en) * 2001-08-30 2007-03-15 Sharp Corp Semiconductor device
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