JPS59160334U - encoder - Google Patents

encoder

Info

Publication number
JPS59160334U
JPS59160334U JP5088283U JP5088283U JPS59160334U JP S59160334 U JPS59160334 U JP S59160334U JP 5088283 U JP5088283 U JP 5088283U JP 5088283 U JP5088283 U JP 5088283U JP S59160334 U JPS59160334 U JP S59160334U
Authority
JP
Japan
Prior art keywords
encoder
state buffer
address
control device
recorded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5088283U
Other languages
Japanese (ja)
Inventor
西原　正敏
穂坂　重孝
武生 大道
桜井　朋文
Original Assignee
三菱重工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱重工業株式会社 filed Critical 三菱重工業株式会社
Priority to JP5088283U priority Critical patent/JPS59160334U/en
Publication of JPS59160334U publication Critical patent/JPS59160334U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のエンコーダ信号出力配線の構成図、第２
図は本考案によるエンコーダの構成図である。 図面中、ＩＡ〜ＩＮはエンコーダ（本体）、４は制御装
置、５はアドレス発生器、６はエンコーダ信号ケーブル
、７は増巾器、８Ａ〜８Ｎは３ステートバツフア、９Ａ
〜９Ｎはアドレスデコーダ、　　−１０はアドレス信号
ケーブルである。Figure 1 is a configuration diagram of conventional encoder signal output wiring, Figure 2
The figure is a block diagram of an encoder according to the present invention. In the drawing, IA to IN are encoders (main body), 4 is a control device, 5 is an address generator, 6 is an encoder signal cable, 7 is an amplifier, 8A to 8N are 3-state buffers, 9A
~9N is an address decoder, -10 is an address signal cable.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] エンコーダの出力を入力し制御装置に接続可能な３ステ
ートバツフアと、アドレス発生器に接続′　゛　　可能
であって３ステートバツフアを制御するアドレスデコー
ダとを備えたエンコーダ。An encoder comprising a 3-state buffer that inputs the output of the encoder and can be connected to a control device, and an address decoder that can be connected to an address generator and controls the 3-state buffer.
JP5088283U 1983-04-07 1983-04-07 encoder Pending JPS59160334U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5088283U JPS59160334U (en) 1983-04-07 1983-04-07 encoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5088283U JPS59160334U (en) 1983-04-07 1983-04-07 encoder

Publications (1)

Publication Number Publication Date
JPS59160334U true JPS59160334U (en) 1984-10-27

Family

ID=30181329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5088283U Pending JPS59160334U (en) 1983-04-07 1983-04-07 encoder

Country Status (1)

Country Link
JP (1) JPS59160334U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51144137A (en) * 1975-06-06 1976-12-10 Hitachi Ltd Input/output data control unit
JPS5597625A (en) * 1979-01-17 1980-07-25 Fanuc Ltd Bus connection system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51144137A (en) * 1975-06-06 1976-12-10 Hitachi Ltd Input/output data control unit
JPS5597625A (en) * 1979-01-17 1980-07-25 Fanuc Ltd Bus connection system

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