JPS58106952U - integrated circuit - Google Patents

integrated circuit

Info

Publication number
JPS58106952U
JPS58106952U JP307782U JP307782U JPS58106952U JP S58106952 U JPS58106952 U JP S58106952U JP 307782 U JP307782 U JP 307782U JP 307782 U JP307782 U JP 307782U JP S58106952 U JPS58106952 U JP S58106952U
Authority
JP
Japan
Prior art keywords
integrated circuit
power supply
output buffer
type output
supply wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP307782U
Other languages
Japanese (ja)
Inventor
市田　憲治
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP307782U priority Critical patent/JPS58106952U/en
Publication of JPS58106952U publication Critical patent/JPS58106952U/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

−幣１−図は従来の蝋一配線図の一例を示す図、第２図
は従来の電源の配分方法を示す図、第３図は本実施例の
電源配線図を示し、第４図ｃｔ本考案の電一一分方法を
誉す図工ある。Figure 1 is a diagram showing an example of a conventional wiring diagram, Figure 2 is a diagram showing a conventional power distribution method, Figure 3 is a power supply wiring diagram of this embodiment, and Figure 4 is a diagram showing an example of a conventional wiring diagram. There are drawings and crafts that praise the electric 11-minute method devised by this invention.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プレユプル型出力バ］ンブアーを内革した集積回１路に
於いて、前記プシュテル型出力バツブアーへめ電源配線
と、センスアンプ回路への電源配線とが、電源用パッド
から分離して、？諭々に配線されでいることを特徴とす
る集積回路。In a single integrated circuit with a pre-pull type output buffer, the power supply wiring to the pushtel type output buffer and the power supply wiring to the sense amplifier circuit are separated from the power supply pad. An integrated circuit characterized by being carefully wired.
JP307782U 1982-01-13 1982-01-13 integrated circuit Pending JPS58106952U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP307782U JPS58106952U (en) 1982-01-13 1982-01-13 integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP307782U JPS58106952U (en) 1982-01-13 1982-01-13 integrated circuit

Publications (1)

Publication Number Publication Date
JPS58106952U true JPS58106952U (en) 1983-07-21

Family

ID=30016027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP307782U Pending JPS58106952U (en) 1982-01-13 1982-01-13 integrated circuit

Country Status (1)

Country Link
JP (1) JPS58106952U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0187561U (en) * 1987-12-01 1989-06-09
JP2010232288A (en) * 2009-03-26 2010-10-14 Oki Semiconductor Co Ltd Semiconductor integrated chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0187561U (en) * 1987-12-01 1989-06-09
JP2010232288A (en) * 2009-03-26 2010-10-14 Oki Semiconductor Co Ltd Semiconductor integrated chip

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