JPS59155963A - High sensitive thyristor - Google Patents
High sensitive thyristorInfo
- Publication number
- JPS59155963A JPS59155963A JP3030283A JP3030283A JPS59155963A JP S59155963 A JPS59155963 A JP S59155963A JP 3030283 A JP3030283 A JP 3030283A JP 3030283 A JP3030283 A JP 3030283A JP S59155963 A JPS59155963 A JP S59155963A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thyristor
- type emitter
- type
- emitter layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 230000002349 favourable effect Effects 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
- H01L29/7408—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a capacitor or a resistor
Abstract
Description
【発明の詳細な説明】
（１）発明の属する分野
本発明は、ＰＮＰＮ４層よりなる高感度サイリスタのゲ
ート特性に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to gate characteristics of a high-sensitivity thyristor made of four PNPN layers.
（２）従来の技術の説明
従来の高感度サイリスタは、概ね第１図に示゛
すような構造を有している。第１図に於て、最下
層のＰ型エミッタ層１はサイリスタのアノードと称する
ものである。Ｐ型エミッタ層１の上面に、Ｎ型ベース層
２が配置され、Ｎ型ベース層２の上にＰ型ベース層３が
配置され、Ｐ型ベース層３にはＮ型不純物の選択拡散に
より％Ｎ型エミッタ層４が設けられている。これは、サ
イリスタのカソードと称するものである。Ｐ型エミッタ
層１の表面には、アノード電極７．Ｎ型エミツタ層４の
表面には、カソード電極５、Ｐ型ベース層３には、ゲー
ト電極６がそれぞれ設けられている。サイリスタの電気
的特性のうち重要なものの一つとしてゲー・トトリガ電
流・（以下、Ｉｇｔと略す）が挙げられる。従来の高感
度サイリスクに於ては、通常数μＡ程度以下と言う発生
状況が一般的である。実用上から判断し、Ｉｇｔは高感
度サイリスタとしての機能を損うことなく、又、誤動作
を起こしにくいという面から数十μＡ程度が望まれてい
る。(2) Description of conventional technology A conventional high-sensitivity thyristor is generally shown in Figure 1.
It has such a structure. In FIG. 1, the lowest P-type emitter layer 1 is called the anode of the thyristor. An N-type base layer 2 is arranged on the upper surface of the P-type emitter layer 1, a P-type base layer 3 is arranged on the N-type base layer 2, and the P-type base layer 3 is doped with % by selective diffusion of N-type impurities. An N-type emitter layer 4 is provided. This is called the cathode of the thyristor. On the surface of the P-type emitter layer 1, an anode electrode 7. A cathode electrode 5 is provided on the surface of the N-type emitter layer 4, and a gate electrode 6 is provided on the P-type base layer 3, respectively. One of the important electrical characteristics of a thyristor is the gate trigger current (hereinafter abbreviated as Igt). In conventional high-sensitivity psi-risks, the occurrence situation is usually about several μA or less. Judging from a practical standpoint, Igt is desired to have a value of about several tens of μA without impairing its function as a high-sensitivity thyristor and to prevent malfunctions.
従従来、Ｔｇｔのスクリーニングなる手段により。Conventionally, by means of Tgt screening.
良品を選別していたため、歩留が低く、コスト高となっ
ていた。そこで、サイリスタとして他の特性を損うこと
な（Ｉｇｔを大きくする方法として、Ｐ型ベース層３０
表面近傍に、例えはイオン注入、Ｎ型不純物の低濃拡散
方法により、低濃度のＰ層を設け、該低濃度Ｐ層を通じ
て、サイリスタのトリガ特性に寄与しない無効電流を流
し、Ｉｇｔを増大させる方法が提案されている。しかし
、この方法は、Ｐイー１表面に低濃度層を設けるため、
保護酸化膜や被覆樹脂中に含まれる不純物の影響を受け
やすく、ゲート特性が不安定であると言う欠点を有して
いた。Because good products were selected, yields were low and costs were high. Therefore, as a method of increasing Igt without impairing other characteristics as a thyristor, it is recommended to
A low concentration P layer is provided near the surface by, for example, ion implantation or a low concentration diffusion method of N-type impurities, and a reactive current that does not contribute to the triggering characteristics of the thyristor is caused to flow through the low concentration P layer to increase Igt. A method is proposed. However, this method provides a low concentration layer on the surface of PE1,
It has the disadvantage that it is easily affected by impurities contained in the protective oxide film and coating resin, and the gate characteristics are unstable.
（３）発明の目的
本発明の目的は、これらの欠点を除去した半導体装置を
提供することにある。(3) Object of the invention An object of the invention is to provide a semiconductor device that eliminates these drawbacks.
（４）発明の特徴
本発明の特徴は、Ｐ型ベース層とＮ型エミツタ層との接
合表面に低抵抗層を積層させ、該低抵抗層を介してゲー
ト・カソード間に無効電流を流しｖ Ｉｇｔを増大させ
ることにある。(4) Features of the invention The feature of the invention is that a low resistance layer is laminated on the junction surface of the P type base layer and the N type emitter layer, and a reactive current is passed between the gate and the cathode through the low resistance layer. The aim is to increase Igt.
（５）実施例 以下に、図面を用いて本発明の詳細な説明する。(5) Examples The present invention will be described in detail below using the drawings.
第２図は、本発明の実施例のゲート付近の断面拡大図で
あって、３は、１５０μｍから３００μｍ程度の厚さの
Ｓｉ基板にＧａ又はＢを３０μｍから８０μｍ程度の深
さに拡散して設けたＰ型ベース層、４は、Ｐ型ベース層
３に酸化膜をマスクとしてリンを１０μｍから５０μｍ
程度の深さに選択拡散して設けたＮ型エミツタ層である
。９は、ＬＰＣＶＤ法により積層させた６０００Ｘの厚
さをもつポリシリ成長層である。１０は、ポリシリ層上
に積層したＣＶＤ Ｓ ｉ ０２であり、底面保護膜と
して作用する。ポリシリ層の抵抗は、リン拡散によりコ
ントロールが容易であることを利用し、数１０オームか
ら数１０にΩまで可変できる。FIG. 2 is an enlarged cross-sectional view of the vicinity of the gate of the embodiment of the present invention, and 3 is a Si substrate with a thickness of about 150 μm to 300 μm, in which Ga or B is diffused to a depth of about 30 μm to 80 μm. The provided P-type base layer 4 is formed by applying phosphorus to a thickness of 10 μm to 50 μm using an oxide film as a mask on the P-type base layer 3.
This is an N-type emitter layer provided by selective diffusion to a depth of approximately 9 is a polysilicon growth layer having a thickness of 6000× laminated by the LPCVD method. 10 is a CVD Si 02 layered on the polysilicon layer, which acts as a bottom protective film. The resistance of the polysilicon layer can be varied from several tens of ohms to several tens of ohms by utilizing the fact that it is easily controlled by phosphorus diffusion.
第３図は、ゲート部の等価回路である。ここで、ゲート
・カソード間のダイオードの順方向特性において、順電
圧が、通常０．６．Ｖ程度の拡散電位に達した時、サイ
リスタはターンオンし、この時のダイオード順電流Ｉｇ
ｔがサイリスタのゲートトリガ電流である。本発明では
、ポリシリ層の抵抗は、第３図のＲＣ，Ｋに相当するも
のである。°ここで、ＲＧＫは、次式により与えられる
。FIG. 3 is an equivalent circuit of the gate section. Here, in the forward characteristic of a diode between the gate and the cathode, the forward voltage is usually 0.6. When the diffusion potential of about V is reached, the thyristor turns on, and the diode forward current Ig at this time
t is the gate trigger current of the thyristor. In the present invention, the resistance of the polysilicon layer corresponds to RC and K in FIG. °Here, RGK is given by the following equation.
Ｒｓは、ＰＮダイオード部抵抗を意味し、ＶＤ／Ｉｇｔ
ｉより求めている。Rs means PN diode resistance, VD/Igt
I'm looking for more than i.
ＲＧＫ ＝ Ｖｎ−Ｒｓ／ （Ｒｓ・ＩＧＴ −ＶＤ）
そこで、Ｖｏ＝＝０．６Ｖ 、 Ｒｓ＝６０Ｉ（Ωの時
、ＴＧＴを５０μ人に設定しようとする時、ＲＧＫは約
１５にΩ程度に設定すれば良い。RGK = Vn-Rs/ (Rs・IGT-VD)
Therefore, when Vo==0.6V and Rs=60I (Ω), when trying to set TGT to 50μ, RGK should be set to about 15Ω.
第４図は、第３図等価回路のＩｇｔ特性を示している。FIG. 4 shows the Igt characteristics of the equivalent circuit of FIG. 3.
すなわち、本サイリスタのＩｇｔは、Ｔｇｔ ＝ Ｉｇ
ｔｌ ＋ Ｉｇ、ｔ２で表わされ、ポリシリ層を流れる
無効電流Ｉｇｔｌを制御すること、すなわちリン濃度の
コントロールにより、抵抗を可変することにより本サイ
リスタのＩｇｔを精度良く、設定できる。That is, Igt of this thyristor is Tgt = Ig
Igt of the present thyristor can be set with high accuracy by controlling the reactive current Igtl expressed as tl + Ig, t2, which flows through the polysilicon layer, that is, by controlling the phosphorus concentration, and by varying the resistance.
（６）効果の説明
以上説明したように、高感度サイリスタに於て、Ｐ型ベ
ース層とＮ型エミツタ層とを低抵抗層（ポリシリ層）に
て短絡した構造を採用することにより、本サイリスタの
Ｉｇｔを精度良く設定することが可能となり、歩留り向
上に寄与し、原価低減に大きな効果が期待できる。(6) Explanation of effects As explained above, this thyristor has a structure in which the P-type base layer and the N-type emitter layer are short-circuited by a low-resistance layer (polysilicon layer). It becomes possible to set Igt with high accuracy, which contributes to improving yield and can be expected to have a significant effect on cost reduction.
第１図は、従来の一般的な高感度サイ１ノスタの断面図
、第２図は、本発明でのサイ１ノスタのゲート付近の断
面拡大図、・第３図は、ゲート付近の等価回路図。第４
図は、第３図にて示しだゲート付近の等価回路図である
。
′なお、図において、１・・・・・・Ｐ型エミッタ層、
２・・・・・・Ｎｕペース層、３・・・・・・ｐｇベー
ス層、４・・・・・・Ｎ型エミツタ層、５・・・・・・
カンード電極、６・・・・・・ゲート電極、７・・・・
・・アノード電極、８・・・・・・表面保護酸化膜、９
・・・・・・ポリシリ層による低抵抗層、１０・・・・
・・ＣＶＤ Ｓ ｌｏｚによる表面保護膜、１１・・・
・・・ゲート部ＰＮダイオード、である。Figure 1 is a cross-sectional view of a conventional general high-sensitivity Cy-1 Nostar, Figure 2 is an enlarged cross-sectional view of the Cy-1 Nostar of the present invention near the gate, and Figure 3 is an equivalent circuit near the gate. figure. Fourth
This figure is an equivalent circuit diagram of the vicinity of the gate shown in FIG. 3. 'In addition, in the figure, 1...P-type emitter layer,
2...Nu pace layer, 3...PG base layer, 4...N type emitter layer, 5...
Cando electrode, 6...Gate electrode, 7...
...Anode electrode, 8...Surface protective oxide film, 9
...Low resistance layer made of polysilicon layer, 10...
...Surface protection film by CVD S loz, 11...
...Gate part PN diode.
Claims (1)
於て、該Ｐ型代−ス層と該Ｎ型エミツタ層の接合表面に
低抵抗層を積層し、該Ｐ型代−ス層と該Ｎ型エミツタ層
とを短絡したことを特徴とする高感度サイリスタ。[Claims] P-type emitter layer, N-type base layer, P-type substitute layer. In a high-sensitivity thyristor having a four-layer structure including an N-type emitter layer, a low-resistance layer is laminated on the junction surface of the P-type emitter layer and the N-type emitter layer, and the P-type emitter layer and the A high-sensitivity thyristor characterized by short-circuiting the N-type emitter layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3030283A JPS59155963A (en) | 1983-02-25 | 1983-02-25 | High sensitive thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3030283A JPS59155963A (en) | 1983-02-25 | 1983-02-25 | High sensitive thyristor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59155963A true JPS59155963A (en) | 1984-09-05 |
Family
ID=12299950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3030283A Pending JPS59155963A (en) | 1983-02-25 | 1983-02-25 | High sensitive thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59155963A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4994885A (en) * | 1988-07-01 | 1991-02-19 | Sanken Electric Co., Ltd. | Bidirectional triode thyristor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS559399A (en) * | 1978-06-29 | 1980-01-23 | Siemens Ag | Arrester |
-
1983
- 1983-02-25 JP JP3030283A patent/JPS59155963A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS559399A (en) * | 1978-06-29 | 1980-01-23 | Siemens Ag | Arrester |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4994885A (en) * | 1988-07-01 | 1991-02-19 | Sanken Electric Co., Ltd. | Bidirectional triode thyristor |
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