JP2510972B2 - Bidirectional thyristor - Google Patents
Bidirectional thyristorInfo
- Publication number
- JP2510972B2 JP2510972B2 JP59278726A JP27872684A JP2510972B2 JP 2510972 B2 JP2510972 B2 JP 2510972B2 JP 59278726 A JP59278726 A JP 59278726A JP 27872684 A JP27872684 A JP 27872684A JP 2510972 B2 JP2510972 B2 JP 2510972B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductivity type
- intermediate layer
- junction
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000002457 bidirectional effect Effects 0.000 title claims description 4
- 239000010410 layer Substances 0.000 claims description 110
- 239000002344 surface layer Substances 0.000 claims description 64
- 239000000758 substrate Substances 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 30
- 238000009792 diffusion process Methods 0.000 description 25
- 239000012535 impurity Substances 0.000 description 13
- 230000035945 sensitivity Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/747—Bidirectional devices, e.g. triacs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】 [発明の技術分野] この発明は、双方向性半導体装置に係り、特に導電型
が交互に異なる5層構造を持つ交流用スイツチング用の
半導体装置に関する。Description: TECHNICAL FIELD The present invention relates to a bidirectional semiconductor device, and more particularly to a semiconductor device for AC switching having a five-layer structure in which conductivity types are alternately different.
[発明の技術的背景] 導電型が交互に異なる5層構造を持つ交流用スイツチ
ング用半導体装置は、通常トライアツクと称され、従来
より第3図に示すように、n−p−n−p−nの5層構
造からなる半導体基板の一面に主電極(T1)とゲート電
極(G)が、また他面に主電極(T2)が設けられた構造
に形成されている。[Technical Background of the Invention] A semiconductor device for alternating current switching having a five-layer structure with alternating conductivity types is usually called a triac, and as shown in FIG. A semiconductor substrate having a five-layer structure of n has a main electrode (T 1 ) and a gate electrode (G) on one surface and a main electrode (T 2 ) on the other surface.
この半導体装置は、ゲート電極(G)に入つた信号に
よりオフ状態からオン状態に移行して、交流電力を制御
する機能を有する。その点弧モードは、主電極(T1),
(T2)間のバイアス方向と、主電極(T1)とゲート電極
(G)のバイアス方向との組合せにより、次の4通りが
ある。This semiconductor device has a function of shifting from an off state to an on state by a signal input to the gate electrode (G) and controlling AC power. The firing mode is the main electrode (T 1 ),
There are the following four types depending on the combination of the bias direction between (T 2 ) and the bias directions of the main electrode (T 1 ) and the gate electrode (G).
Iモード:主電極(T1)に対し主電極(T2)に正の電
圧を印加し、同時に主電極(T1)に対しゲート電極
(G)に正の信号を入れる Iモード:主電極(T1)に対し主電極(T2)に正の電
圧を印加し、同時に主電極(T1)に対しゲート電極
(G)に負の信号を入れる IIIモード:主電極(T1)に対し主電極(T2)に負の
電圧を印加し、同時に主電極(T1)に対しゲート電極
(G)に正の信号を入れる IIIモード:主電極(T1)に対し主電極(T2)に負の
電圧を印加し、同時に主電極(T1)に対しゲート電極
(G)に負の信号を入れる この4通りのモードのうち、通常使用されるモード
は、IIIモードを除く3通りのモードのうちの2つで
ある。IIIモードは、その点弧機構の複雑さから、点
弧に必要なゲート電流が他のモードに比べて非常に大き
いため、従来用いられていなかつた。I Mode: main electrodes (T 1) to the main electrodes (T 2) a positive voltage is applied to, I-mode add positive signal to the gate electrode (G) to simultaneously main electrodes (T 1): main electrode (T 1) to a positive voltage is applied to the main electrode (T 2), III-mode add negative signal to the gate electrode (G) to the main electrodes (T 1) at the same time: the main electrode (T 1) In contrast, a negative voltage is applied to the main electrode (T 2 ), and at the same time a positive signal is applied to the gate electrode (G) with respect to the main electrode (T 1 ). III mode: Main electrode (T 1 ) with respect to the main electrode (T 1 ). 2 ) Apply a negative voltage to the main electrode (T 1 ) and apply a negative signal to the gate electrode (G) at the same time. Of these four modes, the ones that are normally used are 3 except the III mode. Two of the street modes. Due to the complexity of the ignition mechanism, the III mode has not been used in the past because the gate current required for ignition is much larger than other modes.
しかし最近、IIIモードを含む4モード駆動可能な
半導体装置の需要が生じており、特にIおよびIII
モードを用いてICによるトライアツクの直接駆動の実現
が望まれている。そのためには、従来10〜20mA程度であ
つたゲート電流を5mA程度に減少させてゲートトリガ特
性を高感度にすることが必要である。However, recently, there has been a demand for a semiconductor device capable of driving four modes including the III mode, and particularly, I and III.
It is desired to realize direct drive of triac by IC using mode. For that purpose, it is necessary to reduce the gate current, which used to be about 10 to 20 mA, to about 5 mA, to make the gate trigger characteristic highly sensitive.
ところでトライアツクは、等価的に逆並列に接続され
る2つのサイリスタから構成されていると考えることが
できるので、第3図におけるP型領域(P1),(P2)の
半分は、一方のサイリスタのアノード領域に当り、比較
的高濃度の拡散が要求されるが、残りの半分の領域は、
もう一つのサイリスタPベースに相当し、ここにNエミ
ツタが拡散されるから、アノードに比べて低濃度である
ことが望ましい。しかしながら従来は、IIIモードで
のトリガ機能の要求がなく、またそれ以外のトリガモー
ドについても極端に高感度にする必要がなかつたため、
P型領域(P1),(P2)を同時にしかも同一濃度で形成
していた。すなわち従来は、N型半導体基板の両面に同
時にP型不純物を付着させ、これをそれぞれ基板の内部
に拡散させてP型領域(P1),(P2)を形成したのち、
このP型領域(P1),(P2)の一部にそれぞれN型不純
物を付着させ、これらをP型領域(P1),(P2)の一部
にそれぞれN型不純物を付着させ、これらをP型領域
(P1),(P2)中の所定の深さまで拡散させてN型領域
(NE1),(NE2),(NEG)を形成していた。By the way, since the triac can be considered to be composed of two thyristors that are equivalently connected in anti-parallel, half of the P-type regions (P 1 ) and (P 2 ) in FIG. A relatively high concentration of diffusion is required for the anode region of the thyristor, but the other half is
Since it corresponds to another thyristor P base and N emitters are diffused therein, it is desirable that the concentration is lower than that of the anode. However, in the past, there was no requirement for a trigger function in the III mode, and it was not necessary to make the sensitivity extremely high for other trigger modes as well.
The P-type regions (P 1 ) and (P 2 ) were formed simultaneously and at the same concentration. That is, conventionally, P-type impurities are simultaneously adhered to both surfaces of an N-type semiconductor substrate and diffused into the inside of the substrate to form P-type regions (P 1 ) and (P 2 ).
The P-type region (P 1), depositing the respective N-type impurity in a part of (P 2), these P-type regions (P 1), depositing the N-type impurity respectively in a portion of (P 2) , N-type regions (N E1 ), (N E2 ), and (N EG ) were formed by diffusing these to a predetermined depth in the P-type regions (P 1 ) and (P 2 ).
しかし、IIIモードにおけるトリガ特性が高感度な
トライアツク、さらにはすべてのモードにおいてトリガ
特性を高感度にするためには、従来構造ではいろいろな
制約を生じ、製造プロセス上拡散などの制御がむつかし
く製作が極めて困難である。However, in order to make the triac with high sensitivity in the III mode and the trig with high sensitivity in all modes, various restrictions are caused in the conventional structure, and the control such as diffusion is difficult in the manufacturing process. It's extremely difficult.
[発明の目的] この発明は、トライアツクの基本的な特性を損うこと
なく、ゲートトリガ特性の高感度化、特にIIIモード
におけるトリガ特性を高感度にすることにある。[Object of the Invention] An object of the present invention is to enhance the sensitivity of the gate trigger characteristic, particularly the trigger characteristic in the III mode, without damaging the basic characteristics of the triac.
[発明の概要] 異なる導電型層を交互に重ねて構成する半導体基板
と,この半導体基板の一面に形成する第1導電型の第1
表面層と,これに隣接・連続し前記半導体基板表面を構
成する第2導電型の第1中間層と,前記第1表面層と第
2導電型の第1中間層により形成する第1PN接合と,前
記第2導電型の第1中間層に露出する第1PN接合端部
と,この第1PN接合端部に接続し前記半導体基板表面に
沿って形成する第1PN接合平坦部と,この第1PN接合平坦
部に対向する前記第2導電型の第1中間層部分に設ける
低濃度層と,これに隣接・連続し深さを大きく形成する
高濃度層と,前記第1PN接合端部及び第2導電型の第1
中間層に跨がって形成する第1主電極と,前記第1表面
層と離れた前記第2導電型の第1中間層露出部に形成す
る第1導電型の第2表面層と,この第2表面層及び前記
第2導電型の第1中間層の露出部を接続するゲート電極
と,前記半導体基板の他面に得られる前記半導体基板の
一面の投影部分において前記第1表面層の一部に及び第
2表面層の一部を重ねて形成する第1導電型の第3表面
層と,これに隣接・連続し前記半導体基板の他面を構成
する第2導電型の第2中間層と,この第2導電型の第2
中間層に隣接・連続する第1導電型の中間層と,前記第
2中間層及び第1導電型の第3表面層間に形成する第2P
N接合と,前記半導体基板の他面を構成する第2導電型
の第2中間層部分に露出する第2PN接合端部と,この第2
PN接合端部に接続し前記半導体基板の他表面に沿って形
成する第2PN接合平坦部と,前記第2PN接合端部と前記第
2導電型の第2中間層を接続する第2主電極と,前記第
3表面層と第1導電型の中間層間に位置する第2導電型
の第2中間層部分に形成する低濃度層及び他部分の高濃
度層とを具備し,前記第1主電極−第1導電型の第1表
面層−前記第2導電型の第1中間層に形成する低濃度層
−前記第1導電型の中間層及び第2導電型の第2中間層
部分の低濃層−前記第1導電型の第3表面層からなる導
電路と、前記第2主電極−前記第2導電型の第2中間層
部分の高濃度層−前記第1導電型の中間層−前記第2導
電型の第1中間層に形成する低濃度層−前記第1導電型
の第1表面層からなる導電路を交互に利用する点に本発
明に係わる双方向サイリスタの特徴がある。[Summary of the Invention] A semiconductor substrate having different conductivity type layers alternately stacked, and a first conductivity type first substrate formed on one surface of the semiconductor substrate.
A surface layer, a second conductive type first intermediate layer adjacent to and continuous with the surface of the semiconductor substrate, and a first PN junction formed by the first surface layer and the second conductive type first intermediate layer , A first PN junction end exposed on the second intermediate layer of the first conductivity type, a first PN junction flat portion connected to the first PN junction end and formed along the surface of the semiconductor substrate, and the first PN junction A low-concentration layer provided on the first intermediate layer portion of the second conductivity type facing a flat portion, a high-concentration layer adjacent to and continuous with the first intermediate layer portion, and forming a large depth, the first PN junction end portion and the second conductivity layer. Type 1
A first main electrode formed over the intermediate layer, a second surface layer of the first conductivity type formed in the exposed portion of the first intermediate layer of the second conductivity type separated from the first surface layer, and The gate electrode connecting the exposed portion of the second surface layer and the first intermediate layer of the second conductivity type, and the one portion of the first surface layer in the projected portion of the one surface of the semiconductor substrate obtained on the other surface of the semiconductor substrate. And a part of the second surface layer are overlapped with each other to form a third surface layer of the first conductivity type, and a second intermediate layer of the second conductivity type that is adjacent to and continuous with the third surface layer and forms the other surface of the semiconductor substrate. And this second conductivity type second
An intermediate layer of the first conductivity type adjacent to and continuous with the intermediate layer, and a second P formed between the second intermediate layer and the third surface layer of the first conductivity type
An N junction, a second PN junction end exposed at a second intermediate layer portion of the second conductivity type constituting the other surface of the semiconductor substrate, and the second PN junction end portion.
A second PN junction flat portion connected to the PN junction end portion and formed along the other surface of the semiconductor substrate; and a second main electrode connecting the second PN junction end portion and the second conductive type second intermediate layer A low concentration layer formed in a second intermediate layer portion of the second conductive type located between the third surface layer and the intermediate layer of the first conductive type and a high concentration layer of another portion, the first main electrode -First surface layer of the first conductivity type-Low concentration layer formed in the first intermediate layer of the second conductivity type-Low concentration of the intermediate layer of the first conductivity type and the second intermediate layer portion of the second conductivity type Layer-a conductive path composed of the third surface layer of the first conductivity type, the second main electrode, a high-concentration layer of the second intermediate layer portion of the second conductivity type-the intermediate layer of the first conductivity type-the above The bidirectional service according to the present invention is characterized in that the conductive paths composed of the low-concentration layer formed on the first intermediate layer of the second conductivity type and the first surface layer of the first conductivity type are alternately used. There is a feature of the lister.
[発明の実施例] 以下、図面を参照してこの発明を実施例に基づいて説
明する。Embodiments of the Invention Hereinafter, the present invention will be described based on embodiments with reference to the drawings.
第1図にプレーナ構造のトライアツクの一例を示す。
この半導体装置は、N型半導体基板の一面に、互に離間
して同一N型の第1、第2表面層(NE1),(NEG)が設
けられ、またこれら第1、第2表面層(NE1),(NEG)
を取り囲む如くP型の第1中間層露出部(P1)が設けら
れ、さらに他面には、前記第1表面層(NE1)と同一導
電型の第3表面層(NE2)が、図面中に破線(1)で囲
んで示すように一部が第1表面層(NE1)の投影部分と
重なる如く、更に第2表面層(NEG)の投影部分と重な
る如く、またこの第3表面層(NE2)を取り囲む如く前
記中間層露出部(P1)と同一導電型の第2中間層露出部
(P2)が設けられ、全体としてn−p−n−p−nの5
層構造に形成されている。しかも第1表面層(NE1)に
前記第3表面層NE2側で隣接する第1中間層は、第1、
第2表面層(NE1),(NEG)に隣接する第1中間層露出
部(P1)の不純物濃度より小さく、かつ拡散の深さが浅
くなつている。また第3表面層(NE2)に第1表面層(N
E1)側で隣接する第2中間層も、この第3表面層
(NE2)に隣接する第2中間層露出部(P2)の不純物濃
度より小さく、かつ拡散の深さが浅くなつている。なお
前記基板の一面には、第1表面層(NE1)と第1中間層
露出部(P1)、および第2表面層(NEG)と第1中間層
露出部(P1)に跨つて、それぞれそららを接続する第1
主電極(T1)およびゲート電極(G)が設けられ、また
他面には、第3表面層(NE2)と第2中間層露出部
(P2)を接続する第2主電極(T2)が設けられている。FIG. 1 shows an example of a triac having a planar structure.
In this semiconductor device, the same N-type first and second surface layers (N E1 ), (N EG ) are provided on one surface of an N-type semiconductor substrate and are separated from each other, and these first and second surfaces are also provided. Layer (N E1 ), (N EG )
A P-type first intermediate layer exposed portion (P 1 ) is provided so as to surround, and a third surface layer (N E2 ) having the same conductivity type as the first surface layer (N E1 ) is provided on the other surface. As indicated by the broken line (1) in the drawing, a part of it overlaps the projected portion of the first surface layer (N E1 ), and further overlaps the projected portion of the second surface layer (N EG ). 3 the surface layer (n E2) as the intermediate layer exposed portion surrounding the (P 1) and the second intermediate layer exposed portion of the same conductivity type (P 2) is provided, as a whole n-p-n-p- n of 5
It is formed in a layered structure. Moreover, the first intermediate layer adjacent to the first surface layer (N E1 ) on the side of the third surface layer N E2 is
The impurity concentration is lower than the first intermediate layer exposed portion (P 1 ) adjacent to the second surface layers (N E1 ) and (N EG ) and the diffusion depth is shallow. In addition, the first surface layer (N E2 ) is formed on the third surface layer (N E2 ).
The second intermediate layer adjacent to E1) side, smaller than the impurity concentration and the depth of the diffusion and summer shallow the third surface layer (a second intermediate layer exposed portion adjacent to the N E2) (P 2) . In addition, the first surface layer (N E1 ) and the first intermediate layer exposed portion (P 1 ) and the second surface layer (N EG ) and the first intermediate layer exposed portion (P 1 ) are formed on one surface of the substrate. First, connecting each sky
The main electrode (T 1 ) and the gate electrode (G) are provided, and the second main electrode (T 2 ) that connects the third surface layer (N E2 ) and the second intermediate layer exposed portion (P 2 ) is provided on the other surface. 2 ) is provided.
この半導体装置は下記のように製造することができ
る。This semiconductor device can be manufactured as follows.
まず第2図(a)図に示すように、N型半導体基板に
アイソレーシヨン拡散を施こし、個々の素子に分離する
P型領域(2)を形成する。次に(b)図に示すよう
に、この基板の一面のP領域(2)に囲まれた一定の領
域に、また他面にはP領域(2)との境界部を跨いで、
それぞれP型の不純物を1100℃で付着させて浅い拡散層
(3)を形成する。この拡散層(3)の表面を酸化した
のち、各面の拡散層(3)間の領域(4)に、拡散層
(3)を形成するときの不純物付着温度より低い温度、
たとえば950℃でP型の不純物を付着させて、(c)図
に示すように浅い拡散層(5)を形成する。しかるのち
全面に酸化膜を形成して、1200℃以上の高温で処理し、
(d)図に示すように、所定の深さまで深く拡散して、
前記第1、第2中間層露出部(P1),(P2)および第
1、第2中間層に対応するP型拡散層(3a),(5a)を
形成する。この基板の両面に形成される拡散層(5a)
は、その一方の投影部分に他方の一部が重る如く形成さ
れ、かつ隣接する拡散層(3a)に比べて不純物濃度が小
さく、拡散の深さはこの不純物濃度差により浅く形成さ
れる。次にこの基板の両面に形成された拡散層(3a)
(5a)の所定領域にN型不純物を付着させ、(e)図に
示すようにこれを所定の深さまで拡散させて、基板の一
面にN型の第1、第2表面層(NE1),(NEG)を、また
基板の他面に一部がこの第1表面層(NE1)の投影部分
と重なる如く第3表面層(NE2)を形成する。しかるの
ち基板の一面に形成されている酸化膜を、第1表面層
(NE1)と拡散層(3a)をそれぞれ跨ぐ如く開孔すると
ともに、他面の酸化膜を除去して、これら開孔および他
面に金属膜を蒸着して、第1図に示したように第1、第
2主電極(T1),(T2)およびゲート電極(G)を形成
する。First, as shown in FIG. 2 (a), isolation diffusion is applied to an N-type semiconductor substrate to form a P-type region (2) for separating into individual elements. Next, as shown in FIG. 2B, a certain region surrounded by the P region (2) on one surface of the substrate and a boundary region with the P region (2) on the other surface are crossed,
P-type impurities are deposited at 1100 ° C. to form a shallow diffusion layer (3). After oxidizing the surface of the diffusion layer (3), a temperature lower than the impurity attachment temperature when the diffusion layer (3) is formed in the region (4) between the diffusion layers (3) on each surface,
For example, P-type impurities are deposited at 950 ° C. to form a shallow diffusion layer (5) as shown in FIG. After that, an oxide film is formed on the entire surface and processed at a high temperature of 1200 ° C or higher,
(D) As shown in the figure, diffuse deeply to a predetermined depth,
P-type diffusion layers (3a) and (5a) corresponding to the first and second intermediate layer exposed portions (P 1 ) and (P 2 ) and the first and second intermediate layers are formed. Diffusion layers (5a) formed on both sides of this substrate
Is formed so that one of the projected portions overlaps the other, and the impurity concentration is smaller than that of the adjacent diffusion layer (3a), and the diffusion depth is shallow due to this difference in impurity concentration. Next, diffusion layers (3a) formed on both sides of this substrate
An N-type impurity is attached to a predetermined area of (5a) and diffused to a predetermined depth as shown in (e), and N-type first and second surface layers (N E1 ) are formed on one surface of the substrate. , (N EG ) and a third surface layer (N E2 ) is formed on the other surface of the substrate so that a part thereof overlaps the projected portion of the first surface layer (N E1 ). After that, an oxide film formed on one surface of the substrate is opened so as to extend over the first surface layer (N E1 ) and the diffusion layer (3a) respectively, and the oxide film on the other surface is removed to form these holes. Then, a metal film is deposited on the other surface to form the first and second main electrodes (T 1 ) and (T 2 ) and the gate electrode (G) as shown in FIG.
前記のようにトライアツクを構成すると、IIIモー
ドを含め各点弧モードにおけるゲートトリガ特性を高感
度にすることができる。すなわち、IIIモードにおけ
るトライアツクの点弧機構は、ゲート電極(G)から第
1主電極(T1)に向つて第1中間層中を横方向にゲート
電流を流すことにより、NE1−P1接合のうちゲート電極
(G)に近い部分から電子の注入が始まる。そしてこの
電子がn-領域に達してこの部分の電位を下げ、P1−Nで
構成される接合を順バイアスして、正孔が第1中間層か
らn-領域に注入される。この正孔は、n-領域を拡散して
第2中間層に達し、最終的には第2主電極(T2)に流入
する。この場合、電子の注入を始める第1表面層
(NE1)の第2表面層(NEG)を第3表面層(NE2)の一
部と重なるように形成しておくと、n-領域を拡散して第
2中間層に達した正孔は、第3表面層(NE2)を避ける
ようにして第2中間層中のこの重なり部分を横方向に流
れる。このとき、この重なり部分の横方向抵抗により、
第2中間層には横方向の電圧降下が生じ、部分的にはP2
−NE2からなる接合を順バイアスして、第3表面層
(NE2)より第2中間層に電子が注入される。この電子
は、第2中間層を拡散してn-領域に入り、n-領域の電位
を第1中間層に対して下げる。この一連の動作によつ
て、各接合が強く順バイアスされてP1−N-−P2−NE2で
構成されるサイリスタがオン状態になり、IIIモード
による点弧が開始される。When the triac is configured as described above, the gate trigger characteristic in each firing mode including the III mode can be made highly sensitive. That is, the triac ignition mechanism in the III mode is such that a gate current flows laterally in the first intermediate layer from the gate electrode (G) to the first main electrode (T 1 ) to generate N E1 −P 1 Injection of electrons starts from a portion of the junction near the gate electrode (G). Then, the electrons reach the n − region, reduce the potential of this portion, forward bias the junction composed of P 1 —N, and holes are injected from the first intermediate layer to the n − region. The holes diffuse in the n − region, reach the second intermediate layer, and finally flow into the second main electrode (T 2 ). In this case, if the second surface layer (N EG ) of the first surface layer (N E1 ) where injection of electrons is started is formed so as to overlap a part of the third surface layer (N E2 ), the n − region The holes that have diffused into the second intermediate layer and reach the second intermediate layer laterally flow in this overlapping portion in the second intermediate layer so as to avoid the third surface layer (N E2 ). At this time, due to the lateral resistance of this overlapping part,
In the second intermediate layer, a lateral voltage drop occurs, which is partially P 2
The junction made of -N E2 is forward biased and electrons are injected from the third surface layer (N E2 ) to the second intermediate layer. The electrons diffuse the second intermediate layer n - enter the region, n - lowering the potential of the region with respect to the first intermediate layer. Through this series of operations, each junction is strongly forward-biased, the thyristor composed of P 1 -N -- P 2 -N E2 is turned on, and ignition by the III mode is started.
この点弧モードに対し、この実施例のトライアツク
は、P型の不純物を拡散させて形成した拡散層(5a)が
他のP型の拡散層(3a)に比べて低濃度であるため、そ
の後N型の不純物を拡散して形成した第1、第3表面層
(NE1),(NE2)との間のP−N接合を高い注入効率で
おこなうことができ、IIIモードにおけるゲートトリ
ガ特性を高感度にすることができた。In contrast to this ignition mode, in the triac of this embodiment, the concentration of the diffusion layer (5a) formed by diffusing P-type impurities is lower than that of the other P-type diffusion layer (3a). A P-N junction between the first and third surface layers (N E1 ), (N E2 ) formed by diffusing N-type impurities can be performed with high injection efficiency, and gate trigger characteristics in the III mode Could be made highly sensitive.
また、拡散層(5a)が低濃度であるため、ゲート感度
が第1、第3表面層(NE1),(NE2)の拡散のばらつき
の影響を受けにくいという製造上の利点もある。Further, since the diffusion layer (5a) has a low concentration, there is also a manufacturing advantage that the gate sensitivity is not easily affected by the dispersion of diffusion of the first and third surface layers (N E1 ) and (N E2 ).
また、拡散層(3a)に比べて高濃度に形成することに
より、深い拡散を短時間でおこなうことができるという
利点がある。Further, by forming the diffusion layer (3a) at a higher concentration than that of the diffusion layer (3a), there is an advantage that deep diffusion can be performed in a short time.
また、深い拡散層(3a)が拡散層(5a)を取り囲む形
で形成され、プレーナ構造の端部に要求される大きな曲
率を持つため、その耐圧を高くすることができ、使用機
器の信頼性を高めることができる。Further, since the deep diffusion layer (3a) is formed so as to surround the diffusion layer (5a) and has a large curvature required at the end of the planar structure, its breakdown voltage can be increased, and the reliability of the equipment used can be improved. Can be increased.
[発明の効果] 半導体基板の一面に形成される第1表面層の投影部分
に一部が重なる如く他面に第3表面層を形成し、かつこ
の第3表面層に、第1表面層側で隣接する第2中間層の
濃度を、第3表面層に隣接する第2中間層露出部の濃度
より小としたので、IIIモードにおけるゲートトリガ
特性を高感度にすることができた。EFFECTS OF THE INVENTION A third surface layer is formed on the other surface of the semiconductor substrate so as to partially overlap the projected portion of the first surface layer formed on the one surface, and the third surface layer is formed on the first surface layer side. Since the concentration of the second intermediate layer adjacent to the third surface layer is set to be smaller than the concentration of the exposed portion of the second intermediate layer adjacent to the third surface layer, the gate trigger characteristic in the III mode can be made highly sensitive.
第1図はこの発明の一実施例であるプレーナ構造のトラ
イアツクの図、第2図(a)ないし(e)図は第1図示
トライアツクの製造方法説明図、第3図は従来のトライ
アツクの図である。 (G)……ゲート電極、(NE1)……第1表面層 (NE2)……第3表面層、(NEG)……第2表面層 (P1)……第1中間層露出部 (P2)……第2中間層露出部 (T1)……第1主電極、(T2)……第2主電極FIG. 1 is a diagram of a triac having a planar structure according to an embodiment of the present invention, FIGS. 2 (a) to 2 (e) are diagrams for explaining a manufacturing method of the triac shown in FIG. 1, and FIG. 3 is a diagram of a conventional triac. Is. (G) …… Gate electrode, (N E1 ) …… First surface layer (N E2 ) …… Third surface layer, (N EG ) …… Second surface layer (P 1 ) …… First intermediate layer exposed Part (P 2 ) ... 2nd intermediate layer exposed part (T 1 ) ... 1st main electrode, (T 2 ) ... 2nd main electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 松本 信一 君津市内箕輪70番地 東芝コンポーネン ツ株式会社君津工場内 (56)参考文献 特開 昭57−196569(JP,A) 特開 昭55−124262(JP,A) 特開 昭56−150862(JP,A) 特開 昭58−188161(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichi Matsumoto 70 Minowa, Kimitsu city Kimitsu factory Toshiba Components Co., Ltd. (56) Reference JP 57-196569 (JP, A) JP 55- 124262 (JP, A) JP 56-150862 (JP, A) JP 58-188161 (JP, A)
Claims (1)
導体基板と,この半導体基板の一面に形成する第1導電
型の第1表面層と,これに隣接・連続し前記半導体基板
表面を構成する第2導電型の第1中間層と,前記第1表
面層と第2導電型の第1中間層により形成する第1PN接
合と,前記第2導電型の第1中間層に露出する第1PN接
合端部と,この第1PN接合端部に接続し前記半導体基板
表面に沿って形成する第1PN接合平坦部と,この第1PN接
合平坦部に対向する前記第2導電型の第1中間層部分に
設ける低濃度層と,これに隣接・連続し深さを大きく形
成する高濃度層と,前記第1PN接合端部及び第2導電型
の第1中間層に跨がって形成する第1主電極と,前記第
1表面層と離れた前記第2導電型の第1中間層露出部に
形成する第1導電型の第2表面層と,この第2表面層及
び前記第2導電型の第1中間層の露出部を接続するゲー
ト電極と,前記半導体基板の他面に得られる前記半導体
基板の一面の投影部分において前記第1表面層の一部に
及び第2表面層の一部を重ねて形成する第1導電型の第
3表面層と,これに隣接・連続し前記半導体基板の他面
を構成する第2導電型の第2中間層と,この第2導電型
の第2中間層に隣接・連続する第1導電型の中間層と,
前記第2中間層及び第1導電型の第3表面層間に形成す
る第2PN接合と,前記半導体基板の他面を構成する第2
導電型の第2中間層部分に露出する第2PN接合端部と,
この第2PN接合端部に接続し前記半導体基板の他表面に
沿って形成する第2PN接合平坦部と,前記第2PN接合端部
と前記第2導電型の第2中間層を接続する第2主電極
と,前記第3表面層と第1導電型の中間層間に位置する
第2導電型の第2中間層部分に形成する低濃度層及び他
部分の高濃度層とを具備し,前記第1主電極−第1導電
型の第1表面層−前記第2導電型の第1中間層に形成す
る低濃度層−前記第1導電型の中間層及び第2導電型の
第2中間層部分の低濃層−前記第1導電型の第3表面層
からなる導電路と、前記第2主電極−前記第2導電型の
第2中間層部分の高濃度層−前記第1導電型の中間層−
前記第2導電型の第1中間層に形成する低濃度層−前記
第1導電型の第1表面層からなる導電路を交互に利用す
ることを特徴とする双方向サイリスタ。1. A semiconductor substrate having layers of different conductivity type alternately stacked, a first surface layer of a first conductivity type formed on one surface of the semiconductor substrate, and a surface of the semiconductor substrate adjacent to and continuous with the first surface layer. A first intermediate layer of the second conductivity type, a first PN junction formed by the first surface layer and the first intermediate layer of the second conductivity type, and a first intermediate layer of the second conductivity type exposed. A 1PN junction end portion, a first PN junction flat portion connected to the first PN junction end portion and formed along the surface of the semiconductor substrate, and the second intermediate layer of the second conductivity type facing the first PN junction flat portion A low-concentration layer provided in a portion, a high-concentration layer adjacent to and continuous with the high-concentration layer and forming a large depth, and a first concentration layer formed across the first PN junction end and the first intermediate layer of the second conductivity type. A second table of the first conductivity type formed on the exposed portion of the first intermediate layer of the second conductivity type separated from the main electrode and the first surface layer. A layer, a gate electrode connecting the second surface layer and an exposed portion of the first intermediate layer of the second conductivity type, and the first electrode in a projected portion of the one surface of the semiconductor substrate obtained on the other surface of the semiconductor substrate. A third surface layer of the first conductivity type formed by overlapping a part of the surface layer and a part of the second surface layer, and a second surface layer of the second conductivity type which is adjacent to and continuous with the third surface layer and constitutes the other surface of the semiconductor substrate. A second intermediate layer and a first conductive type intermediate layer adjacent to and continuous with the second conductive type second intermediate layer;
A second PN junction formed between the second intermediate layer and the third surface layer of the first conductivity type, and a second PN junction forming the other surface of the semiconductor substrate.
A second PN junction end exposed at the conductive second intermediate layer portion;
A second PN junction flat portion connected to the second PN junction end portion and formed along the other surface of the semiconductor substrate, and a second main portion connecting the second PN junction end portion and the second conductivity type second intermediate layer. An electrode, a low-concentration layer formed in a second conductive-type second intermediate layer portion located between the third surface layer and the first conductive-type intermediate layer, and a high-concentration layer in another portion, Main electrode-first surface layer of first conductivity type-low concentration layer formed on first intermediate layer of second conductivity type-intermediate layer of first conductivity type and second intermediate layer portion of second conductivity type Low-concentration layer-conducting path composed of the third surface layer of the first conductivity type, the second main electrode-high concentration layer of the second intermediate layer portion of the second conductivity type-intermediate layer of the first conductivity type −
A bidirectional thyristor characterized by alternately using a conductive path composed of a low-concentration layer formed in the first intermediate layer of the second conductivity type and the first surface layer of the first conductivity type.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59278726A JP2510972B2 (en) | 1984-12-28 | 1984-12-28 | Bidirectional thyristor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59278726A JP2510972B2 (en) | 1984-12-28 | 1984-12-28 | Bidirectional thyristor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61158179A JPS61158179A (en) | 1986-07-17 |
JP2510972B2 true JP2510972B2 (en) | 1996-06-26 |
Family
ID=17601341
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59278726A Expired - Fee Related JP2510972B2 (en) | 1984-12-28 | 1984-12-28 | Bidirectional thyristor |
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JP (1) | JP2510972B2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0793424B2 (en) * | 1992-03-27 | 1995-10-09 | 工業技術院長 | Surge protection device |
GB9215017D0 (en) * | 1992-07-15 | 1992-08-26 | Texas Instruments Ltd | Solid state suppressor |
GB9919764D0 (en) * | 1999-08-21 | 1999-10-27 | Koninkl Philips Electronics Nv | Thyristors and their manufacture |
JP5618578B2 (en) * | 2010-03-12 | 2014-11-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55124262A (en) * | 1979-03-16 | 1980-09-25 | Mitsubishi Electric Corp | Bidirectional thyristor |
JPS56150862A (en) * | 1980-04-24 | 1981-11-21 | Nec Corp | Semiconductor device |
JPS57196569A (en) * | 1981-05-27 | 1982-12-02 | Toshiba Corp | Bidirectional thyristor |
-
1984
- 1984-12-28 JP JP59278726A patent/JP2510972B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JPS61158179A (en) | 1986-07-17 |
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