JPS59148354A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPS59148354A JPS59148354A JP2201183A JP2201183A JPS59148354A JP S59148354 A JPS59148354 A JP S59148354A JP 2201183 A JP2201183 A JP 2201183A JP 2201183 A JP2201183 A JP 2201183A JP S59148354 A JPS59148354 A JP S59148354A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead frame
- semiconductor device
- parts
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の伎術分野］
本発明は、半導体装置用リードフレームに係り、特に半
導体装置を組立だ後、リードフレームの連結部分を個々
に切断することなく、半導体装置の電気的特性の測定、
あるいは検査を可能にした半導体装置用リードフレーム
に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a lead frame for a semiconductor device, and in particular, the present invention relates to a lead frame for a semiconductor device. Measuring electrical properties,
Or it relates to a lead frame for a semiconductor device that enables inspection.
［発明の技術的背景］
樹脂モールド型半導体装置を製作する場合、量産効果等
を期待し得るところから、たとえば第１図（Ａ）、（Ｂ
）に示すような構造のリードフレームが使用されている
。[Technical Background of the Invention] When manufacturing a resin molded semiconductor device, it is possible to expect mass production effects, so for example, the method shown in FIGS.
) is used.
すなわち、同図（Ａ）に示すものは、外枠１の対向位置
を互いに連結する連結部２を設け、この連結部２と外枠
１０対向側とからリード部３，４を連続１て形成したも
のである。That is, the device shown in FIG. 1A is provided with a connecting portion 2 that connects opposing positions of the outer frame 1 to each other, and leads 3 and 4 are continuously formed from the connecting portion 2 and the opposite side of the outer frame 10. This is what I did.
そして、このリード部３，４のいずれか一方に半導体ペ
レット５を載置して固定し、このペレット５と使方のリ
ードフレーム４との間を金属細線６にてワイヤボンデン
グ等により結線した後、破線で示す部分を樹脂モールド
し、モールド部７を形成する。Then, a semiconductor pellet 5 was placed and fixed on either one of the lead parts 3 and 4, and the pellet 5 and the lead frame 4 to be used were connected with a thin metal wire 6 by wire bonding or the like. Thereafter, the portion indicated by the broken line is molded with resin to form the molded portion 7.
最後に各リード部３，４を連結部２および外枠１から切
離して個々の半導体装置とする。Finally, each lead portion 3, 4 is separated from the connecting portion 2 and outer frame 1 to form an individual semiconductor device.
また、第１図に示すものは本発明者等が先に提案′した
ものであるが、このリードフレーム１０の構造は、電極
板となる導電性金属板上に化学的工ツヂング可能な樹脂
、たとえばポリイミド樹脂を張り合せた合板を所定の形
状に化学的エツチングしたものである。The lead frame 10 shown in FIG. 1 was previously proposed by the present inventors, but the structure of this lead frame 10 consists of a resin that can be chemically processed, For example, it is made by chemically etching plywood laminated with polyimide resin into a predetermined shape.
すなわち、連結部１１、リード部１２および半導体ペレ
ットが収納されるパッケージ部１３が化学的エツチング
により形成される。That is, the connecting portion 11, the lead portion 12, and the package portion 13 in which the semiconductor pellet is housed are formed by chemical etching.
上記のパッケージ部１３の底面は、同図（Ｃ）に示すよ
うに化学的エツチングによって形成された細い溝１４に
よって互いに絶縁分離され、この分離されたいずれか一
方に半導体ペレット１５を載置して固定し、他方のリー
ド部１２と連結されたパッケージ部１３の底面と金属細
線１６により結線しｌｃ後、パッケージ部１３内に樹脂
１７を充填して硬化させる。その後は、リード部１２を
連結部１１およびパッケージ部１３を連結する連結部か
ら切離して個々の半導体装置とするものである。The bottom surfaces of the package parts 13 are insulated and separated from each other by thin grooves 14 formed by chemical etching, as shown in FIG. After fixing and connecting the bottom surface of the package part 13 connected to the other lead part 12 with the thin metal wire 16, the package part 13 is filled with resin 17 and hardened. Thereafter, the lead portion 12 is separated from the connecting portion connecting the connecting portion 11 and the package portion 13 to form individual semiconductor devices.
（）かるに、上記のいずれのリードフレームを使用する
にしても完成した半導体装置を個々に切離さないで電気
的特性のチェック等の試験、測定をすることはできない
。(2) However, no matter which of the above lead frames is used, it is not possible to perform tests or measurements such as checking electrical characteristics without separating the completed semiconductor devices individually.
すなわち、リード部が連結部あるいは外枠と連続して形
成されているので、いずれか一方のリード部あるいは双
方のリード部を切離さないと隣接する半導体装置との電
気的絶縁がとれず、この半導体装置の試験、測定ができ
ない。In other words, since the lead portion is formed continuously with the connecting portion or the outer frame, electrical insulation from the adjacent semiconductor device cannot be achieved unless one or both lead portions are separated. Unable to test or measure semiconductor devices.
反面、双方のリード部を切離す場合には試験、測定のた
めに再び半導体装置を整列させる工程が必要となること
、また一方のリード部を切離す場合には、試験、測定後
に再び切離す工程を必要となる等、工数がかかる問題が
ある。On the other hand, when both lead parts are separated, a process is required to align the semiconductor devices again for testing and measurement, and when one lead part is separated, the semiconductor device must be separated again after testing and measurement. There is a problem that it takes a lot of man-hours, such as the need for a process.
［発明の目的］
本発明は、上記の事情に基きなされたもので、完成した
半導体装置を個々に切離すことなく、電気的特性チェッ
ク等の試験、測定を可能にした半導体リードフレームを
提供することを目的とする。[Object of the Invention] The present invention was made based on the above-mentioned circumstances, and provides a semiconductor lead frame that enables tests and measurements such as checking electrical characteristics without separating completed semiconductor devices individually. The purpose is to
［発明の概要］
すなわち、本発明は、複数のリード部と、このリード部
の少なくとも１つのリード部と電気的絶縁層を介して接
続された連結部とを有するをことを特徴とする半導体装
置用リードフレームである。[Summary of the Invention] That is, the present invention provides a semiconductor device comprising a plurality of lead portions and a connecting portion connected to at least one of the lead portions via an electrically insulating layer. This is a lead frame for use.
［発明の実施例］
第２図は、本発明に係る半導体装置用リードフレームの
製造過程を示す。すなわち、導電性金属板２０上に化学
的エツヂング可能な絶縁樹脂層、たとえばポリイミド樹
脂層２１を形成し、この樹脂層２１上に必要に応じ補強
用の金属板２２を設けた合板２３を用意しくＡ）、次い
で通常の写真蝕刻法により同図（Ｂ）のように化学的エ
ツチングづる。[Embodiments of the Invention] FIG. 2 shows a manufacturing process of a lead frame for a semiconductor device according to the present invention. That is, prepare a plywood 23 in which a chemically etched insulating resin layer, for example, a polyimide resin layer 21 is formed on a conductive metal plate 20, and a reinforcing metal plate 22 is provided on this resin layer 21 as necessary. A), and then chemically etched as shown in Figure (B) using a conventional photolithography method.
すなわら、まず、絶縁樹脂層２１の上下面に設けられた
金属板２０．２２を図示のように所定の形状に化学的エ
ツチングし、次いで同図（Ｃ）に示すように前記樹脂層
２１を掘り込んでパッケージ部２３および電気的絶縁層
２４を形成する。That is, first, the metal plates 20 and 22 provided on the upper and lower surfaces of the insulating resin layer 21 are chemically etched into a predetermined shape as shown in the figure, and then the resin layer 21 is etched as shown in FIG. A package portion 23 and an electrically insulating layer 24 are formed by digging.
なお、下面の導電性金属板２０は、化学的エツチングに
より細溝２５が形成され、第３図の平面図に示すように
パッケージ部２３の内部で互いに絶縁分離された島状の
電極部２５．２６を有するリード部２７が形成される。Note that the conductive metal plate 20 on the lower surface has a thin groove 25 formed by chemical etching, and as shown in the plan view of FIG. 3, island-shaped electrode portions 25. A lead portion 27 having 26 is formed.
このリード部２７．２７は、それぞれ電気４的絶縁層２
４．２４を介して図示を省略したリードフレームの連結
部と接続されている；
第４図は、隣接するパッケージ間を絶縁樹脂層２４ａで
連結したもので、この連結部となる樹脂層２４ａも前記
同様に化学的エツチングにより形成するものである。The lead portions 27 and 27 are electrically insulating layers 2 and 27, respectively.
4. It is connected to a connection part of a lead frame (not shown) through 24. In Fig. 4, adjacent packages are connected by an insulating resin layer 24a, and the resin layer 24a which becomes this connection part is also connected. It is formed by chemical etching in the same manner as above.
また、この樹脂層２４ａは、同図（Ｂ）に示すように最
終的に同図（Ａ）のＣ−Ｃ線により切断される。Further, this resin layer 24a is finally cut along the line CC in FIG. 12A, as shown in FIG.
上記のパッケージ部２３内には、第１図（Ｃ）に示すよ
うに半導体ペレットが収納され、金属細線で所定の結線
が施こされた後、モールド用樹脂を充填し、これを硬化
させて半導体装置を完成する。As shown in FIG. 1(C), semiconductor pellets are housed in the package part 23, and after predetermined connections are made with thin metal wires, molding resin is filled and cured. Complete the semiconductor device.
上記の場合、互いに隣接する半導体装置は、リードフレ
ーム上の電気的樹脂層２４．２４ａにより電気的に絶縁
分離されているので個々の半導体装置に分離することな
く、電気的特性チェツ々等の試験、測定が可能である。In the above case, since the semiconductor devices adjacent to each other are electrically insulated and separated by the electrical resin layer 24, 24a on the lead frame, tests such as electrical characteristics can be performed without separating the semiconductor devices into individual semiconductor devices. , measurement is possible.
第５図は、本発明の他の実施例を示すものである。FIG. 5 shows another embodiment of the invention.
この実施例では、帯状の金属板２０の長手方向に沿って
２本の平行な電気的絶縁層２４ｂを設ける。In this embodiment, two parallel electrically insulating layers 24b are provided along the longitudinal direction of the strip-shaped metal plate 20.
そして同図（Ｃ）に示すように金属板２０を所定の形状
に化学的エツチングし、連結部２８と連続した電極部２
９を有するリード部２９を形成する。The metal plate 20 is then chemically etched into a predetermined shape as shown in FIG.
A lead portion 29 having 9 is formed.
そして、この電極部２つには、同図（Ｄ）に示すように
半導体ベレット５を載置して固定し、金属細線６にて結
線した後、樹脂モールドをしてモールド部６を形成し、
半導体装置とする。Then, a semiconductor pellet 5 is placed and fixed on these two electrode parts as shown in FIG. 2(D), and after connecting them with a thin metal wire 6, resin molding is performed to form a mold part 6. ,
Semiconductor device.
上記の構成によれば、隣接するり一ド部２９が電気的絶
縁層２４ｂによって互いに絶縁分離されているので、前
記同様に個々に切離すことなく電気的試験、測定が可能
である。According to the above configuration, since the adjacent grid portions 29 are insulated and isolated from each other by the electrically insulating layer 24b, electrical tests and measurements can be performed without separating them individually, as described above.
なお、上記の実施例の場合、必ずしも化学的エツチング
可能な樹脂に限定されることなく一般の絶縁物質で差し
使えない。In the case of the above-mentioned embodiments, the material is not necessarily limited to chemically etched resins, and general insulating materials may be used.
第６図は、本発明に係るさらに伯の実施例を示ず。FIG. 6 does not show a further embodiment of the present invention.
この実施例では、トランジスタ、サイリスタ等の複数の
端子構造を有する半導体装置に適したリードフレームを
提供するもので、この実施例では、連結部２８と一連に
形成したリード部２９および連結部２８とは分離され、
かつリード部２９の両側に分離されて設けられたリード
部３０を絶縁層３１によって電気的に分離したもので、
この実施例にｄ３いても前記の絶縁層３１によって隣接
個所に形成された半導体装置を個々に分離することなく
、半導体装置の特性チェック等の試験、測定が可能であ
る。This embodiment provides a lead frame suitable for semiconductor devices having a plurality of terminal structures such as transistors and thyristors. is separated,
And lead parts 30 provided separately on both sides of the lead part 29 are electrically separated by an insulating layer 31,
Even in d3 of this embodiment, it is possible to perform tests and measurements such as checking the characteristics of the semiconductor devices without separating the semiconductor devices formed at adjacent locations by the insulating layer 31 into individual parts.
［発明の効果］
上記のように本発明は、リードフレーム上に電気的絶縁
層を設りたので半導体装置を製作後、個々に分離するこ
となく電気的特性チェック等の測定、試験が可能となり
、高能率の作業が実現できる。[Effects of the Invention] As described above, in the present invention, since an electrical insulating layer is provided on the lead frame, it is possible to perform measurements and tests such as checking electrical characteristics after manufacturing a semiconductor device without having to separate the devices individually. , high efficiency work can be achieved.
第１図（Ａ）、（Ｂ）および（Ｃ）は従来の半導体リー
ドフレームの一部切欠平面図および縦断面図、第２図（
Ａ）、（Ｂ）、（Ｃ）は本発明に係る半導体リードフレ
ームの製作過稈を示す図、第３図は上記工程によって製
作された前記リードフレームの一部切欠平面図、第４図
は前記リードフレームにおいて、半導体ペレットを収納
覆るための隣接づるパッケージ部分を電気的絶縁層で接
続したものを示し、同図（Ａ）はその平面図、同図（Ｂ
）は同図（Ａ＞のｘ−ｘに沿う断面図、第５図は本発明
に係る半導体装置用リードフレームの他の実施例を示し
、同図（Ａ＞は上記フレームを形成する前の金属板の一
部切欠平面図、同図（Ｂ）はその側面図、同図（Ｃ）は
上記金属板から形成した上記リードフレームの一部切欠
平面図、同図（Ｄ）は同図（Ｃ）のＹ−Ｙ線に沿う断面
図、第６図は本発明に係る半導体装置用リードフレーム
のさらに他の実施例を示し、同図（Δ）はその一部切欠
平面図、同図（Ｂ）はその裏面図である。
５・・・半導体ペレツ１〜．２８・・・連結部２９．３
１・・・リード部
２４．２４ａ 、２４ｂ ・・・電気的絶縁層出願代理
人 弁理士 菊 池 五 部Figures 1 (A), (B), and (C) are a partially cutaway plan view and longitudinal sectional view of a conventional semiconductor lead frame, and Figure 2 (
A), (B), and (C) are diagrams showing the progress of manufacturing the semiconductor lead frame according to the present invention, FIG. 3 is a partially cutaway plan view of the lead frame manufactured by the above process, and FIG. In the lead frame, adjacent package parts for storing and covering semiconductor pellets are connected by an electrically insulating layer, and FIG.
) is a cross-sectional view taken along the line xx of the same figure (A>, and FIG. A partially cutaway plan view of the metal plate, (B) a side view thereof, (C) a partially cutaway plan view of the lead frame formed from the metal plate, and (D) the same figure ( C) is a sectional view taken along the Y-Y line, and FIG. 6 shows still another embodiment of the lead frame for a semiconductor device according to the present invention, and FIG. B) is a back view thereof. 5... Semiconductor pellets 1 to .28... Connection portion 29.3
1... Lead part 24. 24a, 24b... Electrical insulating layer application agent Patent attorney Kikuchi, Department 5
Claims (2)
つのリード部・と電気的絶縁層を介して接続された連結
部とを有することを特徴とする半導体装置用リードフレ
ーム。(1) A plurality of lead parts and at least one of the lead parts
1. A lead frame for a semiconductor device, comprising two lead parts and a connecting part connected through an electrically insulating layer.
化学的エツチングして島状に形成したことを特徴とする
特許請求の範囲第１項記載の半導体装置用リードフレー
ム。(2) The lead frame for a semiconductor device according to claim 1, wherein the insulating layer is formed into an island shape by chemically etching an insulating resin layer provided on a metal plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2201183A JPS59148354A (en) | 1983-02-15 | 1983-02-15 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2201183A JPS59148354A (en) | 1983-02-15 | 1983-02-15 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59148354A true JPS59148354A (en) | 1984-08-25 |
Family
ID=12071054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2201183A Pending JPS59148354A (en) | 1983-02-15 | 1983-02-15 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59148354A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61177260A (en) * | 1985-02-01 | 1986-08-08 | Seiko Epson Corp | Color printer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4528100Y1 (en) * | 1967-09-27 | 1970-10-29 | ||
| JPS5381073A (en) * | 1976-12-27 | 1978-07-18 | Hitachi Ltd | Oroduction of resin seal type semiconductor device and lead frame used the same |
-
1983
- 1983-02-15 JP JP2201183A patent/JPS59148354A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4528100Y1 (en) * | 1967-09-27 | 1970-10-29 | ||
| JPS5381073A (en) * | 1976-12-27 | 1978-07-18 | Hitachi Ltd | Oroduction of resin seal type semiconductor device and lead frame used the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61177260A (en) * | 1985-02-01 | 1986-08-08 | Seiko Epson Corp | Color printer |
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