JPS5914338U - hybrid integrated circuit - Google Patents
hybrid integrated circuitInfo
- Publication number
- JPS5914338U JPS5914338U JP1982109116U JP10911682U JPS5914338U JP S5914338 U JPS5914338 U JP S5914338U JP 1982109116 U JP1982109116 U JP 1982109116U JP 10911682 U JP10911682 U JP 10911682U JP S5914338 U JPS5914338 U JP S5914338U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- bonding wire
- semiconductor chip
- wire connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の混成集積回路の平面図、第２図は本考案
の一実施例の平面図である。
１・・・・・・膜回路基板、２・・・・・・半導体チッ
プ搭載用導体ランド、３． ３’・・・・・・ボンディ
ングワイヤ接続ランド、４・・・・・・放熱台、５・・
・・・・半導体チップ、６・・・・・・ボンディングワ
イヤ、７・・・・・・放熱台上の位置出しパターン、８
・・・・・・ボンディングランドの位置出しパターン。FIG. 1 is a plan view of a conventional hybrid integrated circuit, and FIG. 2 is a plan view of an embodiment of the present invention. 1...Membrane circuit board, 2...Conductor land for mounting semiconductor chip, 3. 3'... Bonding wire connection land, 4... Heat radiation stand, 5...
... Semiconductor chip, 6 ... Bonding wire, 7 ... Positioning pattern on heat sink, 8
...Bonding land positioning pattern.
Claims (1)
に固着された半導体チップと、前記膜回路基板上に形成
されたボンディングワイヤ接続ランドと、このボンディ
ングワイヤ接続ランドと前記半導体チップの電極との間
を接続しているボンディングワイヤとを備えた混成集積
回路において、前記放熱台の半導体チップ搭載面または
前記ボンディングワイヤ接続ランド内の両方または何れ
か一方に位置出しパターンが設けられていることを特徴
とする混成集積回路。A heat dissipation stand fixed on a membrane circuit board, a semiconductor chip fixed on the heat dissipation stand, a bonding wire connection land formed on the membrane circuit board, and the bonding wire connection land and the semiconductor chip. and a bonding wire connecting between the electrodes of the hybrid integrated circuit, wherein a positioning pattern is provided on the semiconductor chip mounting surface of the heat sink and/or within the bonding wire connection land. A hybrid integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982109116U JPS5914338U (en) | 1982-07-19 | 1982-07-19 | hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982109116U JPS5914338U (en) | 1982-07-19 | 1982-07-19 | hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5914338U true JPS5914338U (en) | 1984-01-28 |
Family
ID=30254309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982109116U Pending JPS5914338U (en) | 1982-07-19 | 1982-07-19 | hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5914338U (en) |
-
1982
- 1982-07-19 JP JP1982109116U patent/JPS5914338U/en active Pending
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