JPS59141257A - Mounting method of circuit block for watch - Google Patents

Mounting method of circuit block for watch

Info

Publication number
JPS59141257A
JPS59141257A JP58014841A JP1484183A JPS59141257A JP S59141257 A JPS59141257 A JP S59141257A JP 58014841 A JP58014841 A JP 58014841A JP 1484183 A JP1484183 A JP 1484183A JP S59141257 A JPS59141257 A JP S59141257A
Authority
JP
Japan
Prior art keywords
circuit block
chips
chip
substrate
mounting method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58014841A
Other languages
Japanese (ja)
Inventor
Masahiro Tsukahara
塚原　正宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP58014841A priority Critical patent/JPS59141257A/en
Publication of JPS59141257A publication Critical patent/JPS59141257A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G17/00—Structural details; Housings
    • G04G17/02—Component assemblies
    • G04G17/06—Electric connectors, e.g. conductive elastomers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To narrow the space of a circuit block by mutually connecting IC chips directly by a gold wire, etc. without a substrate. CONSTITUTION:In a circuit block for an electronic wristwatch using an MOSIC chip, a substrate (C) and a main IC chip (A) are conducted electrically through wire bonding 1 through a pattern on the substrate (C). Chips (A) and (B) are connected directly through wire bonding 5 in order to give the sub-IC chip (B) electric conduction. Accordingly, the space of the circuit block can be narrowed while trouble is not generated on the substrate, and cost required for mounting can be reduced.

Description

【発明の詳細な説明】 本発明は、ＭＯ８工０チップを使う電子式腕時計におい
て使う回路ブロックの実装方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for mounting a circuit block used in an electronic wristwatch using an MO8-0 chip.

従来の電子腕時計用回路ブロックにおいて使用される回
路ブロックにおいては、基鈑をかいして、ＩＣチップ同
志の電気導通をもたせていた。In circuit blocks used in conventional circuit blocks for electronic wristwatches, electrical continuity between IC chips is provided through a base plate.

前記のような手段を用いる回路ブロックの短所としては
、 （１）基金をかいしてＩＣチップ同志の導通をとるため
のパターンを必要とするために、スペースを必要とする
。Disadvantages of circuit blocks using the above-mentioned means are as follows: (1) Since a pattern is required to establish conduction between IC chips using funds, space is required.

（２）　　（１）の理由により、基板上でのトラブルの
発生が品質を悪化させる原因となる。(2) Due to the reason in (1), occurrence of trouble on the board causes quality to deteriorate.

（３）実装時のコストにおいても、図に示すように、端
子の接続に２回実装している。(3) Regarding the cost of mounting, as shown in the figure, the terminals are connected twice.

本発明は、上記のような短所を改善した実装方法である
。The present invention is a mounting method that improves the above-mentioned shortcomings.

以下は本発明の詳細な説明する。The following is a detailed description of the invention.

第３図は本発明を示す回路ブロックである。Ｃで示すの
が基金であり、Ｃ上のパターンをかいしてＡで示すメイ
ンエ０チップに、ワイヤーボンディングなどの方法によ
り、ＣとＡとを電気的に導通させる。ここまでは今ｉで
と変わらない。FIG. 3 is a circuit block showing the present invention. The fund is indicated by C, and C and A are electrically connected to the main chip 0 indicated by A through a pattern on C by a method such as wire bonding. So far, it's the same as with i.

次に、ＡとＢで示すサプエ０の電気的導通をもたせるた
めに、ＡとＢとを直接ワイヤーポンディング等の方法に
より接続して、Ａ及びＢのＩＣチップ全駆動させるよう
にしている。Next, in order to provide electrical continuity between the sub-units 0 indicated by A and B, A and B are directly connected by a method such as wire bonding, so that all the IC chips of A and B are driven.

以上のような本発明により、次のような効果が生れる。The present invention as described above brings about the following effects.

（１）回路ブロックのスペースを狭くすることができ、
時計のモデル範囲が広がる。(1) The space of the circuit block can be narrowed,
The range of watch models expands.

（２）　　直接ＩＣチップ同志の導通をとるために、基
板上でのトラブルがなくなる。(2) Since the IC chips are directly connected to each other, troubles on the board are eliminated.

（３）実装に要する費用を低減できる。(3) Costs required for implementation can be reduced.

（４）　　ＩＣチップを保護するための保護材を減少さ
せることができるので、（１）で示すような効果がでる
。(4) Since the protective material for protecting the IC chip can be reduced, the effect shown in (1) can be obtained.

（５）保護材を一時期に基板上に塗布するために、（３
）で示すような効果がでる。(5) In order to apply the protective material on the substrate at once, (3
) will produce the effect shown.

【図面の簡単な説明】[Brief explanation of drawings]

第１図で示すのは、現在用いられている実装方法の一例
を示す。ＩＣチップ間に基板をかいしてワイヤーボンデ
ィングなどで接続している。 第２図は、第１図を平面化したものである。 第３図は本発明を示す。ＩＣチップ同志を直接ワイヤー
ボンディング等で接続している。 第４図は第３図を平面化したものである。 第５図は、第１図及び第２図の実装方法において、保護
材によりＩＣチップを保護した図である。 第６図は、第３図及び第４図の実装方法において、保護
材により工Ｃチップを保護した図である。 各図共に、Ａがメインエ０であり、Ｂがサプエ○であり
、○がＩＣチップをのせる基Ｑｅ示し、Ｄは保護材を示
し、番号（１，）　ｌ　（２）　、　（３）で示してい
るのは、ワイヤーボンディングされた金線である。 以　　　上 ｖ２田 １今咄FIG. 1 shows an example of a mounting method currently used. A board is placed between the IC chips and they are connected using wire bonding. FIG. 2 is a plan view of FIG. 1. FIG. 3 illustrates the invention. IC chips are directly connected to each other by wire bonding or the like. FIG. 4 is a plan view of FIG. 3. FIG. 5 is a diagram in which the IC chip is protected by a protective material in the mounting method of FIGS. 1 and 2. FIG. 6 is a diagram in which the C-chip is protected by a protective material in the mounting method of FIGS. 3 and 4. FIG. In each figure, A is the main element 0, B is the support element ○, ○ represents the group Qe on which the IC chip is placed, D represents the protective material, and the numbers (1,) l (2), (3) Shown is a wire-bonded gold wire. That's all v2 den 1 imaja

Claims (1)

【特許請求の範囲】[Claims] 同−基板上において、複数のＩＣチップを実装する場合
ＩＣチップ同志に電気的導通をもたせるためにＩＣチッ
プ間に、基板などをかいせずに直接工０チップ同志を金
線等で接続して、導通させることを特徴とする時計用回
路ブロックの実装方法。When mounting multiple IC chips on the same board, in order to provide electrical continuity between the IC chips, directly connect the chips with gold wire, etc., without using a board, etc., between the IC chips. A method for mounting a circuit block for a watch, which is characterized by conducting.
JP58014841A 1983-02-01 1983-02-01 Mounting method of circuit block for watch Pending JPS59141257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58014841A JPS59141257A (en) 1983-02-01 1983-02-01 Mounting method of circuit block for watch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58014841A JPS59141257A (en) 1983-02-01 1983-02-01 Mounting method of circuit block for watch

Publications (1)

Publication Number Publication Date
JPS59141257A true JPS59141257A (en) 1984-08-13

Family

ID=11872256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58014841A Pending JPS59141257A (en) 1983-02-01 1983-02-01 Mounting method of circuit block for watch

Country Status (1)

Country Link
JP (1) JPS59141257A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091769A (en) * 1991-03-27 1992-02-25 Eichelberger Charles W Configuration for testing and burn-in of integrated circuit chips
US20140257107A1 (en) * 2012-12-28 2014-09-11 Volcano Corporation Transducer Assembly for an Imaging Device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091769A (en) * 1991-03-27 1992-02-25 Eichelberger Charles W Configuration for testing and burn-in of integrated circuit chips
US20140257107A1 (en) * 2012-12-28 2014-09-11 Volcano Corporation Transducer Assembly for an Imaging Device

Similar Documents

Publication Publication Date Title
MY106847A (en) Method of connecting tab tape to semiconductor chip, and bump sheet and bumped tape used in the method.
JP3440238B2 (en) Mounting structure of semiconductor device on liquid crystal display device and semiconductor device
JPH02278740A (en) Packaging of semiconductor device
JPH03255657A (en) Hybrid integrated circuit device
JPS59141257A (en) Mounting method of circuit block for watch
JP3612174B2 (en) Liquid crystal display
JPH11186467A (en) Semiconductor device, lead frame used at manufacturing the device, and manufacture of lead frame
JPH0778903A (en) Method of bias voltage application in hybrid integrated circuit
JPS63122135A (en) Electrically connecting method for semiconductor chip
JP2822446B2 (en) Hybrid integrated circuit device
JPS60225439A (en) Ic-mounting structure
JPS6128318Y2 (en)
JPS5935461A (en) Mounting system of large scale integration
JPH0737932A (en) Semiconductor device and its mounting method
JPH0357619B2 (en)
JPH05315529A (en) Resin-sealed semiconductor device
JP2000269260A (en) Field effect transistor chip and its mounting method
JPS5855673Y2 (en) Electronic component mounting equipment
JPH0637234A (en) Semiconductor device
JPH04323837A (en) Semiconductor device
JPH05326833A (en) Semiconductor mounting substrate
JPH04355192A (en) Ic card
JPH09232899A (en) Package mount method for electronic element
JPH03116745A (en) Resin-sealed semiconductor device
JPS63131559A (en) Semiconductor device