JPS60225439A - Ic-mounting structure - Google Patents

Ic-mounting structure

Info

Publication number
JPS60225439A
JPS60225439A JP8140084A JP8140084A JPS60225439A JP S60225439 A JPS60225439 A JP S60225439A JP 8140084 A JP8140084 A JP 8140084A JP 8140084 A JP8140084 A JP 8140084A JP S60225439 A JPS60225439 A JP S60225439A
Authority
JP
Japan
Prior art keywords
conductive film
anisotropic conductive
spacer
stuck
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8140084A
Other languages
Japanese (ja)
Inventor
Akibumi Shiraki
白木　晃文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP8140084A priority Critical patent/JPS60225439A/en
Publication of JPS60225439A publication Critical patent/JPS60225439A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent edge short by a method wherein, in a structure of IC facedown bonding, a spacer frame for short prevention is provided between an anisotropic conductive film and the edge of an IC chip. CONSTITUTION:A spacer 8 is stuck as an another material after the anisotropic conductive film 7 is stuck to a mounting substrate 4, or is previously stuck closely, exfoliated in an unnecessary part with a mold, etc., thus made integral with the conductive film 7, and then stuck to the mounting substrate 4. Au bumps 9 and a wiring pattern 3 are subjected to positioning by optical observation. The chip edge short with the pattern 3 can be completely prevented by the spacer 8, and stable facedown bonding can be attained.

Description

【発明の詳細な説明】 く技術分野〉 本発明は、Ｘａ実装分野におけるフェースダウンボンデ
ィング構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a face-down bonding structure in the field of Xa mounting.

〈従来技術〉 従来のフェースダウン技術は、ＩＣチップのＡｆｉＰａ
ｄ上に半田バンプを形成し、基板パターンとりフロー等
により半田付けをしていた。<Conventional technology> The conventional face-down technology is the AfiPa IC chip.
Solder bumps were formed on d and soldered using a board pattern flow or the like.

第１図にその実施例を示す。１のＩＣチップに２０半田
バンプをメッキ等によυ形成し、基板４上に設けられた
配線パターン５と、半田付けによ多接合されている。An example is shown in FIG. 20 solder bumps are formed on one IC chip by plating or the like, and are connected to a wiring pattern 5 provided on a substrate 4 by soldering.

しかし、半田バンプは、細密化が難かしく、また、・半
田バンプ形成が特殊なため、チップコストアップはもち
ろん、供給メーカーが限られる等、問題が多い。However, it is difficult to miniaturize solder bumps, and since solder bump formation is special, there are many problems such as increased chip costs and limited supply manufacturers.

そこで、考案されたのが、第２図に示す異方性導電膜を
使ったフェースダウン構造である。Therefore, a face-down structure using an anisotropic conductive film as shown in FIG. 2 was devised.

５はＡλＰａｄ、７は異方性導電膜である。約１５０℃
、１０〜ｓ　ｏ　Ｋｆ／ｄ、約・１０就の熱圧着により
この異方性導電膜を介し、厚み方向のみ確実に導通接着
される。5 is AλPad, and 7 is an anisotropic conductive film. Approximately 150℃
, 10 to s o Kf/d, about 10 degrees, to ensure conductive bonding only in the thickness direction via this anisotropic conductive film.

しかしこの場合、Ａに示す位置でのエッヂショートの可
能性があシ、電特時に大きな問題となる。However, in this case, there is a possibility of an edge short at the position shown in A, which poses a big problem when electrical specials are needed.

これは、６の絶縁パシベーション膜がＩＣのダイシング
時に欠落し、ＩＣの外形エッヂの周りが電気的にむき出
しになるためである。This is because the insulating passivation film 6 is missing during dicing of the IC, and the area around the outer edge of the IC becomes electrically exposed.

〈目　的〉 本発明は、このエッヂショートを防止するためのもので
ある。<Purpose> The present invention is intended to prevent this edge short.

〈概　要〉 本発明では、異方性導電膜とＩＣチップエッヂの間に、
ショート防止のスペーサー枠を設ける。<Summary> In the present invention, between the anisotropic conductive film and the IC chip edge,
Provide a spacer frame to prevent short circuits.

〈実施例〉 本発明の実施例を第５図に示す。実装工程等は基本的に
第２図に示すものと同じである。<Example> An example of the present invention is shown in FIG. The mounting process and the like are basically the same as those shown in FIG.

８のスペーサーは、異方性導電膜を実装基板に貼合せ後
、別様材として貼合わせるか、又は異方性導電膜にあら
かじめベタで貼合せておき、不要部を型等で剥離し、異
方性導電膜と一体化してから実装基板に貼合わせるか、
どちらでもかまわない。The spacer 8 can be made by pasting the anisotropic conductive film on the mounting board and then pasting it as a separate material, or by pasting it solidly on the anisotropic conductive film in advance and peeling off the unnecessary part with a mold, etc. Either integrate it with the anisotropic conductive film and then attach it to the mounting board, or
Either is fine.

９の金バンプと５の配線パターンは、異方性導電膜の透
過率が６０％ぐらいのため充分に光学的に観察位置合わ
せが行なえる。Since the transmittance of the anisotropic conductive film is about 60%, the gold bumps 9 and the wiring pattern 5 can be sufficiently optically aligned for observation.

この構造によシ、パターン５とのチップエッヂショート
は完全に防止でき、安定したフェースダウンボンディン
グが達成される。With this structure, chip edge shorting with pattern 5 can be completely prevented and stable face-down bonding can be achieved.

また、本実施例では、スペーサーは能動面エリアには設
けなかったが、タイバー等で外観のスペーサーと継なぎ
、接合エリア以外全てにスペーサーが設けられる構造で
もかまわない。Further, in this embodiment, the spacer was not provided in the active surface area, but a structure in which the spacer is connected to the external spacer with a tie bar or the like, and the spacer is provided in all areas other than the joint area may be used.

〈効　果〉 本゛発明のスペーサー構造により、エッヂショート撲滅
がはかられ、安定した異方性導電膜フェースダウンが達
成される。<Effects> The spacer structure of the present invention eliminates edge shorts and achieves stable anisotropic conductive film face-down.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、半田バンプによる従来のフェースダウン構造
例 第２図は、従来の異方性導電膜を使ったフェースダウン
構造例 第６図は、本発明のフェースダウン構造例以　上 出願人　株式会社識訪精工舎 代理人　弁理士　最上　務Figure 1 is an example of a conventional face-down structure using solder bumps. Figure 2 is an example of a conventional face-down structure using an anisotropic conductive film. Figure 6 is an example of a face-down structure according to the present invention. Shikiwa Seikosha Company Agent Patent Attorney Tsutomu Mogami

Claims (1)

【特許請求の範囲】[Claims] 異方性導電膜を介して、ＩＣ能動面と回路基板パターン
をフェースダウンボンディングする構造において、前記
異方性導電膜とＩＣの外形エッヂの間に、薄いスペーサ
ー枠が設けられていることを特徴とするＩＣ実装構造。A structure in which an IC active surface and a circuit board pattern are face-down bonded via an anisotropic conductive film, characterized in that a thin spacer frame is provided between the anisotropic conductive film and an outer edge of the IC. IC mounting structure.
JP8140084A 1984-04-23 1984-04-23 Ic-mounting structure Pending JPS60225439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8140084A JPS60225439A (en) 1984-04-23 1984-04-23 Ic-mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8140084A JPS60225439A (en) 1984-04-23 1984-04-23 Ic-mounting structure

Publications (1)

Publication Number Publication Date
JPS60225439A true JPS60225439A (en) 1985-11-09

Family

ID=13745260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8140084A Pending JPS60225439A (en) 1984-04-23 1984-04-23 Ic-mounting structure

Country Status (1)

Country Link
JP (1) JPS60225439A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838061A (en) * 1996-03-11 1998-11-17 Lg Semicon Co., Ltd. Semiconductor package including a semiconductor chip adhesively bonded thereto
US6414397B1 (en) * 1998-12-02 2002-07-02 Seiko Epson Corporation Anisotropic conductive film, method of mounting semiconductor chip, and semiconductor device
US6737300B2 (en) * 2001-01-24 2004-05-18 Advanced Semiconductor Engineering, Inc. Chip scale package and manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838061A (en) * 1996-03-11 1998-11-17 Lg Semicon Co., Ltd. Semiconductor package including a semiconductor chip adhesively bonded thereto
US6414397B1 (en) * 1998-12-02 2002-07-02 Seiko Epson Corporation Anisotropic conductive film, method of mounting semiconductor chip, and semiconductor device
US6737300B2 (en) * 2001-01-24 2004-05-18 Advanced Semiconductor Engineering, Inc. Chip scale package and manufacturing method

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