JPS59136938A - Material of semiconductor substrate - Google Patents

Material of semiconductor substrate

Info

Publication number
JPS59136938A
JPS59136938A JP58010791A JP1079183A JPS59136938A JP S59136938 A JPS59136938 A JP S59136938A JP 58010791 A JP58010791 A JP 58010791A JP 1079183 A JP1079183 A JP 1079183A JP S59136938 A JPS59136938 A JP S59136938A
Authority
JP
Japan
Prior art keywords
powder
alloy
ferric
thermal expansion
ferric elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58010791A
Other languages
Japanese (ja)
Inventor
Mitsuo Osada
光生 長田
Sogo Hase
長谷　宗吾
Akira Otsuka
昭 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP58010791A priority Critical patent/JPS59136938A/en
Publication of JPS59136938A publication Critical patent/JPS59136938A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To obtain the titled material subject to both excellent thermal conductivity and thermal expansion coeffient causing no troubles such as poisonous property, scarcity and the like by a method wherein powder of W, Mo or alloy with specific grain size is respectively mixed with another powder comprising specific amount of Cu powder and ferric elements to be baked within reducing atmosphere after being pressurized and formed. CONSTITUTION:Powder of W, Mo or W-Mo alloy with mean grain size of 5-10mum is mixed with another powder comprising Cu powder with 5-20wt% of the final product ratio and ferric elements with 0.02-2 gross wt% of said two sorts of powder to be baked within reducing atmosphere after being pressurized and formed. The Cu ratio is specified to be 5-20wt% of the semiconductor substrate material so as to maintain the thermal expansion ratio within the range of 6-8(X10<-6>/ deg.C). On the other hand, the ferric elements (Fe, Ni, Co) are added so as to lower the temperature to produce fine alloy since W, Mo powder may be better-sintered with each other compared with the case of no addition of the ferric elements solidly soluble with either one of W, Mo, W-Mo and Cu solidly solved in W, Mo grains in case of baking to produce an alloy layer. It is not recommended to reduce the added amount of ferric elements down to 0.02wt% or less losing remarkable effect or to exceed 2wt% or more since the ferric elements solidly solved in Cu reduces the thermal conductivity of Cu part contained in a compound alloy.

Description

【発明の詳細な説明】 近年、ＩＣの演算速度の向上、トランジスクの電気容量
の増大、Ｇａ　−Ａｓ　ｒ　　Ｆ　ＥＴの出現厚により
、半導体素子の駆動時に半導体素子に発生する熱をいか
に放熱させるかという点が大きな問題となっている。半
導体素子内に発生する熱は半導体素子が塔載され、半導
体素子裏面と接合された基板を通してパッケージ外へ排
出される。従ってこの基板材料には熱伝導度が高い材料
を用いることが好ましい。[Detailed Description of the Invention] In recent years, with the improvement in the operation speed of ICs, the increase in the capacitance of transistors, and the appearance of Ga-As r FETs, it has become important to consider how to dissipate the heat generated in semiconductor devices when they are driven. This is a big problem. Heat generated within the semiconductor element is discharged to the outside of the package through the substrate on which the semiconductor element is mounted and bonded to the back surface of the semiconductor element. Therefore, it is preferable to use a material with high thermal conductivity for this substrate material.

ところで、近年前記パッケージとして七ラミックを用い
た七ラミックパッケージが多用されている。このパッケ
ージの場合、前記基板が電極取出し用のセラミック枠（
又は板）と一体化されている。従って基板材料としてｋ
ｌ　２０　ｓを主成分とする磁器を使用する場合には、
電極取出し用のセラミック枠（又は板）と一体焼成され
るため問題ないが、熱伝導性を向上させる為、ＷやＭｏ
等、電極取出し用の七ラミック枠（又は板）と異種の材
料を基板材料として用いる場合、以下の如き問題が生ず
る。Incidentally, in recent years, a hexalamic package using hexalamic has been frequently used as the package. In the case of this package, the substrate is a ceramic frame for taking out the electrodes (
or board). Therefore, as a substrate material, k
When using porcelain whose main component is l 20 s,
There is no problem because it is fired integrally with the ceramic frame (or plate) for taking out the electrode, but in order to improve thermal conductivity, W or Mo
When using a material different from the laminated frame (or plate) for taking out the electrodes as the substrate material, the following problems occur.

即ち、ＷやＭｏ　　等を基板材料として用いた場合、１
Ｅ極取出し用のセラミック枠（又は板）との接合は通常
銀鑞による鑞付方法が用いられる。この場合ＷやＭｏ　
　等はセラミックとの熱膨張率の差が大きい為、鑞付工
程における加熱後の冷却時に熱歪により七ラミック枠（
又は板）が破損するという問題が生ずる。That is, when W, Mo, etc. are used as the substrate material, 1
For joining with the ceramic frame (or plate) for taking out the E-electrode, a brazing method using silver solder is usually used. In this case, W or Mo
etc. has a large difference in thermal expansion coefficient from ceramic, so thermal distortion occurs during cooling after heating in the brazing process.
or the plate) may be damaged.

この為、熱膨張率がセラミックと近いＦ　ｅ　−Ｎ　ｉ
合金又はＦｅ−Ｎｉ　−Ｃｏ　　合金の薄板を基板とセ
ラミック枠（又は板）の間に介在させることが行なわれ
ているが、かかる方法は熱伝導上好ましくない。For this reason, the coefficient of thermal expansion is close to that of ceramics.
Although it has been attempted to interpose a thin plate of alloy or Fe--Ni--Co alloy between the substrate and the ceramic frame (or plate), such a method is unfavorable in terms of heat conduction.

一方、熱伝導性が良く、熱膨張率も七ラミック枠（又は
板）に近いＢｅＯを用いることが考えられているがＢｅ
Ｏは毒性を有する為、取扱いや製造が困難であり、さら
に人手することも困り）Ｗで実用的でない。On the other hand, it has been considered to use BeO, which has good thermal conductivity and a coefficient of thermal expansion close to that of a hexaramic frame (or board);
Since O is toxic, it is difficult to handle and manufacture, and it is also difficult to handle manually), which is impractical.

そこで発明者らは、熱膨張率、熱伝導率共に満足し、か
つ毒性や入手困難性などの間１ｍのない半導体基板材料
として、最終製品比５〜２０　ｗｔ％のＣｕ粉末と平均
粒度０．５〜５μのＷ粉末又はＭｏ　粉末又はＷ−ＭＯ
合金粉末とを混合成形した後、還元雰囲気中で焼成した
ことを特徴とする半導体基板材料を内容とする発明をし
た。（本願と同日付で特許出願した。）しかるに＋ｉｉ
Ｉ記発明の場合、部用しうるＷ粉末、Ｍｏ粉末、Ｗ−Ｍ
ｏ粉末の平均粒度の範囲であり、その要旨は平均粒度０
．５〜１０μのＷ粉末又はＭＯ粉末又はＷ−Ｍｏ　合金
粉末に最終製品比５〜２０　ｗｔ％のＣｕ粉末及び前記
両粉末総重量比０．０２〜２％の鉄族元素からなる粉末
を混合し、加圧成形した後、還元雰囲気中で焼成したこ
とを特徴とする半導体基板材料にある。Therefore, the inventors developed a semiconductor substrate material that satisfies both thermal expansion coefficient and thermal conductivity, and is free from toxicity and difficulty in obtaining materials by using Cu powder with an average particle size of 0.5 to 20 wt% in the final product. 5-5μ W powder or Mo powder or W-MO
The present invention includes a semiconductor substrate material characterized in that the material is mixed with an alloy powder, molded, and then fired in a reducing atmosphere. (A patent application was filed on the same date as the present application.) However, +ii
In the case of the invention described in I, W powder, Mo powder, W-M
This is the range of the average particle size of o powder, and its gist is that the average particle size is 0.
．． 5 to 10μ of W powder, MO powder, or W-Mo alloy powder is mixed with Cu powder of 5 to 20 wt% of the final product ratio and powder of iron group elements of 0.02 to 2% of the total weight ratio of both powders. , a semiconductor substrate material characterized by being press-molded and then fired in a reducing atmosphere.

本発明において、半導体基板材料中のＣｕ　　比を５〜
２０　ｗｔ％としたのは熱膨張率を６〜８（ＸＩＯ−６
／°Ｃ）の範囲に保たせる為である。即ち、セラミック
の熱膨張率は６．５〜７．５　（ｘｌＯ−６／℃）であ
り、前述の鑞付工程における破損を防止するには熱膨張
率を６〜８　（ｘｌＯ−６／℃）　　の範囲にする必要
があるからである。In the present invention, the Cu ratio in the semiconductor substrate material is 5 to 5.
The reason why the coefficient of thermal expansion is 6 to 8 (XIO-6) is set at 20 wt%.
/°C). That is, the coefficient of thermal expansion of ceramic is 6.5 to 7.5 (xlO-6/°C), and in order to prevent damage during the above-mentioned brazing process, the coefficient of thermal expansion is 6 to 8 (xlO-6/°C). ) must be within the range.

又、半導体素子として近年多用されているＧａ　−Ａｓ
　　を用いる場合、Ｇａ−Ａｓ０熱膨張率が６．７（Ｘ
ｌ　０−６７’Ｃ）であり、かつＳｉ　　に比し、非常
にもろい為、素子を塔載する基板の熱膨張率を素子に近
づける必要がある。この点からも熱膨張率を６〜８　（
ＸＩＯ−６／’Ｃ）　　にする必要があり、その為には
Ｃｕ比を５〜２０　ｗｔ％とする必要がある。In addition, Ga-As, which has been widely used as a semiconductor element in recent years,
When using Ga-As0, the thermal expansion coefficient is 6.7 (X
10-67'C) and is extremely brittle compared to Si, so it is necessary to make the coefficient of thermal expansion of the substrate on which the element is mounted close to that of the element. From this point of view, the coefficient of thermal expansion should be set at 6 to 8 (
XIO-6/'C), and for that purpose, the Cu ratio needs to be 5 to 20 wt%.

次に鉄族元素（ＦｅｔＮｉ　ｔｃｏ　）を添加したのは
鉄族元素がＷ＋Ｍｏ＋　Ｗ−Ｍｏ　　及びＣｕ　　の何
れとも固溶するχ−焼成時Ｗ、　Ｍｏ粒子と固溶し、合
金層を造るため、無添加の場合に比べ低温でＷｒ　Ｍｏ
粉末同志の焼結が進むため緻密な合金を得るために必要
な温度を低−Ｆさせることができるからである。この結
果、粒度の大きいＷｒ　Ｍｏｐ　Ｗ−Ｍｏ粉末を用いて
もＣｕ　　の蒸発消失が激しくなる１５００℃以下の温
度にて充分緻密な合金を得ることが出来る。Next, iron group elements (FetNitco) were added because iron group elements dissolve in solid solution with both W+Mo+W-Mo and Cu during χ-calcination with W and Mo particles to form an alloy layer. Wr Mo at a lower temperature than in the case of addition
This is because the sintering of the powders progresses, so the temperature required to obtain a dense alloy can be lowered to -F. As a result, even if WrMop W-Mo powder with a large particle size is used, a sufficiently dense alloy can be obtained at temperatures below 1500° C., where Cu evaporates and disappears rapidly.

このように鉄族元素の添加により緻密合金を得る為の温
度を低下させ、又、大きい粒度のＷｒ　Ｍｏ＋Ｗ−Ｍｏ
　　粉末を用いることが可能となるが、ｗｌＭＯｒＷ−
Ｍｏ　　粉末の粒度は１０μ以下にしておく必要がある
。又、下限については０．５μ　以上にしておく必要が
ある。これは、平均粒度０，５μ以下のＷｒＭｏ　＋Ｗ
−Ｍｏ　　粉末を用いると無添加の場合同様Ｃｕ　　と
の混合粉末を通常のプレス成形法にて成形すると粉末の
カサが大きくなり、加圧成形時粉末間に含有する空気の
ため成形密度を上げることが困難となり、かかる微細な
粉末は多量の酸素その他のガスを粉末表面に吸着してお
り、焼成時に吸着ガスを放出するため焼成後の合金に多
くの空孔が残る為である。In this way, by adding iron group elements, the temperature for obtaining a dense alloy can be lowered, and WrMo+W-Mo with a large grain size can be
Although it is possible to use powder, wlMOrW-
The particle size of the Mo powder must be 10μ or less. Further, the lower limit needs to be set to 0.5μ or more. This is WrMo +W with an average particle size of less than 0.5μ
-When Mo powder is used, as is the case without additives, when a mixed powder with Cu is molded using a normal press molding method, the bulk of the powder increases, and the compacting density increases due to the air contained between the powders during pressure molding. This is because such fine powders adsorb a large amount of oxygen and other gases on the powder surface, and the adsorbed gases are released during firing, leaving many pores in the fired alloy.

伺添加する鉄族元素の量が０．０２ｗｔ％　より少くな
ると、顕著な効果がなく、又２’ｗｔ％　を越えるとＣ
ｕ　　中に固溶した鉄族元素が複合合金中のＣｕ部分の
熱伝導度を下げ好ましくない。又、鉄族元素が２％を越
えた場合、焼成した複合合金の硬度が上り、後工程の機
械加工にも悪影響を与え好ましくないからである。When the amount of iron group elements added is less than 0.02wt%, there is no significant effect, and when it exceeds 2'wt%, C
The iron group elements dissolved in u are undesirable because they lower the thermal conductivity of the Cu portion in the composite alloy. Moreover, if the iron group element content exceeds 2%, the hardness of the fired composite alloy will increase, which is undesirable as it will have an adverse effect on the machining process in the subsequent process.

以下実施例について説明する。Examples will be described below.

実施例 第１表に示すような種々の平均粒径を有するＷ。Example W having various average particle sizes as shown in Table 1.

Ｍｏあるい′は、Ｗｒ　Ｍｏ合金−８２５ｍｅｓｈ　ノ
銅粉および０．８〜２．８μ　の平均粒径を有するＮｉ
ｐ　Ｆｅｎ　Ｃｏ　　の鉄族粉末を第１表に示す組成に
配合し、アトライタ混合機で３時間均一混合した粉末を
１ｔ／Ｃｒｎ２の圧力で型押した後、夫々の焼結条件（
第１表）でＨ２ガス雰囲気中で焼結を行った。Mo or ' is WrMo alloy-825mesh copper powder and Ni having an average particle size of 0.8 to 2.8μ.
The iron group powder of p Fen Co was blended into the composition shown in Table 1, and the powder was homogeneously mixed for 3 hours using an attritor mixer. After pressing the powder at a pressure of 1 t/Crn2, the respective sintering conditions (
Sintering was performed in an H2 gas atmosphere according to Table 1).

なお、第１表の試料番号１６．１７．３２は通常のプレ
ス成形法では良好な型押体が得られないため静水圧成形
法で得たものを焼結した。Note that sample numbers 16, 17, and 32 in Table 1 were obtained by hydrostatic pressing and sintered because a good stamped body could not be obtained by ordinary press molding.

かくして得られた合金について熱膨張係数および熱伝導
率を測定し、その結果を第１表に示す。The thermal expansion coefficient and thermal conductivity of the thus obtained alloy were measured, and the results are shown in Table 1.

第１表のうち、試料番号７．２０．３５の焼結合金をＳ
ｉ　　チップの塔載基板材料として用いたＩＣパッケー
ジは、ＩＣ実装工程でのＳｉ　　チップや他の外囲暴利
であるｋｌ　２０　ｇとの熱膨張係数の差が小さいため
何らの熱歪を生ぜず、またデバイスとしては熱放散性が
極めて良好であるためか命が伸び、信頼性の高いすぐれ
たＩＣを得ることが出来た。In Table 1, the sintered alloy of sample number 7.20.35 is S
The IC package used as the substrate material for the i-chip does not cause any thermal distortion because it has a small difference in thermal expansion coefficient from that of the Si chip or other external materials such as kl 20 g during the IC mounting process. Furthermore, as a device, the lifespan of the device was extended, probably due to its extremely good heat dissipation properties, and an excellent, highly reliable IC could be obtained.

以」二の如く本発明により得られた半導体基板材料は熱
伝導度、熱膨張係数共にすぐれた拐料であり、産性や人
手の困難性という問題もない、太容ｊ７に半導体に対応
しうる半導体基板４Ａ料であり、かつ、原料粉末として
粒度の大きい原料を用いることが出来、さらに焼成温度
を低下さすことが出来る。As described below, the semiconductor substrate material obtained by the present invention is a material with excellent thermal conductivity and coefficient of thermal expansion, and has no problems with productivity or labor difficulties, and is suitable for large-sized semiconductors. It is a semiconductor substrate 4A material that can absorb moisture, and a raw material with a large particle size can be used as the raw material powder, and the firing temperature can be lowered.

Claims (1)

【特許請求の範囲】[Claims] （１）平均粒度０．５〜１０μ　のＷ粉末又はＭｏ　粉
末又はＷ−Ｍｏ　　８−金粉末に最終製品比５〜２０　
ｗｔ％　のＣｕ粉末及び前記両粉末総重量比０．０２〜
２％の鉄族元素からなる粉末を混合し、加圧成形した後
、還元雰囲気中で焼成したことを特徴とする半導体基板
材料。(1) Average particle size of W powder or Mo powder or W-Mo 8-gold powder to final product ratio of 5-20μ
wt% of Cu powder and the total weight ratio of both powders is 0.02~
A semiconductor substrate material characterized in that a powder consisting of 2% iron group elements is mixed, pressure molded, and then fired in a reducing atmosphere.
JP58010791A 1983-01-25 1983-01-25 Material of semiconductor substrate Pending JPS59136938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58010791A JPS59136938A (en) 1983-01-25 1983-01-25 Material of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58010791A JPS59136938A (en) 1983-01-25 1983-01-25 Material of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS59136938A true JPS59136938A (en) 1984-08-06

Family

ID=11760158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58010791A Pending JPS59136938A (en) 1983-01-25 1983-01-25 Material of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS59136938A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001158901A (en) * 1999-10-08 2001-06-12 Osram Sylvania Inc Alloy for electric contact and electrode and producing method therefor
JP2012052182A (en) * 2010-08-31 2012-03-15 Toshiba Corp Mo-SINTERED PART FOR ALTERNATOR, ALTERNATOR USING THE SAME, AND AUTOMOBILE

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4918688A (en) * 1972-06-08 1974-02-19
JPS5062776A (en) * 1973-10-05 1975-05-28

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4918688A (en) * 1972-06-08 1974-02-19
JPS5062776A (en) * 1973-10-05 1975-05-28

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001158901A (en) * 1999-10-08 2001-06-12 Osram Sylvania Inc Alloy for electric contact and electrode and producing method therefor
JP2012052182A (en) * 2010-08-31 2012-03-15 Toshiba Corp Mo-SINTERED PART FOR ALTERNATOR, ALTERNATOR USING THE SAME, AND AUTOMOBILE

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