JPS5913331A - Forming method for pattern - Google Patents
Forming method for patternInfo
- Publication number
- JPS5913331A JPS5913331A JP12246582A JP12246582A JPS5913331A JP S5913331 A JPS5913331 A JP S5913331A JP 12246582 A JP12246582 A JP 12246582A JP 12246582 A JP12246582 A JP 12246582A JP S5913331 A JPS5913331 A JP S5913331A
- Authority
- JP
- Japan
- Prior art keywords
- film
- processed
- etching
- sections
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000012528 membrane Substances 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000005360 phosphosilicate glass Substances 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 6
- 238000000151 deposition Methods 0.000 abstract 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000011259 mixed solution Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 210000004379 membrane Anatomy 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 210000004303 peritoneum Anatomy 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体製造技術に係わシ、特にリフトオフ法
によるパターン形成方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor manufacturing technology, and particularly to improvements in a pattern forming method using a lift-off method.
従来、半導体基板上の膜の加工技術、つｔシバターン形
成方法としては、次の２つの方法が広く用いられている
。１つは、被加工膜を形成後所望するパターン形状にレ
ジスト膜を例えば光無光技術で形成し、このレジスト膜
をマスクとして被加工膜の不用な部分をエツチング除去
する方法である。もう１つは、被加工膜を形成する前に
所望するパターン形状以外の領域に予めレジスト膜を形
成しておき、被加工膜をレジスト膜の少なくとも側面の
一部が裏山するように堆積し、その後レジメ）ＩＩＩの
エツチングと同時にレジスト膜上の被加工膜を除去し、
所望のパターン形状に被加工膜を残置する方法、所謂リ
フトオフ法である。このリフトオフ法は前述の方法に比
べ、レジスト膜をマスクとして被加工膜をエツチングす
る工程が不用になり、上記エツチング工程中、特にドラ
イエツチング法を用いた場合、被加工膜の丁にある被膜
或いは半導体基板を、オーバーエツチングしたり汚染し
たシする等の問題がない。このため、リフトオフ法は、
微細なパターンの形成方法として、今後の半導体製造技
術において重要表位置を占めている。Conventionally, the following two methods have been widely used as a technique for processing a film on a semiconductor substrate and as a method for forming a pattern. One method is to form a resist film in a desired pattern shape after forming a film to be processed using, for example, a non-light technology, and use this resist film as a mask to remove unnecessary portions of the film to be processed. The other method is to form a resist film in advance in a region other than the desired pattern shape before forming the film to be processed, and deposit the film to be processed so that at least a part of the side surface of the resist film is on the back side. After that, simultaneously with the etching of regimen) III, the film to be processed on the resist film is removed,
This is a so-called lift-off method, in which a film to be processed is left in a desired pattern shape. Compared to the above-mentioned method, this lift-off method does not require the step of etching the film to be processed using a resist film as a mask. There are no problems such as over-etching or contamination of the semiconductor substrate. For this reason, the lift-off method
As a method for forming fine patterns, it will play an important role in future semiconductor manufacturing technology.
第１図＋１）〜（ｄ）はリフトオフ法を用いた従来のパ
ターン形成工程を示す断面図である。まず、第１図（１
）に示す如く半導体基板Ｊｌ上に、通常の写真食刻工種
を用いてレジスト膜１２を所望パターンに形成する。次
いで、第１図（ｂ）に示す如く被加工膜としての８１０
，１ｌｉＥＪＪを、全面にスパッタ蒸着により形成する
。Figures 1+1) to 1(d) are cross-sectional views showing a conventional pattern forming process using the lift-off method. First, Figure 1 (1
), a resist film 12 is formed in a desired pattern on a semiconductor substrate Jl using a conventional photolithography method. Next, as shown in FIG. 1(b), 810 is processed as a film to be processed.
, 1liEJJ are formed on the entire surface by sputter deposition.
その後、緩衝弗酸液で上記８１Ｏ，ｇｌＪＩをエツチン
グする。７このとき、平坦な部分に堆積した膜に比べて
、レジストＩＩ！ｘｘの周辺で形成された段差部１４に
堆積した膜はそのエツチング速度が１０〜２０倍速いた
め、約３０ （ｓａｃ）から６０ ［ｓｅｃ］のエツチ
ング時間で、第１図（ｅ）に示す如く段差部ｌイに堆積
し九８１ｏ、膜１３が除去されレジスト膜Ｊ２の側壁が
紐出する。Thereafter, the above 81O and glJI are etched with a buffered hydrofluoric acid solution. 7 At this time, compared to the film deposited on the flat area, the resist II! Since the etching rate of the film deposited on the stepped portion 14 formed around xx is 10 to 20 times faster, the etching time of approximately 30 (sac) to 60 [sec] is sufficient to remove the stepped portion 14 as shown in FIG. 1(e). At 981o, the resist film 13 is removed and the side wall of the resist film J2 is exposed.
次いで、第１図（ｄ）に示す如（上記レジスト膜１４を
紐出した側面から１例えば硫酸と過酸化水素水との混合
液によりエツチングすることにより、レジスト膜上に堆
積した８１０，１１１！７３も同時に除去し、所望のパ
ターン形状に８１０゜膜１３を半導体基板１１上罠残置
させることができる。Next, as shown in FIG. 1(d), 810, 111! 810, 111! deposited on the resist film are etched from the side surface from which the resist film 14 is drawn out using, for example, a mixed solution of sulfuric acid and hydrogen peroxide solution. 73 is also removed at the same time, and the 810° film 13 can be left on the semiconductor substrate 11 in a desired pattern shape.
しかしながら、この種の方法にあっては次のような間融
があった。すなわち、前記第１図（ｃｌに示す工程にお
いてレジス）［１ｊの側壁のみを麺出し、この線用部分
からレジス）Ｉｌｚ ｚを除去するようにしているので
、レジスト＃！１２のパターン寸法が大きい場合、例え
ば５ｏ。However, this type of method has the following problems. That is, in the process shown in FIG. 1 (cl), only the side wall of the resist 1j is exposed and the resist 1j is removed from this line portion, so that the resist #! If the pattern size of 12 is large, for example, 5o.
〔μｍ）Ｘ ５００ ［μｍ〕の方形のパターン形状を
持つ九場合、前記第１図（ｄ） Ｋも示す如く方形の中
心部のレジストｆＪ１２はエツチングされないで残る。In the case of a rectangular pattern shape of [μm]×500 [μm], the resist fJ12 at the center of the rectangle remains unetched, as shown in FIG. 1(d) K.
この場合、レジメＮ１１ｘｘ上の８ Ｉ Ｏ。In this case, 8 IO on regimen N11xx.
ｐｌｓは、不用なパターンとして残置することになシ、
また取シ残されたレジスト膜１２がその後の熱工程で、
半導体基板１ノを汚染する虞れがある。そして、このよ
うな不用パターンの残留や半導体基板の汚染等は、半導
体製品の歩留夛低下の大きな要因となっている。pls don't leave it as an unnecessary pattern,
In addition, the resist film 12 left behind is removed in the subsequent heat process.
There is a risk of contaminating the semiconductor substrate 1. Remaining unnecessary patterns, contamination of semiconductor substrates, etc. are major causes of a decrease in the yield of semiconductor products.
本発明の目的は、リフトオフ法を用いて被加工膜をパタ
ーニングするに際し、パターンの残留や、半導体基板の
汚染等を確実に防止することができ、半導体製品の歩留
り向上に寄与し得るパターン形成方法を提供することに
ある。An object of the present invention is to provide a pattern forming method that can reliably prevent pattern residue and contamination of a semiconductor substrate when patterning a processed film using a lift-off method, and that can contribute to improving the yield of semiconductor products. Our goal is to provide the following.
本発明の骨子は、レジスト膜の代シにＡｌ膜を用い、こ
のＡｌ膜に熱処理を施しヒロック（突起物）を生じせし
めることにある。Ａｌ膜を熱処理するとこのＡ／ＩＩに
ヒロックが生じることが知られている。そして、このヒ
ロックはＡＩ！膜の狭い領域よシ広い領域に形成され易
く、かつｔ／ＩＩ！の周辺よ〕中央部の方に形成され易
い。また、適当力エッチャントを選択することによ、９
，８１０．膜や８１．Ｎ４膜等の被加工膜をエツチング
することか＜Ａ／ＩＩ！をエツチングできるのも周知の
ことである。したがって、Ａ／膜にヒロックを生成せし
めたのち、Ａ／膜上に被加工膜を形成し従来と同様に被
加工膜に全面エツチングを施せば、ムｔＳの周辺側壁は
勿論のことヒロック側壁も紐出されることになる。The gist of the present invention is to use an Al film as a substitute for the resist film, and to heat-treat the Al film to form hillocks (protrusions). It is known that when an Al film is heat treated, hillocks occur in this A/II. And this hillock is AI! It is more likely to be formed in a wide area than a narrow area of the film, and t/II! It is more likely to be formed in the center than the periphery of the In addition, by selecting an appropriate force etchant, 9
, 810. Membrane and 81. Etching the film to be processed such as N4 film <A/II! It is also well known that it is possible to etch. Therefore, if a film to be processed is formed on the A/ film after forming hillocks on the A/ film and the entire surface of the film to be processed is etched as in the conventional method, not only the peripheral side wall of the mu tS but also the hillock side wall can be etched. The string will be pulled out.
このため、ｋｌＦｉｌの除去に際しＡ／膜は周辺側壁及
びヒロック側壁からエツチングされる仁とになシ、Ａ／
ｌＩの取９残しが極めて少なくなると考えられる。Therefore, during the removal of klFil, the A/ film is etched from the peripheral sidewall and the hillock sidewall.
It is thought that the remaining amount of lI will be extremely reduced.
本発明はこのよう表点に着目し、被加工膜をパターニン
グするに際し、表面が実質的に平坦表半導体基扱若しく
はこの基板表面にルーされた被膜上にＡｒ１１ｌｌを形
成し、このＡＩ！膜を所望パターンに選択エツチングし
たのち、上記Ａノ膜を熱処理し該Ａｐ膜表面に突起物を
生成せしめ、次いで段差部に堆積した膜が平坦部に堆積
した膜よシ速くエツチングされる性質を持つ被加工膜を
全面に形成し、次いで上記被加工膜を全面エツチングし
該被加工膜の段差側蔀に位置する部分を除去して前記Ａ
Ｊ膜側部及びＡ／１１！の突起物側部を蕗出せしめ、し
かるのち前記Ａ／膜を除去するようにした方法である。The present invention focuses on surface points as described above, and when patterning a film to be processed, Ar11ll is formed on a substantially flat surface semiconductor substrate or a film formed on the surface of this substrate, and this AI! After selectively etching the film into a desired pattern, the A film is heat-treated to generate protrusions on the surface of the Ap film, and then the film deposited on the stepped portions is etched more quickly than the film deposited on the flat portions. A to-be-processed film is formed on the entire surface, and then the entire surface of the to-be-processed film is etched, and the portion of the to-be-processed film located at the step side lip is removed.
J membrane side and A/11! In this method, the sides of the protrusions are exposed, and then the A/film is removed.
本発明によれば、大きなパターン形状のｐ、１膜でも容
易にエツチング除去することができ、Ａ／腹膜上形成し
た被加工膜を（１１し実に除去することができる。した
がって、取シ残し九＾ｌ！膜による汚染や不用パターン
の残留等を防止でき、半導体製品の歩留シ向上をはかる
ことができる。According to the present invention, even one film having a large pattern can be easily removed by etching, and the film to be processed formed on the peritoneum (A/11) can be actually removed. ^l! It is possible to prevent contamination caused by the film and the remaining of unnecessary patterns, and improve the yield of semiconductor products.
第２図（ｍｌ−（ｄ）は本発明の一実施例に係わるパタ
ーン形成工程を示す断面図である。まず、第２図国に示
す如＜ｉ／９コン基板２１上に薄い熱酸化膜２２を例え
ば５００ ＬＡ’） 程度形成し、この酸化膜２２上
に／ｌ膜２３を堆積する。続いて、通常の写真食刻法を
用い、Ａ／腰２３を所望パターニングに選択エツチング
し、ｋｌ膜２３を後述する被加工膜パターンと逆パター
ンに残置する。このとき入１１１１！ｐｓの加工にＨＩ
Ｅ（リマクテ１ブ・イオン・エツチング）技術を用いれ
ば、１４ｙＪ１１３の側壁を基板２１ＶＣ対して略垂直
にすることが可能になり、後の工程で段差部に堆積する
被加工膜を選択的にエツチングするのに適合がよい。次
いで、６００（’Ｃ，）以ドの熱工程を行うことにより
、第２図（ｂｌに示す如く入ｌ膜２３上にヒロック２４
を発生させる。上記ヒロック２４はｋｌＩ％ｚ ｓのパ
ターン形状の広い領域では比較的形成され易く、しかも
パターンの周辺部よ）中心部に出来易いという性質を持
つため、パターン周囲の形状を変えること々く、パター
ン中心部にヒロック２４を発生させることができる。FIG. 2 (ml-(d)) is a sectional view showing a pattern forming process according to an embodiment of the present invention. First, as shown in FIG. 22 is formed to a thickness of, for example, about 500 LA'), and a /l film 23 is deposited on this oxide film 22. Subsequently, the A/waist 23 is selectively etched into a desired pattern using an ordinary photolithography method, and the Kl film 23 is left in a pattern opposite to the film pattern to be processed, which will be described later. At this time, 1111! HI for PS processing
By using the E (remact ion etching) technology, it is possible to make the side wall of 14yJ113 almost perpendicular to the substrate 21VC, and the film to be processed that will be deposited on the stepped portion in a later process can be selectively etched. It is suitable for doing. Next, by performing a heat process at 600 ('C,) or higher, hillocks 24 are formed on the deposited film 23 as shown in FIG.
to occur. The above hillock 24 is relatively easy to form in a wide area of the pattern shape of klI%zs, and moreover, it is easy to form in the center (not the periphery of the pattern), so the shape of the pattern around the pattern is often changed. A hillock 24 can be generated at the center.
次に、スパッタ蒸着法或いはプラズマＯＶＤ法を用い、
全面に８ＩＯ２膜２５を４積する。Next, using a sputter deposition method or a plasma OVD method,
Four 8IO2 films 25 are stacked on the entire surface.
次いで、綬衝弗酸で約３０ ［ｓｅｃ］から５９（ｓｅ
ｅ）上記Ｓｉｎ、１１１５をエツチングする。このとき
、上記方法で形成した８■０．膜２５は１段差部に堆積
した膜が平坦部に堆積した膜により１０〜２０倍速いエ
ツチング速度を有するので、第１図（ｃ）に示す如くヒ
ロック２４とｋｌ１４２３の周辺との各段差部に堆積し
た膜が選択的に除去され、Ａ１１ｌｌ！２３の周辺側壁
及びヒロック２４が露出される。その後、ｋｌｐ／４２
Ｊを、例えば硫酸と過酸化水素水との混合液でエツチ
ングすると、Ａｊ膜２３上に堆積していたＳ１０゜膜２
５も同時に除去され、第２図（ｄ）に示す如く酸化ｆＪ
２６が所望のパターン形状に残置されることになる。Next, the mixture was heated with hydrofluoric acid for approximately 30 to 59 seconds.
e) Etching the above Sin, 1115. At this time, 8■0. The film 25 has an etching rate that is 10 to 20 times faster than the film deposited on a flat part. The deposited film is selectively removed and A11ll! The peripheral side walls of 23 and hillocks 24 are exposed. After that, klp/42
When J is etched, for example, with a mixed solution of sulfuric acid and hydrogen peroxide, the S10° film 2 deposited on the Aj film 23 is removed.
5 is also removed at the same time, and as shown in Figure 2(d), oxidized fJ
26 will be left in the desired pattern shape.
かくして木実流側方法では、ｋｌ！ｆＪ２ ｊの周辺側
壁のみならずヒロック２４０部分からもエツチングが進
行するため、ｋｌＩｌｔｉ２ｓは確実にエツチングされ
る。しかも、ｋｌｆｐ２ ｊのヒロック２４は、従来リ
フトオフされずに残り易い広い面積の中央部に多くなる
ので、１１１１！２ Ｊのエツチング残しを避け、不用
パターンの残留を除くのにきわめて有効である。また、
従来リフトオフ加工が困難とされていた広い面積のリフ
トオフ加工も容易になる。さらに、従来のレジス） ７
１％を用いた方法に比べ、６００Ｌ′Ｃ，）程度までの
高温工程が可能に々す、有機溶剤によるクエーハ洗浄が
可能になる等の利点もある。Thus, in the nut style method, kl! Since etching progresses not only from the peripheral side wall of fJ2j but also from the hillock 240 portion, klIlti2s is reliably etched. Moreover, since the hillocks 24 of klfp2 j are more likely to remain in the center of a wide area that is conventionally not lifted off and tend to remain, this is extremely effective in avoiding etching residues of 1111!2 J and removing unnecessary pattern residues. Also,
Lift-off processing of large areas, which was conventionally considered difficult to perform, becomes easier. In addition, conventional Regis) 7
Compared to the method using 1%, it has advantages such as being able to perform high-temperature processes up to about 600 L'C,) and making it possible to clean Quar with an organic solvent.
々お、本発明は上述した実施例に限定されるものではな
い。例えば、前記被加工膜はプラズマＯＶ Ｄ法やスパ
ッター蒸着法で形成した８１０、膜に限るものではなく
、七の他ＬＰＯＶＤ法で形成したリン硅化ガラス膜、プ
ラズマＯＶＤ法により堆積したシリコン窒化膜等であっ
てもよい。つまシ段差部に堆積した膜が平坦部に堆積し
た膜に比べてエツチング速度が速くなるという性質を持
つものであればよい。また、ｈｔ映のエッチャントは硫
酸と過酸化水素水との混合液に限る必要はなく、被加工
膜とのエッチソグ選択性のあるものであればよい。その
他、本発明の要旨を逸脱しない範囲で、種々変形して実
施することができる。However, the present invention is not limited to the embodiments described above. For example, the film to be processed is not limited to the 810 film formed by the plasma OVD method or the sputter evaporation method, but may also include a phosphosilicate glass film formed by the LPOVD method, a silicon nitride film deposited by the plasma OVD method, etc. It may be. Any material may be used as long as it has a property that the film deposited on the stepped portions has a faster etching rate than the film deposited on the flat portions. Further, the etchant for the HT film is not limited to a mixed solution of sulfuric acid and hydrogen peroxide, and may be any etchant that has etch selectivity with respect to the film to be processed. In addition, various modifications can be made without departing from the gist of the present invention.
第１図（ａ）〜＋ｄ）は従来方法によるパターン形成工
程を示す断面図、第２図（ａ）〜（ｄ）は本発明の一実
施例に係わるパターン形成工程を示す断面図である。
２１・・・シリコン基板（半導体基板）、２２・・・熱
酸化膜、２３・・・Ａ／膜、２４・・・ヒロック（突起
物）、２５・・・８１０．（被加工膜）。
出願人代理人 弁理土鈴 江 武 彦1(a) to +d) are sectional views showing a pattern forming process according to a conventional method, and FIGS. 2(a) to 2(d) are sectional views showing a pattern forming process according to an embodiment of the present invention. 21... Silicon substrate (semiconductor substrate), 22... Thermal oxide film, 23... A/film, 24... Hillock (protrusion), 25... 810. (Processed film). Applicant's agent Takehiko E, patent attorney
Claims (2)
板表面に形成された被膜上にＡ／膜を形成する工程と、
上記Ａ／膜を所望パターンに選択エツチングする工程と
、次いで上記Ａ／膜を熱処理し該Ａ／膜表面に突起物を
生成せしめる工程と、次いで段差部に堆積した膿が平坦
部に堆積した膜より速くエツチングされる性質を持つ被
加工膜を全面に形成する工程と、上記被加工膜を全面エ
ツチングし該被加工膜の段差側部に位置する部分を除去
して前記Ａｊｌｌ側部及びＡＩ！膜の突起物側部を紐出
せしめる工程と１次いで前記Ａ／膜を除去する工程とを
具備したことを特徴とするパーターン形成方法。(1) forming an A/film on a semiconductor substrate with a substantially flat surface or a film formed on the surface of this substrate;
A step of selectively etching the A/film into a desired pattern, then a step of heat-treating the A/film to form protrusions on the surface of the A/film, and then a film in which pus deposited on the stepped portions is deposited on the flat portions. A step of forming a film to be processed which has a property of being etched more quickly on the entire surface, etching the entire surface of the film to be processed and removing a portion of the film to be processed located on the step side, and etching the film on the Ajll side and the AI! A method for forming a pattern, comprising the steps of: stringing out the sides of the protrusions of the membrane; and (1) removing the A/membrane.
、プラズマＯｖＤによる８ｉ、Ｎ４１１！ｌ！、スパッ
タ蒸着による８ｉ０．膜、或いはＬＰＯｖＤによるリン
珪化ガラス膜であることを特徴とする特許請求の範囲第
１項記載のバタ、−ン形成方法。(2) The film to be processed is 8IO1 film by plasma OVD, 8i by plasma OvD, N411! l! , 8i0. by sputter deposition. 2. The method for forming a batten according to claim 1, characterized in that it is a film or a phosphosilicate glass film made by LPOvD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12246582A JPS5913331A (en) | 1982-07-14 | 1982-07-14 | Forming method for pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12246582A JPS5913331A (en) | 1982-07-14 | 1982-07-14 | Forming method for pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5913331A true JPS5913331A (en) | 1984-01-24 |
Family
ID=14836522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12246582A Pending JPS5913331A (en) | 1982-07-14 | 1982-07-14 | Forming method for pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5913331A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6361708B1 (en) | 1997-05-14 | 2002-03-26 | Nec Corporation | Method and apparatus for polishing a metal film |
-
1982
- 1982-07-14 JP JP12246582A patent/JPS5913331A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6361708B1 (en) | 1997-05-14 | 2002-03-26 | Nec Corporation | Method and apparatus for polishing a metal film |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH06177090A (en) | Manufacturing method of integrated circuit and integrated circuit manufactured by said method | |
| JPH04251925A (en) | Manufacture of semiconductor device | |
| JPS5913331A (en) | Forming method for pattern | |
| JPS58212136A (en) | Forming method for ultrafine pattern | |
| JPH07169755A (en) | Formation of narrow window or a groove | |
| JPS6213047A (en) | Manufacture of semiconductor device | |
| JP2003519912A (en) | Etching and ashing photoresist removal process | |
| JPS59150421A (en) | Manufacture of semiconductor device | |
| JPH06168917A (en) | Resist removing method | |
| JPS6161423A (en) | Dry etching method | |
| JPS6289324A (en) | Manufacture of semiconductor device | |
| JPH0122731B2 (en) | ||
| JPH05129253A (en) | Production of semiconductor device | |
| JPH01243426A (en) | Etching method for resist film | |
| JPH05267246A (en) | Manufacture of semiconductor device | |
| JPS60254733A (en) | Pattern forming method | |
| JPH03286578A (en) | Processing method for aluminum mask for niobium film etching | |
| JPH09181081A (en) | Fabrication of semiconductor device | |
| JPH11251286A (en) | Manufacture of silicon wafer | |
| JPH04256319A (en) | Manufacture of semiconductor device | |
| JPH01124241A (en) | Formation of device isolation region | |
| JPH11176807A (en) | Manufacture of semiconductor device | |
| JPS6194326A (en) | Manufacture of semiconductor element | |
| JPH0429316A (en) | Dry etching method | |
| JPH01286330A (en) | Manufacture of semiconductor device |