JPS59124760A - Read-only memory - Google Patents
Read-only memoryInfo
- Publication number
- JPS59124760A JPS59124760A JP58000102A JP10283A JPS59124760A JP S59124760 A JPS59124760 A JP S59124760A JP 58000102 A JP58000102 A JP 58000102A JP 10283 A JP10283 A JP 10283A JP S59124760 A JPS59124760 A JP S59124760A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal
- bit line
- rom
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
(1)発明の属する技術分野の説明
本発明は読み出し専用メモリにかかり、とくにM OS
集積回路のマスクプログラム方式の読み出し専用メモ
リ(マスクR,OM)に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a read-only memory, and in particular to a MOS
The present invention relates to a mask programmable read-only memory (mask R, OM) of an integrated circuit.
(2)従来技術の説明
よく知られているように、この種の読み出し専用メモI
J(ROM)においては%ROMデータの書き換えを行
なう工程が遅い工程であるほど、R,0Mデータの決定
からICの完成までの期間が短くなり有利であり、また
ROMセルの大きさが小さいほど、チップサイズ等の理
由により有利となる。(2) Description of the prior art As is well known, this type of read-only memo I
In J(ROM), the slower the process of rewriting the %ROM data, the shorter the period from the determination of R, 0M data to the completion of the IC, which is advantageous, and the smaller the ROM cell size, the more advantageous it is. This is advantageous due to factors such as chip size.
メタル2層の場合のROMは第1図に示すように2層目
のメタルのビット線とR,0MセルをなすMOSFET
のドレイン電極の開音2層目のメタルで接続することに
より、・第1の出力レベルを得、2層目のメタルで接続
しないでおくことによ!It、第2の出力レベル全得る
ような、つまり2層目のメタルの工程でR(JMデータ
の貫き換えを行なうものであった。As shown in Figure 1, the ROM in the case of two metal layers has a MOSFET that forms an R, 0M cell with the bit line of the second metal layer.
By connecting the open sound of the drain electrode with the metal of the second layer, the first output level is obtained, and by leaving it unconnected with the metal of the second layer! It was intended to obtain the full second output level, that is, to perform R (JM data penetration) in the second layer metal process.
しかしながら従来のこの方法では、ROMデータの書き
換え工程は最終工程であるがROMセルに接続した1層
目のメタルと2層目のメタルとの接続点(スルーホール
)をビット線から離さねばならない為、セルの大きさが
ビットガ同に大きくなる、という欠点があった。However, in this conventional method, although the ROM data rewriting process is the final process, the connection point (through hole) between the first layer metal and second layer metal connected to the ROM cell must be separated from the bit line. However, the disadvantage is that the size of the cell becomes as large as the bit size.
(3)発明の詳細な説明
不発明は1層目のメタルと2層目のメタル全接続するス
ルーホールの工程においてROMデータの書き換えを行
なうことにより、R,0Mセルの面積の小さいMO8集
積回路の読み出し専用メモリを提供することを目的とし
ている。(3) Detailed description of the invention The invention is based on an MO8 integrated circuit with a small R, 0M cell area by rewriting ROM data in the process of through-holes that connect all the metals in the first layer and the metals in the second layer. The purpose is to provide read-only memory.
(4)発明の構成
本発明は、ワード線とビット線の交わる位置にMOSF
ET ?有するようなMO8集積回路の読み出し専用メ
モリにおいて、前記ビット線を2層目のメタルで構成し
、前記ワード線QPolySiで構成し、前記MO8F
ETのソース電極を基準電位に接続し、前記MO8FE
Tのゲート電極を前記ワード線に接続し、前記MO8F
ETのドレイン電極を1層目のメタルと接続し、この1
層目のメタルとビット線の2層目のメタルの間にスルー
ホールを設けることにより、第1の出力レベルを得、前
記ドレイン電極に接続した1層目のメタルと前6己ビツ
ト線の2層目のメタルとの間にスルーホールを設けずに
おくことによりN2の出力レベルを得ることを特徴とす
る読み出し専用メモリである。(4) Structure of the Invention The present invention provides a MOSFET at the intersection of the word line and the bit line.
ET? In the read-only memory of the MO8 integrated circuit, the bit line is made of a second layer of metal, the word line is made of QPolySi, and the MO8F
The source electrode of ET is connected to a reference potential, and the MO8FE
The gate electrode of T is connected to the word line, and the gate electrode of MO8F is connected to the word line.
Connect the drain electrode of ET to the first layer of metal, and
The first output level is obtained by providing a through hole between the first layer metal and the second layer metal of the bit line. This is a read-only memory characterized in that an output level of N2 is obtained by not providing a through hole between the metal layer and the metal layer.
(5)この発明の詳細な説明 次に本発明の実施例について図面を参照して説明する。(5) Detailed description of this invention Next, embodiments of the present invention will be described with reference to the drawings.
第2図を参照すると本発明の第1の実施例は、ROMセ
ルをなすMO8FE’r AおよびBのソース電極?G
ND配線3に接続し、ゲート電極2けワード線を構成し
ドレイン電極1は、1層目のメタル6に接続されており
、ビット線5a、5bは、2層目のメタルで構成されて
おり1層目のメタル6とビット線の2層目のメタルとの
重なった部分にスルーホール14全置くことによfi、
R,OMセルAのドレイン電極はビット線に接続され
、ワード線が選択された際にビット線5aの電位?L。Referring to FIG. 2, the first embodiment of the present invention has source electrodes of MO8FE'r A and B forming a ROM cell. G
The gate electrode 1 is connected to the ND wiring 3 and forms two word lines. The drain electrode 1 is connected to the first layer metal 6, and the bit lines 5a and 5b are made of the second layer metal. By placing all the through holes 14 in the overlapped part of the first layer metal 6 and the second layer metal of the bit line, fi,
The drain electrode of the R, OM cell A is connected to the bit line, and when the word line is selected, the potential of the bit line 5a? L.
Wレベルにおと丁。又、ROMセルセルようにドレイン
接続した1層目のメタル6とビット線の間に、スルーホ
ールを置かないと、ビ、)線5 bは、ROMセルセル
ドレイン電極とは接続されず、ワード線2が選択された
際にも、ビット線5bの電位hH4gh レベルに保た
れる。このようにスルホールを設けるか、設けないかに
より、ROMデータの変更が可能となり、第1図の2層
目のメタルで書き換える場合に比べて、第1図における
ビット線とスルーホールの間隔分だけ、セルサイズを小
さくできる。Almost at W level. Also, if a through hole is not placed between the bit line and the first layer metal 6 whose drain is connected like a ROM cell, the line 5b will not be connected to the ROM cell drain electrode and will be connected to the word line 2. Even when the bit line 5b is selected, the potential of the bit line 5b is maintained at the hH4gh level. In this way, depending on whether or not to provide a through hole, it is possible to change the ROM data, and compared to the case where the data is rewritten using the second layer of metal in Fig. 1, it is possible to change the ROM data by the distance between the bit line and the through hole in Fig. 1. , the cell size can be reduced.
次に、第3図を参照すると本発明の第2の実施例は、N
2図におけるスルーホール14の位置をドレイン電極の
ワード線に移したものであり、このような構造にするこ
とによフビット方向のセルサイズが短くて済み、面積的
にも第1図の場合に比べて約3割程度小さくて済む。Next, referring to FIG. 3, a second embodiment of the present invention has N
The position of the through hole 14 in Fig. 2 has been moved to the word line of the drain electrode, and by adopting this structure, the cell size in the fbit direction can be shortened, and the area is also smaller than in the case of Fig. 1. It is about 30% smaller than the previous one.
次にN4図を参照すると本発明の第3の実施 5−
例は、第3図におけるp o 1 y 8 +のワード
線2と平行に1層目のメタル22vi?配置し、メモリ
セル数ビット毎にPo 1 yS iのワードa2との
コンタクト32を設けたものであり、このような構造に
することによりワード線の抵抗を減らすことができ、規
模が大きくなった場合に問題となるワード線抵抗による
遅延を少くすることができる。Next, referring to Figure N4, the third embodiment of the present invention 5-example shows the first layer of metal 22vi? parallel to the word line 2 of po1y8+ in Figure 3. A contact 32 with word a2 of Po 1 yS i is provided for every few bits of memory cells. By adopting this structure, the resistance of the word line can be reduced and the scale can be increased. It is possible to reduce delays caused by word line resistance, which can be a problem in some cases.
(6)発明の詳細な説明
本発明は以上説明したように、2層メタル構造をもった
マスクROMの書き換えをスルーホールで行なうことに
より、2層目のメタルで書き換える場合に比べて、セル
面積を小さくする効果がある。(6) Detailed Description of the Invention As explained above, the present invention enables rewriting of a mask ROM having a two-layer metal structure using through holes, thereby reducing the cell area compared to the case where rewriting is performed using the second layer of metal. It has the effect of reducing the
第1図は、2層目のメタルで書き換える場合のR,0M
セルのバタン例を示す図、第2図は本発明の第1の実施
例を示したバタン図、第3図は本発明の第2の実施例を
示したバタン図、第4図は木 6 −
発明の第3の実施例を示したバタン図である。
A、 B・・・・・・ROMセルをなすMOSFET、
1・・・・・・ROMセルをなすMO8F’ET
のドレイン電極、2・・・・・po I ySiワード
線、3・・・・・・GND拡散層配線、4・・・・・ス
ルーホール、5a、5b・・・・・・ビット線、6・・
・・・ドレイン電極に接続した1層目のメタル、14・
・・・・・スルーホール、22・・・・・・1層目のメ
タルのワード線、32・・・・・・2と22のコンタク
ト。
榮1図Figure 1 shows R, 0M when rewriting with the second layer of metal.
Figure 2 is a diagram showing an example of a cell slam; Figure 2 is a diagram showing a first embodiment of the present invention; Figure 3 is a diagram showing a second embodiment of the invention; Figure 4 is a diagram showing a tree. - It is a button diagram showing a third embodiment of the invention. A, B... MOSFET forming the ROM cell,
1...MO8F'ET forming a ROM cell
drain electrode, 2... po I ySi word line, 3... GND diffusion layer wiring, 4... through hole, 5a, 5b... bit line, 6・・・
...First layer metal connected to the drain electrode, 14.
...Through hole, 22...First layer metal word line, 32...Contact between 2 and 22. Sakae 1 figure
Claims (1)
るシリコンゲート開O8集積回路の読み出し専用メモリ
において、前記ビット線を2層目のメタルで構放し、前
記ワード線をシリコンで構成し、前記MO8FETのソ
ース電極全基準電位に接続し、前記上〜J(、l5FE
Tのゲート電極全前記ワード線VC接続し、前記MO8
FETのドレイン電極に接続した1層目のメタルと前記
ビット線の2層目のメタルの間にスルーホールを設ける
ことVCより、第1の出力レベルを得、前記スルーホー
ルを設けずにおくことにより、第2の出力レベルを得る
ことを特徴とする読み翳し専用メモリ。 −In a read-only memory of a silicon gate open O8 integrated circuit having a MOSFET at the intersection of a word line and a bit line, the bit line is left open with a second layer of metal, the word line is made of silicon, and the source of the MO8FET is Connect the electrodes to all reference potentials, and
All the gate electrodes of T are connected to the word line VC, and the MO8
A through hole is provided between the first layer metal connected to the drain electrode of the FET and the second layer metal of the bit line. A first output level is obtained from the VC, and the through hole is not provided. A read-only memory characterized by obtaining a second output level by. −
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58000102A JPS59124760A (en) | 1983-01-04 | 1983-01-04 | Read-only memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58000102A JPS59124760A (en) | 1983-01-04 | 1983-01-04 | Read-only memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59124760A true JPS59124760A (en) | 1984-07-18 |
JPH0345552B2 JPH0345552B2 (en) | 1991-07-11 |
Family
ID=11464726
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58000102A Granted JPS59124760A (en) | 1983-01-04 | 1983-01-04 | Read-only memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59124760A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62112160U (en) * | 1985-12-28 | 1987-07-17 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56147472A (en) * | 1980-04-18 | 1981-11-16 | Nec Corp | Read only semiconductor memory |
JPS57104253A (en) * | 1980-12-19 | 1982-06-29 | Matsushita Electric Ind Co Ltd | Semiconductor memory device |
-
1983
- 1983-01-04 JP JP58000102A patent/JPS59124760A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56147472A (en) * | 1980-04-18 | 1981-11-16 | Nec Corp | Read only semiconductor memory |
JPS57104253A (en) * | 1980-12-19 | 1982-06-29 | Matsushita Electric Ind Co Ltd | Semiconductor memory device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62112160U (en) * | 1985-12-28 | 1987-07-17 |
Also Published As
Publication number | Publication date |
---|---|
JPH0345552B2 (en) | 1991-07-11 |
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