JPS59122138A - Digital signal regenerating circuit - Google Patents
Digital signal regenerating circuitInfo
- Publication number
- JPS59122138A JPS59122138A JP22945082A JP22945082A JPS59122138A JP S59122138 A JPS59122138 A JP S59122138A JP 22945082 A JP22945082 A JP 22945082A JP 22945082 A JP22945082 A JP 22945082A JP S59122138 A JPS59122138 A JP S59122138A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- voltage
- capacitor
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
- H04L25/062—Setting decision thresholds using feedforward techniques only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は符号変調を受けたディジタル信号の記録再生又
は通信等、周波数帯域の制限を受けた系を通過したディ
ジタル信号の波形等化に関するもので、特に周波数スペ
クトルが低域周波数帯まで広がったディジタル信号は低
域ノイズの混入が多く、低域周波数帯を制限した系を通
過することにより受ける波形歪を補正できるディジタル
信号再生回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to waveform equalization of digital signals that have passed through a system with a limited frequency band, such as recording/reproducing or communication of code-modulated digital signals. In particular, a digital signal whose frequency spectrum has expanded to a low frequency band is often contaminated with low frequency noise, and the present invention relates to a digital signal reproducing circuit that can correct waveform distortion caused by passing through a system that limits the low frequency band.
従来の構成とその問題点
ディジタル信号は、周知の通り、０と１又は−１と１の
２値を扱う場合がほとんどである。今簡単のため、扱う
信号が２値のＮＲＺ変調のディジタル信号を考えると、
信号の０，１の並び方には無数の組み合わせの可能性が
ある。−例として、その中で特定の３種類の並びを考え
てみると、第１図（ａ） （ｂ） （ｃ）の様なパター
ンが考えられる。第１図で（ａ）のパターンの平均値す
なわち直流分はゼロ、（ｂ）ツバターンの直流分は＋０
．５ 、（ｃ）のパターンの直流分は−０，５となる。Conventional configuration and its problems As is well known, most digital signals handle binary values of 0 and 1 or -1 and 1. For simplicity's sake, let's consider a binary NRZ modulated digital signal.
There are countless possible combinations of how the 0's and 1's of the signal are arranged. - As an example, if we consider three specific types of arrangement, patterns such as those shown in Fig. 1 (a), (b), and (c) can be considered. In Figure 1, the average value of the pattern (a), that is, the DC component is zero, and (b) the DC component of the tube turn is +0.
．． 5, the DC component of the pattern (c) is -0.5.
従って、今これらのパタ−ンが縦続に接続された信号が
ＤＣまで平坦に通過できる系を通ると、第２図の（ａ）
の様に正しく波形が１ｑ現されるが、その直流分は（ａ
）の破線の様に変動するため、低域の帯域が制限された
系を通過した場合には、第２図（ｂ）の様にエンベロー
プの変動がその直流分に対応して生ずる。この時、高域
の周波数帯域が制限されない場合には、信号の立上がり
、立下がりの傾斜は極めて急峻になるため、ゼロクロス
ポイントの位置情報は保持され、ディジタル信号の再生
には誤りを生じない。しかし、実際には高域の帯域も制
限されるため、信号の立ち上がりはゆるやかになり、正
しいゼロクロス位置が第２図（ｃ）の様にシフトしてし
まい、誤りの原因となっていた。Therefore, if a signal in which these patterns are connected in cascade passes through a system that can pass flatly up to DC, it will become as shown in (a) in Figure 2.
The waveform is correctly expressed as 1q, but its DC component is (a
), so when the low frequency band passes through a limited system, the envelope changes as shown in FIG. 2(b), corresponding to the DC component. At this time, if the high frequency band is not limited, the rising and falling slopes of the signal will be extremely steep, so the position information of the zero crossing point will be maintained and no error will occur in the reproduction of the digital signal. However, in reality, since the high frequency band is also limited, the rise of the signal becomes gradual, and the correct zero-crossing position shifts as shown in FIG. 2(c), causing an error.
従来、この様な誤りに対しては、大きく分けて次の２つ
の方法で対処されている。第１の方法は、信号の直流成
分又は低域のスペクトルを極力押えたパターンとなる変
調を行う。第２の方法は信号の包絡線から直流を再生す
るという方法である。Conventionally, such errors have been dealt with roughly in the following two ways. The first method is to perform modulation that creates a pattern in which the DC component or low-frequency spectrum of the signal is suppressed as much as possible. The second method is to regenerate direct current from the signal envelope.
本発明は後者の方法に関するもので、従来は文献（中用
他’ ＮＲＺ記録における積分検出方式の検討電子通信
学会磁気記録研究会ＭＲ７７−４６，１９７８ａ ）に
見られる様に第３図の様な構成をとっていた。The present invention relates to the latter method, and as can be seen in the literature (Chuuyo et al.' Study of Integral Detection Method in NRZ Recording, Institute of Electronics and Communication Engineers Magnetic Recording Study Group MR77-46, 1978a), there has been a method as shown in Fig. 3. It was structured.
第３図で（１） （２）はダイオード、（３） （４）
はコンデンサ、（５） （６）は抵抗、（７）は加算器
、（８）は減算器である。この構成の中で、ダイオード
（１）とコンデンサ（３）と抵抗（５）で構成される部
分は、入力の負電圧側の包絡線検波を行うもので、第３
図中の点Ａ、Ｂ、Ｃ。In Figure 3, (1) (2) are diodes, (3) (4)
is a capacitor, (5) and (6) are resistors, (7) is an adder, and (8) is a subtracter. In this configuration, the part consisting of the diode (1), capacitor (3), and resistor (5) performs envelope detection on the negative voltage side of the input;
Points A, B, and C in the diagram.
Ｄの各点の出力波形は第４図（ａ）の曲線ｐ、ｑ、ｒ。The output waveforms at each point of D are curves p, q, and r in FIG. 4(a).
Ｓの様に、又第３図Ｅ点の出方波形は第４図（ｂ）の様
になり、直流成分は再生される。しかしこの方法では、
Ｓ／／Ｎが２倍以下と言う様な低Ｓ／ｆＶ下では第５図
（ａ）の様に包絡線がゼロレベルを割ってしまい、正確
な包絡線検波ができながった。すなわち、第３図中の点
Ａ、Ｂ、Ｃ，Ｄの出力波形は第５図（ａ）の曲線Ｔ”
＋ ｑ’ ＋ ｒ′＋ Ｓ’となり、第３図Ｅ点の出方
波形は第５図（ｂ）の様になって点Ｘ、Ｙ、で誤りを生
じていた。S, and the output waveform at point E in FIG. 3 becomes as shown in FIG. 4(b), and the DC component is regenerated. But with this method,
Under low S/fV where the S//N is less than 2 times, the envelope exceeds the zero level as shown in FIG. 5(a), making accurate envelope detection impossible. That is, the output waveforms at points A, B, C, and D in FIG. 3 are the curve T'' in FIG. 5(a).
+ q' + r'+ S', and the output waveform at point E in FIG. 3 became as shown in FIG. 5(b), with errors occurring at points X and Y.
このように、信号検出の誤りを生ずる原因は、低域周波
数制限により信号のエンベロープが変動するのに加えて
、低域雑音が加算され、エンベロープの変動がゼロｌノ
ベルを割ってしまい、包藉線検波が動作しなくなるため
である。In this way, the cause of signal detection errors is that in addition to the fluctuation of the signal envelope due to the low-frequency limit, low-frequency noise is added, and the fluctuation of the envelope is less than zero, causing the envelope to change. This is because line detection will no longer work.
発明の目的
本発明は従来のかかる欠点に鑑みてなされたもので、そ
の目的とするところは、包絡線検波の方法を改良するこ
とにより、低域の周波数帯域が制限され、直流が通過で
きない系を通じてディジタル信号を伝送する場合、系の
低域雑音が著しく多く、その振幅が信号より大きくても
、十分にこの雑音を抑圧し、正しい信号を得ることので
きるディジタル信号再生回路を提供することにある。OBJECT OF THE INVENTION The present invention has been made in view of the above drawbacks of the conventional technology.The purpose of the present invention is to improve the method of envelope detection to improve systems in which the low frequency band is restricted and direct current cannot pass through. To provide a digital signal reproducing circuit that can sufficiently suppress this noise and obtain a correct signal even if the low-frequency noise in the system is significantly large and the amplitude is larger than the signal when transmitting a digital signal through a digital signal. be.
発明の構成
上記目的を達成するために、本発明は、入力信号に正の
直流電圧を加算する手段と、入力信号に負の直流電圧を
加算する手段と、上記正及び負の直流電圧を加算する手
段の出方をそれぞれ整流する手段と、この整流する手段
の出方を充電するための容量と、この容量の正負の電荷
をそれぞれゆるやかに放電する手段と、上記正の直流電
圧を加算する手段の出力を整流し容量に充電された電圧
として得られる第１の信号と負の直流電圧を加算する手
段の出力を整流し容量に充電された電圧として得られる
第２の信号を加算する手段と、この第１と第２の信号を
加算する手段の出力を減衰する手段と、この減衰する手
段の出方を前記入力信号から減算する手段とを具備した
構成にしたものであり、信号の正の包絡線の検波には正
の直流電圧を重畳し、負の包絡線の検波には負の直流電
圧を重畳したものを検波することにより、包絡線検波の
動作領域を広げることを可能としている。Structure of the Invention In order to achieve the above object, the present invention provides a means for adding a positive DC voltage to an input signal, a means for adding a negative DC voltage to the input signal, and a means for adding the positive and negative DC voltages. A means for rectifying the output of the means for rectifying, a capacitor for charging the output of the means for rectifying, a means for slowly discharging the positive and negative charges of this capacitor, and adding the above positive DC voltage. means for rectifying the output of the means and adding a first signal obtained as a voltage charged in the capacitor and a second signal obtained as a voltage charged in the capacitor rectifying the output of the means for adding a negative DC voltage; , means for attenuating the output of the means for adding the first and second signals, and means for subtracting the output of the attenuating means from the input signal. By superimposing a positive DC voltage to detect a positive envelope, and by superimposing a negative DC voltage to detect a negative envelope, it is possible to expand the operating range of envelope detection. There is.
実施例の説明
以下、本発明の実施例を図面に基づいて説明する。＠７
図は本発明の一具体実施例を示す。第７図で、◇１は入
力端子、Ｑｌ）（６）は加算器、（１３ｏ→は直流電圧
源で、電圧はそれぞれ＋Ｅ、−Ｅである。（Ｊ。DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described based on the drawings. @7
The figure shows one specific embodiment of the invention. In Fig. 7, ◇1 is an input terminal, Ql) (6) is an adder, (13o→ is a DC voltage source, and the voltages are +E and -E, respectively. (J.
ｑＱは整流器、α７）（至）は充電用コンデンサ、θす
（イ）は放電用抵抗、■υは加算器、（２）は１／２減
衰器、に）は減算器、（ハ）は出力端子である。今、第
５図（ａ）の様にエンベロープ変動を含むディジタル信
号が入力端子（Ｉｒｌ＋に入力されると、加算器０υ（
６）の出力はそれぞれ第６図（ａ）の曲線ｗ 、 （ｂ
）の曲線ｊの様になる。すなわち、入力信号がそれぞれ
十Ｅ、−Ｅだけレベルシフトする。レベルシフトした（
ｎ号はそれぞれ整流器００ｕＱを通してコンデンサ（１
７） ａｅに充電される。qQ is a rectifier, α7) (to) is a charging capacitor, θsu (a) is a discharging resistor, ■υ is an adder, (2) is a 1/2 attenuator, ni) is a subtractor, and (c) is a It is an output terminal. Now, when a digital signal including envelope fluctuations is input to the input terminal (Irl+) as shown in Fig. 5(a), the adder 0υ(
The outputs of 6) are the curves w and (b) in Fig. 6(a), respectively.
) will look like the curve j. That is, the input signals are level-shifted by 10E and -E, respectively. level shifted (
No. n is connected to a capacitor (1
7) Charged to ae.
ＩＫ 流Ｎ４θ！０１（９はコンデンサα″７１０８）
の電荷が加算器αＵ′４へ逆流するのを防止している。IK style N4θ! 01 (9 is capacitor α″7108)
This prevents the charge from flowing back to the adder αU'4.
ここでの放電抵抗（Ｉｎ Ｋ）を適当に選ぶことにより
、略第６図（ａ）の曲線ｕ 、 （ｂ）の曲線Ｕ′の様
に信号の正及び負の包絡線が得られる。従って、これら
の正及び負の包絡線出力は、入力信号の正負の包絡線を
ｆ （ｔ） 、 ｇ （ｔ）とすると、それぞれｆ（ｔ
）＋Ｅ、ｇの−Ｅで表わされる。By appropriately selecting the discharge resistance (InK), positive and negative envelopes of the signal can be obtained approximately as shown by the curve u in FIG. 6(a) and the curve U' in FIG. 6(b). Therefore, these positive and negative envelope outputs are f(t), respectively, where f (t) and g (t) are the positive and negative envelopes of the input signal.
)+E, expressed as -E of g.
正負の包絡線信号は加算器０１）で加算され、ｆ （ｔ
） ＋ｇ（［）が得られる。さらに、その加算出力は減
衰器（イ）で１７′２に減衰され、（ｆ （ｔ） 十ｇ
（ｔ）ン／２となって入力信号の平均値すなわち直流
成分が第８図（ａ）の曲線Ｘの様に再生される。この直
流成分は減算器（／Ｉで入力信号から減算され、はぼエ
ンベロープ変動のない信号が出力端子（ハ）に第８図（
ｂ）の様に得られる。The positive and negative envelope signals are added by an adder 01), and f (t
) +g([) is obtained. Furthermore, the added output is attenuated to 17'2 by the attenuator (A), and (f (t) 10 g
(t)/2, and the average value of the input signal, that is, the DC component, is reproduced as shown by curve X in FIG. 8(a). This DC component is subtracted from the input signal by a subtracter (/I), and a signal with no envelope fluctuation is sent to the output terminal (c) as shown in Figure 8 (c).
It is obtained as in b).
発明の効果
以上、本発明によれば、低域の帯域が制限され、低域ノ
イズ成分が信号振幅以上のレベルの場合にも、十分原信
号の再生が可能となる。又、本発明は構成が極めて簡単
であり、低コストで実現できるため工業的に得る利益は
極めて大である。As described above, according to the present invention, even when the low frequency band is limited and the low frequency noise component has a level higher than the signal amplitude, it is possible to sufficiently reproduce the original signal. Further, the present invention has an extremely simple structure and can be realized at low cost, so that the industrial benefits are extremely large.
第１図はディジタル信号に直流成分が生ずることの説明
図、第２図は低域の帯域が制限された系を通過した場合
にゼロクロス位置に誤りの生ずることの説明図、第３図
は従来の回路構成図、第４図は直流成分再生回路の効果
の説明図、第５図は従来方式の欠点の説明図、第６図は
本発明の要旨説明図、第７図は本発明の回路構成図、第
８図は本発明の詳細な説明図である。
αυ（６）・・・加算器、θ側α→・・直流電圧源、ａ
ａａ＊・・・整流器、α７）０１１９・・・充電用コン
デンサ、０１（イ）・・放電用抵抗。
■υ・・・加算器、に）・・・１／２減衰器、（財）・
・・減算器代理人 森本義弘
第１図
第２図
第３図
第４図Figure 1 is an illustration of the generation of a DC component in a digital signal, Figure 2 is an illustration of the occurrence of an error in the zero cross position when the low frequency band passes through a limited system, and Figure 3 is an illustration of the conventional 4 is an explanatory diagram of the effect of the DC component regeneration circuit, FIG. 5 is an explanatory diagram of the drawbacks of the conventional method, FIG. 6 is an explanatory diagram of the gist of the present invention, and FIG. 7 is a diagram of the circuit of the present invention. The configuration diagram and FIG. 8 are detailed explanatory diagrams of the present invention. αυ(6)...Adder, θ side α→...DC voltage source, a
aa*... Rectifier, α7) 0119... Charging capacitor, 01(a)... Discharging resistor. ■υ...adder, ni)...1/2 attenuator, (goods)・
...Subtractor agent Yoshihiro Morimoto Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
号に負の直流電圧を加算する手段と、上記正及び負の直
流電圧を加算する手段の出力をそれぞれ整流する手段と
、この整流する手段の出力を充電するための容量と、こ
の容量の正負の電荷をそれぞれゆるやかに放電する手段
と、上記正の直流電圧を加算する手段の出力を整流し容
量に充電された電圧として得られる第１の信号および負
の直流電圧を加算する手段の出力を整流し容量に充電さ
れた電圧として得られる第２の信号を加算する手段と、
この第１と第２の信号を加算する手段の出力を減衰する
手段と、この減衰する手段の出力を前記入力信号から減
算する手段とを具備したディジタル（ｉ５’Ｆ’ニー再
生回路。1. Means for adding a positive DC voltage to an input signal, means for adding a negative DC voltage to an input signal, means for rectifying the outputs of the means for adding positive and negative DC voltages, and the rectification. A capacitor for charging the output of the means for charging, a means for slowly discharging the positive and negative charges of this capacitor, and a means for adding the positive DC voltage are rectified to obtain the voltage charged in the capacitor. means for rectifying the output of the means for adding the first signal and the negative DC voltage and adding a second signal obtained as a voltage charged in the capacitor;
A digital (i5'F' knee reproducing circuit) comprising means for attenuating the output of the means for adding the first and second signals, and means for subtracting the output of the attenuating means from the input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22945082A JPS59122138A (en) | 1982-12-28 | 1982-12-28 | Digital signal regenerating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22945082A JPS59122138A (en) | 1982-12-28 | 1982-12-28 | Digital signal regenerating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59122138A true JPS59122138A (en) | 1984-07-14 |
Family
ID=16892392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22945082A Pending JPS59122138A (en) | 1982-12-28 | 1982-12-28 | Digital signal regenerating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59122138A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61218251A (en) * | 1985-03-25 | 1986-09-27 | Fujitsu Ltd | Reception sensitivity control system |
| JPH01256849A (en) * | 1988-04-06 | 1989-10-13 | Nec Corp | Identification reproducing circuit |
| EP1202511A1 (en) * | 2000-10-30 | 2002-05-02 | Texas Instruments France | Method for estimating and removing a time-varying DC-offset |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55150645A (en) * | 1979-05-14 | 1980-11-22 | Sony Corp | Data sampling circuit |
-
1982
- 1982-12-28 JP JP22945082A patent/JPS59122138A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55150645A (en) * | 1979-05-14 | 1980-11-22 | Sony Corp | Data sampling circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61218251A (en) * | 1985-03-25 | 1986-09-27 | Fujitsu Ltd | Reception sensitivity control system |
| JPH01256849A (en) * | 1988-04-06 | 1989-10-13 | Nec Corp | Identification reproducing circuit |
| EP1202511A1 (en) * | 2000-10-30 | 2002-05-02 | Texas Instruments France | Method for estimating and removing a time-varying DC-offset |
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