JPS59115650U - logic array integrated circuit - Google Patents
logic array integrated circuitInfo
- Publication number
- JPS59115650U JPS59115650U JP884483U JP884483U JPS59115650U JP S59115650 U JPS59115650 U JP S59115650U JP 884483 U JP884483 U JP 884483U JP 884483 U JP884483 U JP 884483U JP S59115650 U JPS59115650 U JP S59115650U
- Authority
- JP
- Japan
- Prior art keywords
- line group
- logic array
- integrated circuit
- array integrated
- intersection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
３ 第１図は従来の論理アレイ集積回路の１例を示
ｒ す回路図、第２図及び第４図は本考案の論理アレ
１１ イ集積回路のブロック図、第３図及び第５図は
本−考案の論理アレイ集積回路の回路図である。
Ｊ 図において、１・・・ＡＮＤアレイ、２・・・
ＯＲアレイ、・ Ｘ工〜ｘ、・・・入力線、ｐ１〜ｐ
、・・・積項線、ｙ□〜ｙ、・・・出） 力線、Ａ、
Ｂ・・・斜辺、をそれぞれ表わす。
＠Ｚｌ
第４ ｌ3. FIG. 1 is a circuit diagram showing an example of a conventional logic array integrated circuit, FIGS. 2 and 4 are block diagrams of the logic array 11 integrated circuit of the present invention, and FIGS. 1 is a circuit diagram of a logic array integrated circuit of the present invention; FIG. J In the diagram, 1...AND array, 2...
OR array, X engineering ~ x, ... input line, p1 ~ p
,...Product term line, y□~y,...out) Line of force, A,
B...represents the hypotenuse, respectively. @Zl 4th l
Claims (1)
素子を配した第１の論理アレイと、前原積項線群と出力
線群との交点の所定の位置にプログラム素子を配した第
２の論理アレイとから成り前記入力線群に加えられた入
力信号群の関数を１成して前記出力線群に出力する論理
アレイ集積巨路において、第１の論理アレイと第２の論
理アレイの形状を三角形もしくは台形にし、から互いＣ
斜辺を対向して配置したことを特徴とする論理アレイ集
積回路。A first logic array in which a program element is arranged at a predetermined position of the intersection of the input line group and the product term line group, and a program element is arranged at a predetermined position of the intersection of the previous product term line group and the output line group. and a second logic array, which forms a function of a group of input signals applied to the input line group and outputs the resulting signal to the output line group. Make the array shape triangular or trapezoidal, and then
A logic array integrated circuit characterized in that hypotenuses are arranged facing each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP884483U JPS59115650U (en) | 1983-01-25 | 1983-01-25 | logic array integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP884483U JPS59115650U (en) | 1983-01-25 | 1983-01-25 | logic array integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59115650U true JPS59115650U (en) | 1984-08-04 |
Family
ID=30140326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP884483U Pending JPS59115650U (en) | 1983-01-25 | 1983-01-25 | logic array integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59115650U (en) |
-
1983
- 1983-01-25 JP JP884483U patent/JPS59115650U/en active Pending
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