JPS59113621A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59113621A JPS59113621A JP22567482A JP22567482A JPS59113621A JP S59113621 A JPS59113621 A JP S59113621A JP 22567482 A JP22567482 A JP 22567482A JP 22567482 A JP22567482 A JP 22567482A JP S59113621 A JPS59113621 A JP S59113621A
- Authority
- JP
- Japan
- Prior art keywords
- silicon oxide
- oxide film
- electrode
- type
- films
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 230000001681 protective effect Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 240000000530 Alcea rosea Species 0.000 claims 1
- 235000017334 Alcea rosea Nutrition 0.000 claims 1
- 235000017303 Althaea rosea Nutrition 0.000 claims 1
- 235000021395 porridge Nutrition 0.000 claims 1
- 238000002161 passivation Methods 0.000 abstract description 11
- 238000009792 diffusion process Methods 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- 241001474791 Proboscis Species 0.000 description 2
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 235000013399 edible fruits Nutrition 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000750631 Takifugu chinensis Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置のｄ遣方法に関し、特に絶縁膜の段
垂都での゛電極の段切れ防正に関するものである。従来
より素子のパッシベイションとしてリン−シリゲートグ
ラス（ｆ’ＳＧ） ｉｇがよく１史われている。Ｐｅ（
ｊｄはナトリクム（Ｎａ＋） 等のイオン不純物のゲッ
ター幼果及びグロック幼果がありかつ比較的容易に形成
することが出来ることから、広くパッシベイション１漠
として１吏用されている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for discharging a semiconductor device, and more particularly to preventing breakage of an electrode at a stepped portion of an insulating film. Phosphorus siligate glass (f'SG) has been well known as a passivation material for devices. Pe(
JD is widely used as a passivation agent because it has getter seedlings and glock seedlings containing ionic impurities such as sodium chloride (Na+) and can be formed relatively easily.
・以−ド第１図（ａ）〜ｔｅ）を１更って従来のＰ−チ
イネル接合形屯芥幼呆トランジスタ（以ドＪ −Ｆ ｌ
ｔｉ Ｔと称す）にパッシベイションｌ臭としてＰａ（
）、１ｇを使った場合について説明する。・Changing Figures 1(a) to te), a conventional P-channel junction type infant transistor (hereinafter referred to as J-F l
Pa (referred to as ti T) as a passivation odor.
), the case where 1g is used will be explained.
まず第１図（ａ）に示すようにＦ部ゲートとなるｎ形の
半導体基板（υ上にＰ形のエピタキシャル成長）ｔｔｉ
（２）を形成する。仄に第１図（ｂ）に示す如くｎ形
の分離頭載（３）を形成した淡ソース及びドレイン電極
のオーミック性を艮くする目的でＰ形の篩不純吻一度領
域（４）及び（５）を不純吻拡敢法により形ｊ戊する。First, as shown in FIG. 1(a), an n-type semiconductor substrate (P-type epitaxially grown on υ) which becomes the gate of the F section (tti)
(2) is formed. As shown in FIG. 1(b), in order to improve the ohmic properties of the thin source and drain electrodes formed with the n-type separated head (3), the P-type sieve impurity region (4) and ( 5) is shaped by the impure proboscis expansion method.
ここで（１４）はＰ形の烏不純・＋１２７一度碩域＜４
） （５）と形成する１余に１吏用されまたシリコン酸
化膜による拡故マスクである。矢に第１図（Ｃ）に示す
如くｎ形の上部ゲート頭載（６）を不純物拡敢去により
杉Ｉ祝する。続いて前記拡敢マスク用のシリコン峻化ノ
漠（１４）上及び残ったＰ形のエピタキシャルｒｍ Ｌ
２）の表面上を熱酸化し盾なシリコン酸化膜（１４）を
形成し、このシリコン酸化膜の表面全面にパッシベイシ
ョン用のりｔ教を行ないＰＳＧｉ漠（１５）を形１戊し
た麦ビューアなシリコン酸１ヒ模（１６）をＣＶＤで破
着する。ここでｉ Ｓ Ｇ ａ （１５）はイオン性不
純物その曲のゲッター効果及びグロック幼果と共に吸湿
性があるがＰＢＧ膜を素子表開に残して分くと素子の耐
湿性が悪くなる為リンを含まない純粋なシリコン酸化Ｆ
Ａ ”’ＣＰＳＧＪ漠上を被ったＰ Ｓ Ｇ’、ｄのサ
ンドインチ構造になっている。次に第１図（ｄ）に示す
ダロくソース電極及びドレイン電極形成用窓（７）及び
（８）をＰ形の高不純勿一度領域（４） （５）上に開
ける。次に粥１図（θ）に示す如くソース電極（９）及
びドレイン電極（１ｏ）及び半導体基板（１）側にゲー
ト電極（１１）を破着して目的とするＰ−チャネルＪ
−Ｂ” Ｂ Ｔをイ”４るこトカ出来る。Here, (14) is P-type Karasu impurity +127 once subterranean <4
) (5) A diffusion mask made of a silicon oxide film is used for the remainder of the process. As shown in FIG. 1(C), the n-type upper gate head (6) is removed by spreading and removing impurities. Subsequently, the remaining P-type epitaxial rm L is formed on the silicon thickening layer (14) for the expansion mask.
2) The surface of 2) is thermally oxidized to form a shielding silicon oxide film (14), and a passivation paste is applied to the entire surface of this silicon oxide film to create a PSGI viewer (15). A silicone acid pattern (16) is broken by CVD. Here, i S Ga (15) has hygroscopicity along with ionic impurities and the getter effect of the song, but if the PBG film is left on the surface of the element, the moisture resistance of the element will deteriorate, so phosphorus is removed. Pure silicon oxide free
It has a sandwich structure of PSG', d which covers a large area of CPSGJ.Next, as shown in FIG. ) is opened on the P-type high impurity non-uniformity region (4) (5). Next, as shown in Figure 1 (θ), the source electrode (9), the drain electrode (1o) and the semiconductor substrate (1) side are opened. The target P-channel J by tearing the gate electrode (11)
-B" B T can be changed to I"4.
かかる製造方法により作られた素子においてはソース及
びドレイン電極形成用ｅ （７） Ｌ８）をあける場合
にＰＢＧ）漠はピ１−アなシリコン酸化膜に比べて故１
０陪エツチング速度が速い為に第２図（ａ）に示すよう
Ｋ Ｐ Ｓ Ｇ ｊ摸が１黄方向に深くエツチングされ
ビューアなシリコン酸化！漠のひさしく１８）が形成さ
れる。この上に成極（９）が形成されると段差部分で４
極が切断されることがあったり初期の段階では接続され
ていたとしても第２図（ｂ）に示す如くひさしく１８）
が熱ひずみあるいけモールド時のひずみによってめくれ
上り電極（９）を切断し、電極の段切れが発生する。In devices manufactured by such a manufacturing method, when opening the source and drain electrode formation e (7) L8), the PBG) is more difficult to form than a silicon oxide film which is a 1-a layer.
Because the etching speed is fast, the K P S G j pattern is etched deeply in the yellow direction as shown in Figure 2 (a), resulting in silicon oxidation! 18) is formed. When polarization (9) is formed on top of this, 4
The poles may be disconnected, or even if they are connected at the initial stage, they may be severely damaged as shown in Figure 2(b)18)
The electrode (9) is turned up due to thermal strain or strain during molding, and the electrode (9) is cut, causing a break in the electrode.
電極がひさし部分をオーバーランプしていない場合は四
′ａないが、ひさしをオーバラップするオーバーレイ横
這の半導体素子や集積回路素子の場合はひさし部分の段
差で電極の段切れが発生するためＰＳＧサンドインチ構
造のパッシベイションはこのままでは１吏えないという
欠点があった。If the electrodes do not overlap the eaves, there is no 4'a, but in the case of semiconductor devices or integrated circuit devices with sideways overlays that overlap the eaves, electrode breaks occur due to the steps in the eaves, so PSG is used. The sand inch structure passivation had the disadvantage that it could not be used as it was.
不発明はかかる欠点に鑑みてなされたもので、第１のシ
リコン酸化膜を選択的に商去し、半導体基板の表面の一
部を４出させ、＄１のシリコン酸化膜の表面に不純＃Ｊ
をトングし昧護換を形成するようにし、電極形成時の段
切れを防止した半導体装置の製造方法を提供するもので
ある。The invention was made in view of these drawbacks, and by selectively removing the first silicon oxide film and exposing a part of the surface of the semiconductor substrate, impurities were added to the surface of the $1 silicon oxide film. J
The present invention provides a method for manufacturing a semiconductor device in which step breakage during electrode formation is prevented by forming a protective layer by tongs.
以下本発明の一実施例になるＰ−チャンネルＪ−ｋ’
ｆｉ Ｔについて躬３図（ａ）〜（ｅ）により詳細に説
明する。P-channel Jk', which is an embodiment of the present invention, will be described below.
FiT will be explained in detail with reference to Figures 3 (a) to (e).
’ｌ’ｆｆＪａ図（ａ）に示す如くド部ゲートとなるｎ
形の半導体基板（１）上にＰ形のエビクキシャル成長層
（２）を形成する。矢に−Ｊに３図（ｂ）に示す如（ｎ
形分ｌａ領域（３）を形成した後ソースドレイン成極の
オーミック性を良くする目的でＰ形高不純物ａ度頭載（
４）及び（５）を形成する。なお、この１系シリコン酸
化１摸（１４）が拡散用マスクとして使用されるが、こ
のシリコン酸化膜（１４）はこのまま残される。次に第
３図（Ｃ）に示す妬く新にシリコン酸化膜（１４）によ
る拡散用マスクを形ｊ祝し、このマスクを開用してｎ形
の上部ゲート領域（６）及びＰ形高不純吻一度領域（４
）（５）内にｎ影領域（１２）を形成し同時にＰ影領域
（４）あるいけ（５）とｎ形頭載（１２）同にＰＮ接合
（１３）を形成する。この時上部ゲート領域（６）とｎ
影領域（１２）を同時に形成出来ない場合はまずゲート
領域（６）を形１戊した後ゲート領域（６）上にシリコ
ン酸化ノ漢を被着し、ｎ影領域（１２）形成用の窓開け
を行っても艮い。'l'ffJa As shown in figure (a), n becomes the do part gate.
A P-type evixaxial growth layer (2) is formed on a P-type semiconductor substrate (1). As shown in Figure 3 (b) on the arrow -J (n
After forming the la region (3), a P-type high impurity impurity (a degree) was added (
4) and (5) are formed. Note that this 1-silicon oxide film (14) is used as a diffusion mask, but this silicon oxide film (14) is left as is. Next, a new diffusion mask made of a silicon oxide film (14) as shown in FIG. Proboscis region (4
) (5), and at the same time form a PN junction (13) in the P shadow region (4) and the n-shape head (12). At this time, the upper gate region (6) and n
If it is not possible to form the shadow region (12) at the same time, first cut out the gate region (6) and then deposit silicon oxide on the gate region (6) to form the window for forming the n shadow region (12). Even if you open it, it will not work.
また、ｎ形頭載（１２）形成の形成と同時にシリコンｅ
化ｔｂ （１４）にパッシベイション用のリン拡散を
行いこの表面にＰＢＧ膜（１５）を形成する。七の後第
３図（ｄ）に示すように素子の主面全面にシリコン酸化
膜（１６）をＣＶｉ）で形成する。この時ｎ影領域（１
２）上にはＰＢＧ模は形成されないでビューアなシリコ
ン酸化１漠（１６）のみが形成される０次に第３図（θ
）に示す如くソース電極及びドレイン電極取り出し口（
７）、（８）をこの′鴫４＆取り出し口がＰＢＧ膜（１
５）に達しないようにそれぞれＰ影領域（４） （５）
及びｎ影領域（１２）の１部に開けた後ソース電極（９
）、ドレイン磁極（１０）及びゲート電極（１１）を破
着して目的とするＰ−チャネルシーｆｌ′ＥＴを得るこ
とが出来る。Also, at the same time as the formation of the n-type head (12), silicon e
Phosphorus diffusion for passivation is performed on the chemical tb (14), and a PBG film (15) is formed on this surface. After that, as shown in FIG. 3(d), a silicon oxide film (16) is formed using CVi over the entire main surface of the device. At this time, n shadow areas (1
2) No PBG pattern is formed on the top, and only a silicon oxide layer (16) is formed on the 0th order in Figure 3 (θ
) as shown in the source and drain electrode outlet (
7).
P shadow area (4) (5) respectively so as not to reach 5)
and a source electrode (9) after opening in a part of the n shadow area (12).
), the drain magnetic pole (10) and the gate electrode (11) can be broken to obtain the desired P-channel sea fl'ET.
なお第４図に不発明の一実施例のパターン図を示す
かかる製造方法によれば電極取り出し窓（７） （８）
の形成に１祭しその１都、すなわちｎ影領域（１２）の
表面にｆ’ｓＧ膜の端部は終端し、かつこの部分はシリ
コン酸化ｊ漠（１６）によって遣われ露出していないた
め、ｎ影領域上ではシリコン酸化膜にひさしは杉；祝さ
れず、この部分での電極の段切れは防止される。一方ｎ
形領域（１２）はＰ形頭載（４） （５）より浅く形成
されているので、Ｐ影領域（４） （５）内に浮いた状
態になっており、ソース電極（９）及びドレイン電極（
１０）が被着されても素子の特性には影響がない。In addition, according to this manufacturing method, which shows a pattern diagram of an embodiment of the invention in FIG. 4, electrode extraction windows (7) (8)
The edge of the f'sG film terminates on the surface of the n-shaded region (12), and this part is covered with silicon oxide (16) and is not exposed. , the silicon oxide film on the n-shaded area is not shaded, and the electrode is prevented from breaking in this area. On the other hand n
Since the shaped region (12) is formed shallower than the P-shaped head (4) (5), it is floating within the P-shaped region (4) (5), and the source electrode (9) and drain electrode(
10) does not affect the characteristics of the device.
又パッシベイション膜は上部ゲート領域（６）上、Ｐ形
エピタキシャル層（２）上及びゲート接合（１７）上を
破っておればパッシベイション効果は十分でありＰ形高
不純物ｄ度領域（４） （５）及びｎ影領域（１２）上
の一部を被ってなくても素子の特性には間ら影響がない
。In addition, if the passivation film breaks on the upper gate region (6), the P-type epitaxial layer (2), and the gate junction (17), the passivation effect is sufficient, and the P-type high impurity degree region ( 4) Even if a part of (5) and the n-shaded area (12) are not covered, the characteristics of the element are not affected at all.
上述の如く本発明の一実施例によるＰ−チャネルＪ −
Ｆ’ Ｗ Ｔ Ｋ ｐいてはゲッター幼果及びパッシベ
イション効果があり、かつ容易に形１戊出米るＰＳＬ）
ｊｄをパッシベイション膜として１吏用しても電極の絶
縁ｊ漠の段差部分での段切れの発生原因となる、絶＃膜
のひさしが形成されない構造となってｐす、４１雑な工
程を追加する必要もなく、歩ｄ艮く、低画格の素子を得
ることが出来る。As described above, a P-channel J- according to an embodiment of the present invention
F' W T K p has a getter young fruit and a passivation effect, and it is easy to form a type 1 rice (PSL)
Even if JD is used as a passivation film, the structure is such that no eaves of the insulating film are formed, which causes breakage at the stepped portions of the electrode insulation. It is possible to obtain a high-quality, low-definition element without the need to add .
上記実施例ではＰ−チャネルＪ −ｋ’ ｔ Ｔに適用
した場合について説明したが、極性を加えたｎチャイ・
ルＪ−Ｆ［Ｔあるいけバイポーラトランジスタに、ｄ用
できる。In the above embodiment, the case where it is applied to P-channel J-k' t T was explained, but it is also possible to apply
It can be used for d in bipolar transistors.
また、ｋ’Ｂ、ＩＩＪ漠（１５） ’ｋ例えばボロンシ
リケートガラス模（ｊ３ｓＧ漠）に代えた場合も同様の
幼果を発１車する。In addition, when k'B, IIJ (15) 'k, for example, is replaced with a boron silicate glass model (j3sG), similar young fruits are produced.
本発明によれば第１のシリコン酸化膜を選択的に除去し
、半尋体基板の表面の一部を露出させ、第１のシリコン
酸化ｊ漠の表面に不綿物をドーグし保護ノ漠を形１戊し
、この保護を端上に第２のシリコン酸化膜を形成し、こ
の後、保護１漠ｒ尿去することなく手導体基板の表面〜
を４出し、この露出表面に極
電柱を形成するようにしたので、電極形成時の電極の設
切れが防止できるという憂れた幼果をゼする。According to the present invention, the first silicon oxide film is selectively removed to expose a part of the surface of the semicircular substrate, and the surface of the first silicon oxide film is coated with an impurity to form a protective film. A second silicon oxide film is formed on the edge of the protective layer, and then the surface of the conductor substrate is removed without removing the protective layer.
4, and a pole pole is formed on this exposed surface, which prevents the electrode from breaking when forming the electrode, which is a problem.
第１図（ａ）〜（ｅ）は従来のＰ−チャネ／ｌ／ Ｊ
−Ｆ Ｊｉｉ Ｔの製造方法を示す工程別断面図、第２
図ｔａ） （ｂ）は産米のＪ −Ｆ凡Ｔ（ＤＩ！！３縁
膜段差部分に形成された酸化シリコン模のひさしを示す
断面図、第３図（ａ）〜（’３）は本発明の一実施例の
Ｐ−チャネルＪ−Ｆ）ＬＴの一実施例の製造方法を示す
断面図、第４図は本発明の一実施により作られたＰ−チ
ャネルＪ −Ｈ’［Ｔを示すパターン図である。
図において（１） ｔＪｉｎ形半醇体基板、（２）ｒｉ
Ｐ形エピタキシギル成長層、（４）はＰ形部不純物−ノ
（ソース領域、（５）はＰ形高不純物ドレイン頭載、（
６）は上部ゲート領域、（９）／″ｉソース電、Ｉ徴、
（１０）はドレイン電極、（１１）はゲート電極、（１
２）はｎ影領域、（１４）はシリコンｒ浚化１戻、（１
５）ばＰ８ Ｇ ｒｇ、（１８）ハシリコン酸化膜のひ
さしである
なお図中同一符号は同一もしくけ（目当部分を示す
代理人葛野 信−
第１図
フ
第２図
第３図゛
第３図
第４図Figures 1(a) to (e) show the conventional P-channel/l/J
-F Jii T manufacturing method sectional view by process, 2nd
Figure ta) (b) is a cross-sectional view showing the eaves of the silicon oxide model formed on the step part of the rim of J-F BON T (DI!!3) of produced rice, and Figures 3 (a) to ('3) are FIG. 4 is a sectional view showing a method of manufacturing an embodiment of P-channel J-F)LT according to an embodiment of the present invention, and FIG. FIG. In the figure, (1) tJin type semi-solid substrate, (2) ri
P-type epitaxial growth layer, (4) is P-type impurity layer (source region), (5) is P-type high impurity drain head, (
6) is the upper gate region, (9)/″i source voltage, I character,
(10) is the drain electrode, (11) is the gate electrode, (1
2) is n shadow region, (14) is silicon r dredging 1 return, (1
5) P8 G rg, (18) is a silicon oxide film eaves.The same reference numerals in the figures are the same (Shin Kuzuno, the agent who indicates the target part). Figure 4
Claims (1)
１の工程と、ｎａ記−１ｔｒＪ１のシリコン酸化１臭を
選択的に除去し、前記表面の一部を露出させる第２の工
程と、１ＪＩＪ６己ｆＪ１のシリコン酸化！ｊ葵の表面
に不純物をドープレ保、ｉＬ漠を形成する第３の工程と
、前記保護膜上にｆＪ２のシリコン酸化ｊ漢を形成する
第４の工程と、前記第２の工程で選択的に露出された表
面の一部を前記保護膜を除去することなく再び露出する
第５の工程と、前記第５の工程で形１戊された曲記嬉出
された基板表向に電蝋を形成する第６の工程とを含む半
導体装置の製造方法。The first step is to form a silicon oxide film of porridge 1 on the surface of the 4 halves and the 4 plates, and the second step is to selectively remove the silicon oxide 1 odor of na-1trJ1 and expose a part of the surface. Process and silicon oxidation of 1JIJ6selffJ1! A third step of doping impurities on the surface of the hollyhock to form an iL layer, a fourth step of forming a silicon oxide layer of fJ2 on the protective film, and a selective step of doping in the second step. a fifth step of exposing a part of the exposed surface again without removing the protective film; and forming electrolytic wax on the surface of the substrate that has been carved into a shape in the fifth step. a sixth step of manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22567482A JPS59113621A (en) | 1982-12-20 | 1982-12-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22567482A JPS59113621A (en) | 1982-12-20 | 1982-12-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59113621A true JPS59113621A (en) | 1984-06-30 |
Family
ID=16832997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22567482A Pending JPS59113621A (en) | 1982-12-20 | 1982-12-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59113621A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0585688U (en) * | 1992-04-23 | 1993-11-19 | 株式会社学習研究社 | Pencil holder |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52131484A (en) * | 1976-04-28 | 1977-11-04 | Hitachi Ltd | Semiconductor device |
| JPS5543630A (en) * | 1978-09-22 | 1980-03-27 | Toshiba Corp | Graphic code input system |
-
1982
- 1982-12-20 JP JP22567482A patent/JPS59113621A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52131484A (en) * | 1976-04-28 | 1977-11-04 | Hitachi Ltd | Semiconductor device |
| JPS5543630A (en) * | 1978-09-22 | 1980-03-27 | Toshiba Corp | Graphic code input system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0585688U (en) * | 1992-04-23 | 1993-11-19 | 株式会社学習研究社 | Pencil holder |
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