JPH02208974A - Solid-state image sensing device - Google Patents
Solid-state image sensing deviceInfo
- Publication number
- JPH02208974A JPH02208974A JP1028614A JP2861489A JPH02208974A JP H02208974 A JPH02208974 A JP H02208974A JP 1028614 A JP1028614 A JP 1028614A JP 2861489 A JP2861489 A JP 2861489A JP H02208974 A JPH02208974 A JP H02208974A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- signal current
- charge storage
- electrode
- solid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 16
- 230000035945 sensitivity Effects 0.000 claims abstract description 5
- 230000003321 amplification Effects 0.000 claims abstract description 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 3
- 238000003384 imaging method Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000000694 effects Effects 0.000 claims description 5
- 239000011669 selenium Substances 0.000 claims description 5
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000284 extract Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 229910052711 selenium Inorganic materials 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 abstract description 34
- 229920006395 saturated elastomer Polymers 0.000 abstract description 14
- 230000005684 electric field Effects 0.000 abstract description 13
- 230000007423 decrease Effects 0.000 abstract description 7
- 210000003127 knee Anatomy 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 22
- 238000009792 diffusion process Methods 0.000 description 17
- 230000008878 coupling Effects 0.000 description 15
- 238000010168 coupling process Methods 0.000 description 15
- 238000005859 coupling reaction Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 230000001629 suppression Effects 0.000 description 4
- 206010047571 Visual impairment Diseases 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000036211 photosensitivity Effects 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052979 sodium sulfide Inorganic materials 0.000 description 1
- GRVFOGOEDUUMBP-UHFFFAOYSA-N sodium sulfide (anhydrous) Chemical compound [Na+].[Na+].[S-2] GRVFOGOEDUUMBP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、光導電膜を用いた撮像装置、更に詳しく言え
ば、被写体の像に対応する光情報を光導電膜によって電
荷信号に変換し、上記電荷信号を半導体スイッチを介し
て電気信号として読み出す撮像装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an imaging device using a photoconductive film, and more specifically, to an imaging device that uses a photoconductive film to convert optical information corresponding to an image of a subject into a charge signal. , relates to an imaging device that reads out the charge signal as an electrical signal via a semiconductor switch.
（従来の技術〕
テレビジョンカメラ等に使用される固体撮像装置として
、重要な点の一つはより小型に、かつ信号処理が簡単に
実現できることである。(Prior Art) One of the important aspects of a solid-state imaging device used in a television camera or the like is that it can be made smaller and signal processing can be easily realized.
これらの要求を満たすものとして、光電変換部に光導電
膜を利用した固体撮像装置が知られている。この種の固
体撮像装置は、半導体基板上に、画素の光情報を電気信
号に変換し、所定の時間に外部に出力する固体撮像素子
を複数個マトリクス状に配列した構成であり、上記固体
撮像素子は。Solid-state imaging devices that use a photoconductive film in a photoelectric conversion section are known as devices that meet these requirements. This type of solid-state imaging device has a structure in which a plurality of solid-state imaging devices are arranged in a matrix on a semiconductor substrate, and convert pixel optical information into electrical signals and output them to the outside at predetermined times. Motoko is.
光導電膜で発生した電荷を蓄積する電荷蓄積素子と、上
記電荷を所定の時間に選択し出力信号として取り出す半
導体スイッチを構成要素としている。The components include a charge storage element that stores charges generated in a photoconductive film, and a semiconductor switch that selects the charges at a predetermined time and outputs them as an output signal.
例えば、ＦＥＴトランジスタのソース（又はドレイン）
を電荷蓄積素子とし、ソース電極と光導電膜の一方の面
に画素毎に区切られて設けられた画素電極とを結合し、
光導膜の他方の面には、透光性の透明電極が形成され、
ターゲット電圧が加えられ、光導電膜に一定の電界を加
え所定の光電特性を持つように構成され、ＦＥＴトラン
ジスタのゲートに素子選択の電圧が加えられることによ
って、上記電荷蓄積素子の電荷をドレイン（又はソース
）に読み出す構成となっている。なおこの種の固体撮像
装置に関連する文献として、テレビジョン学会技報Ｖｏ
Ｑ、９ Ｎａ２Ｓ、 ＥＤ９３６ （１９８６）用尻
ほか、がある。For example, the source (or drain) of a FET transistor
is used as a charge storage element, and a source electrode and a pixel electrode provided on one side of the photoconductive film are separated for each pixel, and
A light-transmitting transparent electrode is formed on the other surface of the light guide film.
A target voltage is applied to the photoconductive film to apply a constant electric field to the photoconductive film so that it has predetermined photoelectric properties, and an element selection voltage is applied to the gate of the FET transistor to drain the charge of the charge storage element ( or source). In addition, as a document related to this type of solid-state imaging device, there is a technical report of the Society of Television Engineers Vol.
Q, 9 Na2S, ED936 (1986), etc. are available.
上記従来知られている撮像素子では照度と出力電流の関
係が、照度が一定の照度（飽和面照度）以上では一定に
なる。すなわちダイナミックレンジが小さく、高輝度と
低輝度の被写体が共存する場合に双方の複写体を正しく
再生する４とが困難であるという問題があった。In the conventionally known image sensor described above, the relationship between illuminance and output current becomes constant when the illuminance is equal to or higher than a certain illuminance (saturated surface illuminance). That is, there is a problem in that the dynamic range is small, and when high-brightness and low-brightness objects coexist, it is difficult to correctly reproduce both copies.
本発明の主な目的は撮像素子の飽和面照度を大きくし、
広いダイナミックレンジの固体撮像装置を実現すること
である。The main purpose of the present invention is to increase the saturated surface illuminance of the image sensor,
The objective is to realize a solid-state imaging device with a wide dynamic range.
上記目的を達成するため、第１の本発明は、光導電膜の
一面に透光性電極を他面に画素に対応する複数の画素電
極を設け、上記透光性電極と画素電極間にターゲット電
圧を印加する光電変換部と、上記光電変換部で発生した
電荷を蓄積する電荷蓄積部と、上記電荷蓄積部から所定
の時間に電荷を取り出す信号読み出し部を持つ撮像装置
において、上記画素電極と電荷蓄積部との間に抵抗体を
設け、上記ターゲット電圧を上記光導電膜の光感度が増
幅作用を持つ領域に設定し、面照度と信号電流の関係が
少なくとも飽和信号電流の近傍において二イー特性を持
つように構成した。In order to achieve the above object, the first invention provides a light-transmitting electrode on one surface of a photoconductive film and a plurality of pixel electrodes corresponding to pixels on the other surface, and a target is provided between the light-transmitting electrode and the pixel electrode. In an imaging device having a photoelectric conversion section that applies a voltage, a charge storage section that accumulates charges generated in the photoelectric conversion section, and a signal readout section that extracts charges from the charge storage section at a predetermined time, the pixel electrode and A resistor is provided between the charge storage section and the target voltage is set in a region where the photosensitivity of the photoconductive film has an amplifying effect, so that the relationship between surface illuminance and signal current is at least 2E in the vicinity of the saturated signal current. Constructed to have characteristics.
特に好ましい形態として、上記光導電膜として非晶質セ
レン膜（ａ−８ｓと略称する）。又上記電荷蓄積部及び
信号読み出し部は同一半導体基板上に形成されたＦＥＴ
トランジスタ等の固体素子で実現される。As a particularly preferred form, the photoconductive film is an amorphous selenium film (abbreviated as a-8s). Further, the charge storage section and the signal readout section are FETs formed on the same semiconductor substrate.
It is realized using solid-state devices such as transistors.
また、上記目的を達成するため、第２の本発明では、上
記第１の発明と共に、又は単独に、上記電荷蓄積部の一
部をＳｉｎ、、Ｓｉ、Ｎ、、５ｉｎ２／Ｓｉ、Ｎ９．複
合膜、Ｔａ、Ｏ，等の絶縁膜を構成要素とする容量素子
（ＭＯ８容量）で構成する。In addition, in order to achieve the above object, in the second invention, a part of the charge storage section is made of Sin, Si, N, 5in2/Si, N9. It is composed of a capacitive element (MO8 capacitor) whose constituent elements are a composite film, an insulating film such as Ta, O, etc.
本発明は、上記撮像素子のみでなく、テレビジョンカメ
ラ等の撮像装置を構成する場合のように、上記撮像素子
を画素に応じて複数個配列し、上記複数個の撮像素子の
信号を走査して読み出す走査部を含む撮像装置も当然含
まれる。In addition to the above-mentioned image sensor, the present invention also provides a method for arranging a plurality of the above-mentioned image sensors according to pixels and scanning the signals of the plurality of image sensors, as in the case of configuring an image sensor such as a television camera. Naturally, an imaging device including a scanning section for reading data is also included.
画素電極と蓄積容量間に設けられた高抵抗体は、所定の
信号対雑音比が得られる所定の信号電流値以上において
信号電流による抵抗体での電圧降下により画素電極と透
光性電極の間にかかる電圧が低減し光導電膜の光感度が
低下するように動作する。これによって、素子の光電変
換特性はニイー特性すなわち、飽和信号電流となる近傍
において、面照度変化に対する信号電流変化が少なくな
り、飽和信号電流となる最小面照度は大きくなる特性を
持つことになり、飽和信号電流が同一でも飽和面照度を
大きくすることができるので、撮像装置のダイナミック
レンジを拡大することができる。A high-resistance element provided between the pixel electrode and the storage capacitor is used to reduce the voltage between the pixel electrode and the transparent electrode due to the voltage drop across the resistor caused by the signal current when the signal current exceeds a predetermined signal current value that provides a predetermined signal-to-noise ratio. It operates so that the voltage applied to the photoconductive film is reduced and the photosensitivity of the photoconductive film is reduced. As a result, the photoelectric conversion characteristics of the device have a Nieee characteristic, that is, near the saturation signal current, the change in signal current with respect to changes in surface illuminance decreases, and the minimum surface illuminance at which the saturation signal current occurs increases. Since the saturated surface illuminance can be increased even if the saturated signal current is the same, the dynamic range of the imaging device can be expanded.
また、電荷蓄積部を構成するＳｉＯ□もしくはＳｉＯ，
／Ｓｉ３Ｎ４等の絶縁膜を構成要素とする容量素子は、
従来素子で蓄積容量を形成したｐｎ接合に比し、単位面
積当たり５倍程度の容量値拡大を実現できる。これによ
って、撮像装置の飽和信号電流を増加でき、従ってダイ
ナミックレンジを拡大することができる。In addition, SiO□ or SiO constituting the charge storage section,
A capacitive element whose constituent element is an insulating film such as /Si3N4,
Compared to a pn junction in which a storage capacitor is formed using a conventional element, the capacitance value can be increased by about five times per unit area. As a result, the saturation signal current of the imaging device can be increased, and the dynamic range can therefore be expanded.
以下、本発明の実施例について詳細に説明する。 Examples of the present invention will be described in detail below.
第１図は、本発明による撮像装置の一実施例の要部であ
る固体撮像素子の構成を示す側断面図である。なお、説
明の簡明のため以下の各図面の説明において、同様の構
成・作用を持つ部分には同一の番号を付し、説明を省く
。FIG. 1 is a side sectional view showing the configuration of a solid-state image sensor, which is a main part of an embodiment of an image sensor according to the present invention. In order to simplify the explanation, in the explanation of each drawing below, the same numbers are given to the parts having the same configuration and operation, and the explanation will be omitted.
図において、１はＩＴＯ等の透光性電極、２は非晶質セ
レン（以下ａ−８ｅと称する）、３はＡＱ。In the figure, 1 is a transparent electrode such as ITO, 2 is amorphous selenium (hereinafter referred to as a-8e), and 3 is AQ.
Ｍｏ、Ｃｒ或いはＴａ等の導電体よりなる画素電極、４
はポリイミドもしくはリンガラス等の絶縁体よりなる平
坦化層、５は例えばポリシリコンよりなる抵抗体、６−
１は電荷蓄積容量をなすＰ型拡散層、７−１はポリシリ
コンもしくはシリサイドよりなるスイッチ電極、８−１
はＡＱよりなる信号線配線、９はリンガラス等よりなる
層間絶縁膜、１０は素子分離領域を形成するＬＯＧＯ８
酸化膜、１１はｎ型基板、１３はゲート酸化膜である。Pixel electrode made of a conductor such as Mo, Cr or Ta, 4
5 is a flattening layer made of an insulator such as polyimide or phosphor glass, 5 is a resistor made of polysilicon, and 6-
1 is a P-type diffusion layer forming a charge storage capacity, 7-1 is a switch electrode made of polysilicon or silicide, 8-1
9 is a signal line wiring made of AQ, 9 is an interlayer insulating film made of phosphorus glass, etc., and 10 is LOGO 8 forming an element isolation region.
An oxide film, 11 is an n-type substrate, and 13 is a gate oxide film.
透光性電極１には直流電ｇ１２からターゲット電圧Ｖ、
がかけられる。A target voltage V is applied to the transparent electrode 1 from the DC current g12.
is applied.
第２図は、上記ａ−８ｓで構成された光導電膜２の膜に
かかる電界Ｖ／Ｌ（Ｖ：膜にかかる電圧、Ｌ：膜厚）と
信号電流密度Ｉ／Ｓ（Ｉ：信号電流、Ｓ：膜の面積）の
関係を示す図で、電界領域Ａは従来使用されている光電
変換のなされる電界領域で電界の大きさに拘らず感度が
ほぼ一定の領域、領域Ｂは感度が領域Ａより大きく、電
界の大きさに応じて感度が増大するアバランシュ増倍す
なわち電流増幅作用の生じる電界領域である。第１図に
示したターゲット電圧Ｖ、はａ −Ｓｅ２にかかる透光
性電極１と画素電極３の間の電圧がａ−Ｓｅがアバラン
シュ増倍を起こす電圧となる領域に設定される０例えば
、ａ−８ｅ膜厚が２μｍの時に、１０倍のアバランシュ
増倍を起こすには約２４０ｖのターゲット電圧をかける
。Figure 2 shows the electric field V/L (V: voltage applied to the film, L: film thickness) applied to the photoconductive film 2 composed of the above a-8s and the signal current density I/S (I: signal current , S: area of the film), where electric field area A is the electric field area where photoelectric conversion is conventionally used, and the sensitivity is almost constant regardless of the electric field size, and area B is the area where the sensitivity is constant. This is an electric field region which is larger than region A and where avalanche multiplication, that is, current amplification effect occurs, where the sensitivity increases according to the magnitude of the electric field. The target voltage V shown in FIG. 1 is set in a region where the voltage between the transparent electrode 1 and the pixel electrode 3 applied to a-Se2 is a voltage at which a-Se causes avalanche multiplication. For example, When the a-8e film thickness is 2 μm, a target voltage of about 240 V is applied to cause 10 times avalanche multiplication.
以下、第１図の実施例の動作を説明する。The operation of the embodiment shown in FIG. 1 will be explained below.
光導電膜ａ−８ｅ２に光が当たると抵抗体５に信号電流
が流れ、蓄積容量６−１の電圧がビデオバイアスＶｖよ
り高くなる。この時、抵抗体５に流れる電流による電圧
降下により、透光性電極１と画素電極３にかかる電圧が
減少し、光導電膜２にかかる電界が減少し、信号電流密
度が減少する。When light hits the photoconductive film a-8e2, a signal current flows through the resistor 5, and the voltage of the storage capacitor 6-1 becomes higher than the video bias Vv. At this time, due to a voltage drop due to the current flowing through the resistor 5, the voltage applied to the transparent electrode 1 and the pixel electrode 3 decreases, the electric field applied to the photoconductive film 2 decreases, and the signal current density decreases.
しかし、電界が領域Ａとなった場合は、照度が一定であ
るかぎりは信号電流密度は変化しない。However, when the electric field is in region A, the signal current density does not change as long as the illuminance remains constant.
第３図は上記実施例による面照度と信号電流の関係すな
わち光電変換特性を示す図である。同図において、飽和
信号電流は第１図に示したＰ型拡散層６−１の容量値Ｃ
ｐｏにＰ型拡散層６−１がｎ型基板１１に対し頭方向と
なる電圧ｖｔよりＰ型拡散層６−１のビデオバイアスＶ
Ｖを引いた電圧をかけた飽和信号電荷量に水平走査のク
ロック周波数をかけたものである。FIG. 3 is a diagram showing the relationship between surface illuminance and signal current, ie, photoelectric conversion characteristics, according to the above embodiment. In the same figure, the saturation signal current is the capacitance value C of the P-type diffusion layer 6-1 shown in FIG.
The video bias V of the P-type diffusion layer 6-1 is determined from the voltage VT at which the P-type diffusion layer 6-1 is oriented in the head direction with respect to the n-type substrate 11 at po.
This is the saturation signal charge amount multiplied by the voltage subtracted by V, multiplied by the horizontal scanning clock frequency.
第１図の実施例の光電変換特性は、第３図の実線に示す
様にニイー特性を示すことになり、飽和信号電流が同一
でも飽和面照度を大きくすることができ、ダイナミック
レンジを実質的に拡大できる。この際、低照度において
も高い信号対雑音比を得るために、上記電圧降下による
信号電流密度の低下が、充分な信号対雑音比を得るのに
必要な信号電流値、すなわち、所定の信号電流値以上で
生じる様に抵抗体５の抵抗値を設定する。例えば、上記
実施例でこの所定信号電流を２００ｎ Ａとすると、１
０００ ｘ ２０００画素数の素子では、高抵抗体５の
抵抗値を５Ｘ１０”Ωとすればよい。The photoelectric conversion characteristics of the embodiment shown in FIG. 1 exhibit knee characteristics as shown by the solid line in FIG. It can be expanded to At this time, in order to obtain a high signal-to-noise ratio even under low illuminance, the reduction in signal current density due to the voltage drop described above is the signal current value necessary to obtain a sufficient signal-to-noise ratio, that is, the predetermined signal current. The resistance value of the resistor 5 is set so that the resistance value is greater than or equal to the value. For example, if this predetermined signal current is 200 nA in the above embodiment, 1
In an element having 000 x 2000 pixels, the resistance value of the high resistance element 5 may be set to 5 x 10''Ω.
なお、本実施例では、高抵抗体５を縦に形成したが、そ
の空間配置は画素電極３と蓄積容量を形成するＰ型拡散
層６−１間にすればどのようにしてもよい、また、本実
施例では高抵抗体らをポリシリコンで形成したが、所望
の抵抗値を得られるならば、ポリシリコン以外の導電性
で形成してもよい、また、本実施例では、光導電膜とし
てａ−８ｅ膜の場合を述べたが信号電流密度が光導電膜
にかかる電界に依存性を持つならば、ａ−８ｉ等のよう
なものでも適用できる。In this embodiment, the high-resistance element 5 is formed vertically, but its spatial arrangement may be in any manner as long as it is placed between the pixel electrode 3 and the P-type diffusion layer 6-1 forming the storage capacitor. In this example, the high-resistance elements were formed of polysilicon, but they may be formed of a conductive material other than polysilicon as long as the desired resistance value can be obtained. Although the case of the a-8e film has been described, if the signal current density has dependence on the electric field applied to the photoconductive film, films such as a-8i can also be applied.
ところで、上記第１の発明の撮像素子を用いてカラー撮
像装置を構成する場合、異なるカラーフィルタを配置さ
れた画素ごとに飽和面照度が異なり、高照度時の色バラ
ンスに不都合が生じるときは上記抵抗体５の抵抗値を信
号電流の大きいフィルタを有する画素については大きく
することにより、飽和面照度を各画素間でバランスがと
れるようにすれば良い。By the way, when configuring a color imaging device using the image sensor of the first aspect of the invention, the saturated surface illuminance differs for each pixel in which a different color filter is arranged, and if a problem arises in color balance at high illuminance, the above-mentioned method may be used. By increasing the resistance value of the resistor 5 for pixels having a filter with a large signal current, the saturated surface illuminance may be balanced among each pixel.
第４図は第１の本発明による固体撮像装置の要部である
撮像素子の他の実施例の構造を示す断面部の構成図で、
第１図に示した実施例では、蓄積容量６−１の電圧が、
基板１１に対し接合が順方向になる電圧になると、過剰
な信号電荷が基板１１を介し垂直信号線８−１に流れ込
み、ブルーミングという！！象が生じるという問題が生
じるので、本実施例では、蓄積容量６−１の電圧を所定
の電圧Ｖｃにクランプするためのトランジスタを付加す
ることにより、ブルーミング現象を防止したものである
。FIG. 4 is a cross-sectional configuration diagram showing the structure of another embodiment of the image sensor which is the main part of the solid-state image sensor according to the first invention.
In the embodiment shown in FIG. 1, the voltage of the storage capacitor 6-1 is
When the voltage becomes such that the junction goes in the forward direction with respect to the substrate 11, excessive signal charges flow into the vertical signal line 8-1 through the substrate 11, which is called blooming! ! In this embodiment, a transistor for clamping the voltage of the storage capacitor 6-1 to a predetermined voltage Vc is added to prevent the blooming phenomenon.
第４図において、７−２はクランプトランジスタのゲー
ト電極、６−３はクランプトランジスタのドレインとな
るｐ型拡散層、８−２はドレイン配線層である。クラン
プトランジスタは、蓄積容量６−１の電圧がクランプト
ランジスタのゲート電極電圧ｖｃ１よりクランプトラン
ジスタのしきい電圧Ｖ ｔ ｈを引いたＶｃなる電圧に
なるとクランプトランジスタが導通し過剰信号電荷は、
拡散層６−３、配線層８−２を介し、素子外部に掃き出
される。この結果、蓄積容量６−１の電圧は上記スイッ
チトランジスタ以下の電圧にクランプされ、過剰電荷が
信号線に漏れこむことを防止することができる。従って
、ブルーミングの発生を抑圧できる。In FIG. 4, 7-2 is a gate electrode of a clamp transistor, 6-3 is a p-type diffusion layer which becomes a drain of the clamp transistor, and 8-2 is a drain wiring layer. In the clamp transistor, when the voltage of the storage capacitor 6-1 reaches a voltage Vc obtained by subtracting the threshold voltage V th of the clamp transistor from the gate electrode voltage vc1 of the clamp transistor, the clamp transistor becomes conductive and the excess signal charge is
It is swept out to the outside of the element via the diffusion layer 6-3 and the wiring layer 8-2. As a result, the voltage of the storage capacitor 6-1 is clamped to a voltage lower than the switch transistor, and it is possible to prevent excess charge from leaking into the signal line. Therefore, the occurrence of blooming can be suppressed.
本実施例においては、蓄積容量のクランプ電圧Ｖｃは、
ばらつきの小さいクランプトランジスタのしきい電圧Ｖ
ｔｈで決定されるので、縦型オーバフロードレインを用
いた場合に比し、飽和信号電流のばらつきを抑圧するこ
とが可能になる。さらに、微細加工が進むにつれ、クラ
ンプトランジスタの面積を容易に縮小できるため、高集
積化にも適している。また１本実施例では、高抵抗体５
の抵抗値をクランプトランジスタのオン抵抗より大きく
することにより、高照度時に光導電体の抵抗値が小さく
なった時にも透明電極にかかる高電圧を分圧し、拡散層
６−１には接合耐圧以下の小さな電圧しか発生せず、接
合の破壊を防ぐことができるという利点も有している。In this embodiment, the clamp voltage Vc of the storage capacitor is
Threshold voltage V of clamp transistor with small variation
Since it is determined by th, it is possible to suppress variations in the saturation signal current compared to the case where a vertical overflow drain is used. Furthermore, as microfabrication progresses, the area of the clamp transistor can be easily reduced, making it suitable for higher integration. In addition, in one embodiment, the high resistance element 5
By making the resistance value larger than the on-resistance of the clamp transistor, the high voltage applied to the transparent electrode can be divided even when the resistance value of the photoconductor is small during high illuminance, and the diffusion layer 6-1 has a voltage lower than the junction breakdown voltage. It also has the advantage of generating only a small voltage, which prevents breakdown of the junction.
第５図は第２の本発明による固体撮像装置の実施例の断
面構造を示す図である。Ｐ型拡散層６−１とポリシリコ
ン等よりなる電極１５間には５ｉｎ２゜ｓｉ、Ｎ、、Ｓ
ｔＯ，／５ｉａＮ４複合膜、ＴａａＯ，等よりなる絶縁
膜１６を絶縁体とするＭＯ８容量が形成されている。光
電変換の結果１発生した信号電荷は、拡散層６−１と基
板１１間の接合容量と拡散層６−１と電極１５間のＭＯ
８容量よりなる蓄積容量に蓄積される。FIG. 5 is a diagram showing a cross-sectional structure of an embodiment of the solid-state imaging device according to the second invention. Between the P-type diffusion layer 6-1 and the electrode 15 made of polysilicon or the like, there are
An MO8 capacitor is formed using an insulating film 16 made of tO, /5iaN4 composite film, TaaO, etc. as an insulator. The signal charges generated as a result of photoelectric conversion are the junction capacitance between the diffusion layer 6-1 and the substrate 11 and the MO between the diffusion layer 6-1 and the electrode 15.
The data is stored in a storage capacity consisting of 8 capacities.
本実施例においては、例えばＭＯ８容量絶縁膜１６を２
５０人の５ｉｎ２で形成すると２ Ｘ １０” ｃｓ−
”の濃度を持つｎ型基板に形成されたｐｔ拡散層にビデ
オバイアス３ｖがかかった時のＰｎ接合に比し、約５倍
の単位面積当たりの容量値を得ることができる。この結
果、従来のＰｎ接合により蓄積容量を形成していた場合
に比べ、約５倍程度の飽和信号電流を実現できる。In this embodiment, for example, the MO8 capacitor insulating film 16 is
When formed with 50 people 5in2, 2 X 10” cs-
It is possible to obtain a capacitance value per unit area that is about five times that of a Pn junction when a video bias of 3V is applied to a PT diffusion layer formed on an n-type substrate with a concentration of Compared to the case where the storage capacitor is formed by a Pn junction, it is possible to realize a saturation signal current about five times as large.
また、第１図の実施例で述べた様に第２の本発明をカラ
ー素子に適用する際、色ごとの飽和面照度のバランスを
取るためにＭＯ８容量の値を信号電流の大きいカラーフ
ィルタを有する画素については大きくすればよい。In addition, as described in the embodiment shown in FIG. 1, when applying the second invention to a color element, in order to balance the saturated surface illuminance for each color, the value of the MO8 capacitance is adjusted by using a color filter with a large signal current. It is only necessary to increase the size of pixels that have the same size.
第６図は第１、第２の本発明を同時に実施した固体撮像
装置の実施例の要部である固体撮像素子の断面構造を示
す図である。１７はポリシリコンよりなる高抵抗層で、
５１０２ｙ ＳｉＯ□／Ｓｉ３Ｎ４等よりなるＭ縁膜１
６を絶縁膜としｎ型基板１１との間に高い単位面積当た
りの容量値を持つＭＯ８容量を形成している。動作は、
第１図で説明したと同様なので省略する０本実施例では
、光電変換に二イー特性を持たせ、かつ、飽和信号電流
を増加させることができ、広いダイナミックレンジを持
っ撮像装置を実現できる。FIG. 6 is a diagram showing a cross-sectional structure of a solid-state imaging device which is a main part of an embodiment of a solid-state imaging device in which the first and second aspects of the present invention are implemented simultaneously. 17 is a high resistance layer made of polysilicon;
5102y M edge film 1 made of SiO□/Si3N4 etc.
An MO8 capacitor having a high capacitance value per unit area is formed between the insulating film 6 and the n-type substrate 11. The operation is
Since it is the same as that explained in FIG. 1, the description thereof will be omitted. In this embodiment, it is possible to give two-E characteristics to photoelectric conversion and increase the saturation signal current, thereby realizing an imaging device having a wide dynamic range.
第７図は、第１．第２の本発明を同時に実施し、かつ、
第４図の実施例で述べたクランプトランジスタを付加し
た実施例の断面構成図である。ＭＯ８容量は、クランプ
トランジスタゲート電極７−２と高抵抗層１７の間に形
成される。動作は第１図と同様である。本実施例では、
第６図と同様に広いダイナミックレンジを持つとともに
、ブルーミングを抑圧した素子を実現できる。Figure 7 shows the 1. Simultaneously implementing the second invention, and
FIG. 5 is a cross-sectional configuration diagram of an embodiment in which the clamp transistor described in the embodiment of FIG. 4 is added. The MO8 capacitor is formed between the clamp transistor gate electrode 7-2 and the high resistance layer 17. The operation is similar to that in FIG. In this example,
As in FIG. 6, it is possible to realize an element that has a wide dynamic range and suppresses blooming.
第８図は第２の本発明の他の実施例を示す撮像素子の断
面構造図である０本実施例においては、ＭＯ８容量を基
板内に形成した溝の側壁に形成することにより、面積の
増大なく大きな蓄積容量を作り、高い飽和信号電流を実
現できる。FIG. 8 is a cross-sectional structural diagram of an image pickup device showing another embodiment of the second invention. A large storage capacity can be created without increasing, and a high saturation signal current can be achieved.
さて、上記固体撮像素子を複数個画素に対応して配置し
て撮像装置を構成する場合、走査部の構成としては、従
来、ＴＶ学会技報ｖｏＱ、９ Ｎ＋１４５Ｅ Ｄ９３６
（１９８６）に論じられているＭＯ８型素子と、′８
８年ＴＶ学会全国大会予稿集３５頁から３６頁に述べら
れているＣＣＤ型素子の２つが知られており、本発明の
固体撮像装置に使用できる。ＭＯ８型素子を走査基板と
した場合、ＣＣＤ型素子を走査基板にした場合に比し、
走査基板の読み出し可能な電荷量が大きく、飽和信号電
流を大きく取れ、かつ、各画素のスイッチトランジスタ
を非飽和動作できるので残像が少ないという二つの利点
を有している。ところが、上記文献にも述べられている
様に、垂直信号線と画素電極との容量結合によりスメア
が発生する、走査途中で生じる雑音が、大きいという欠
点がある。この様なＭＯ８型走査基板の欠点を解消し、
低雑音、低スメア、低残像かつ高飽和信号電流を実現す
るために１本願出願人が先に特願昭６１−２５８６２．
特願昭６０−２９２９００ 、特願昭６２−１２８１２
３で出願した垂直信号線ごとに、増幅器とダブルサンプ
リング回路を設け、スメア差動を行うＭＯ８型素子を走
査基板とじて用いた実施例を第９図、第１Ｏ図を用い説
明する。Now, when configuring an imaging device by arranging a plurality of the above-mentioned solid-state image sensors corresponding to pixels, the configuration of the scanning section is conventionally described in TV Society Technical Report voQ, 9 N+145E D936.
(1986) and '8
Two CCD type elements described in the Proceedings of the 1980 TV Society National Conference, pages 35 to 36, are known and can be used in the solid-state imaging device of the present invention. When using an MO8 type element as a scanning substrate, compared to when using a CCD type element as a scanning substrate,
It has two advantages: the amount of charge that can be read out from the scanning substrate is large, a large saturation signal current can be obtained, and the switch transistor of each pixel can be operated in a non-saturated manner, so there is little afterimage. However, as described in the above-mentioned literature, there are drawbacks in that smear occurs due to capacitive coupling between the vertical signal line and the pixel electrode, and noise generated during scanning is large. Eliminating these drawbacks of the MO8 type scanning board,
In order to realize low noise, low smear, low afterimage, and high saturation signal current, the applicant of this application previously filed Japanese Patent Application No. 61-25862.
Patent application 1986-292900, patent application 1987-12812
An embodiment in which an amplifier and a double sampling circuit are provided for each vertical signal line and an MO8 type element that performs smear differential is used as a scanning substrate will be described with reference to FIG. 9 and FIG. 1O.
第９図は本発明による固体撮像装置の一実施例を示す回
路構成図であり、簡単のために画素子を３×４のアレイ
で示す、第１０図は第９図の撮像装置の駆動パルスの波
形図である。図中、８１は光導電膜を積層した一画素子
すなわち撮像素子を示し、例えば、第１図、第５図、第
６図、第８図のいずれかの断面構造を持つ。８２は垂直
走査回路、８３は各画素０ゲート電極につながる垂直ゲ
ート線、８５は垂直信号線、８６は増幅器８７を高利得
領域に設定するための自己バイアススイッチ、８８は垂
直信号線に転送された信号電荷の電圧への変換係数を決
定する帰還容量、８９は第１のカップリングコンデンサ
、９０は第１のクランプスイッチ、９１はソースフォロ
ワ−１９２は第２のカップリングコンデンサ、９３は第
２のクランプスイッチ、９４．９５はメモリ容量９７．
９８への信号読み込みのための読み込みスイッチ、９６
は水平走査回路８４により開閉する水平スイッチ、９９
は水平信号線１０２をリセットするためのリセットスイ
ッチ、１００はブルーミング抑圧回路ゲート、１０１は
ブルーミング抑圧回路ドレインである。また、第１Ｏ図
においてＳ１〜Ｓ５．ＢＯＢＤは第９図の対応する端子
にかかる電圧波形図である。また、ＨＢＬは水平ブラン
キング期間を示す。FIG. 9 is a circuit configuration diagram showing an embodiment of the solid-state imaging device according to the present invention, in which pixel elements are shown as a 3×4 array for simplicity. FIG. 10 shows the driving pulses of the imaging device of FIG. FIG. In the figure, numeral 81 indicates one pixel element, that is, an image pickup element, in which photoconductive films are laminated, and has, for example, a cross-sectional structure as shown in any one of FIG. 1, FIG. 5, FIG. 6, and FIG. 8. 82 is a vertical scanning circuit, 83 is a vertical gate line connected to the 0 gate electrode of each pixel, 85 is a vertical signal line, 86 is a self-bias switch for setting the amplifier 87 to a high gain region, and 88 is a signal transferred to the vertical signal line. 89 is a first coupling capacitor; 90 is a first clamp switch; 91 is a source follower; 192 is a second coupling capacitor; 93 is a second coupling capacitor; The clamp switch of 94.95 is the memory capacity of 97.
Read switch for reading signals to 98, 96
99 is a horizontal switch opened and closed by the horizontal scanning circuit 84;
1 is a reset switch for resetting the horizontal signal line 102, 100 is a blooming suppression circuit gate, and 101 is a blooming suppression circuit drain. Moreover, in FIG. 1O, S1 to S5. BOBD is a voltage waveform diagram applied to the corresponding terminal in FIG. Further, HBL indicates a horizontal blanking period.
以下、本実施例の動作を説明する。The operation of this embodiment will be explained below.
水平ブランキング期間に入ると、まず、全画素の蓄積容
量が飽和前の状態となる。すなわち、ブルーミング抑圧
回路ゲート１００が開き、ブルーミング抑圧（ＢＤ）電
圧がわずかに低くなり（画素のスイッチゲートがＰチャ
ネルトランジスタの場合）全蓄積容量電圧は基板に対し
逆バイアスの電圧となる（第１Ｏ図ｔｉ）。つぎに、Ｂ
Ｄ雷電圧もとの高い電圧となり、蓄積容量電圧が基板に
対し順方向になるまでブルーミングの発生が抑圧される
（第１０図ｔ２）、この後、まず、スメアが第２のカッ
プリングコンデンサ９２に保持される。すなわち、信号
ＳＬ、Ｓ２，８３の電圧が高くなり、スイッチ８６、９
０．９３が開く。このとき、垂直信号線８５の先に各画
素から掃きだされたブルーミング電荷は増幅器８７の電
源線に掃き出されるとともに、増幅器８７が高利得領域
に自己バイアスされる。また、ソースフォロワ−９１入
力端は適当なバイアスＶｖ、にリセットされる。更に、
第２カツプリングコンデンサ９２の出力端子は各メモリ
容量９７．９８のリセット電位と等しいＶｖ、にバイア
スされる（第１０図ｔ、）、つぎに、スイッチ８６が閉
じ、増幅器８７が活性化される。この時、ＫＴＣ雑音に
より垂直信号線８５の電位は■ゎたけゆらぐが、スイッ
チ９０が開いているためにソースフォロワ−９１以降に
はこの雑音は伝わらない（第１０図ｔ、）。この後、ス
イッチ９０が閉じ、この時刻以降の垂直信号線８５の電
圧変動が増幅器８７、第１のカップリングコンデンサ８
９、ソースフォロワ−９１を介して、第２のカップリン
グコンデンサ９２の入力端に伝達される（第１０図ｔｓ
）。この後、時間Ｔｓ、が経過した後、スイッチ９３が
閉じ、Ｔｓ、の間に垂直信号線８５に発生したスメアが
第２のカップリングコンデンサ９２の両端の電位差とし
て保持される（第１０図ｔ６）、この後、ｎ行の信号が
第１のメモリ容量９７に読み込まれる。When the horizontal blanking period begins, first, the storage capacitance of all pixels becomes a state before saturation. That is, the blooming suppression circuit gate 100 opens, the blooming suppression (BD) voltage becomes slightly lower (if the switch gate of the pixel is a P-channel transistor), and the total storage capacitance voltage becomes a reverse bias voltage with respect to the substrate (first O Figure ti). Next, B
The occurrence of blooming is suppressed until the D lightning voltage returns to the original high voltage and the storage capacitance voltage becomes forward with respect to the substrate (t2 in FIG. 10). is maintained. That is, the voltages of the signals SL, S2, 83 become high, and the switches 86, 9
0.93 opens. At this time, the blooming charges swept out from each pixel beyond the vertical signal line 85 are swept out to the power supply line of the amplifier 87, and the amplifier 87 is self-biased to a high gain region. Further, the input terminal of the source follower 91 is reset to an appropriate bias Vv. Furthermore,
The output terminal of the second coupling capacitor 92 is biased to Vv, which is equal to the reset potential of each memory capacitor 97.98 (FIG. 10, t), then the switch 86 is closed and the amplifier 87 is activated. . At this time, the potential of the vertical signal line 85 fluctuates by an amount due to the KTC noise, but since the switch 90 is open, this noise is not transmitted to the source follower 91 and beyond (FIG. 10, t). After this, the switch 90 is closed, and the voltage fluctuation of the vertical signal line 85 after this time is transmitted to the amplifier 87 and the first coupling capacitor 8.
9. Transmitted to the input terminal of the second coupling capacitor 92 via the source follower 91 (Fig. 10 ts
). Thereafter, after a time Ts has elapsed, the switch 93 is closed, and the smear generated on the vertical signal line 85 during Ts is held as a potential difference across the second coupling capacitor 92 (t6 in Fig. 10). ), after which n rows of signals are read into the first memory capacity 97.
すなわち、前述と同様に、スイッチ８６．９０が開き、
垂直信号線８５およびソースフォロワ−９１入力端がリ
セットされる（第１Ｏ図ｔｉ）。その後、スイッチ８６
、９０が順に閉じた後、垂直走査回路８２により選択さ
れた１行垂直ゲート線８３の電位が高くなり、各画素の
蓄積容量６−１より垂直信号線８５に第１の信号電荷が
転送される（第１０図ｔａ）。スイッチ９０が閉じてか
ら時間Ｔｓ２が経過すると、第２のカップリングコンデ
ンサ９２の入力端には、Ｔｓ２の間に垂直信号線８５に
発生したスメアとｎ行の信号電荷による垂直信号線８５
の電圧変動が伝達される。That is, as before, switches 86 and 90 are opened;
The vertical signal line 85 and the input end of the source follower 91 are reset (FIG. 1O ti). Then switch 86
. (Figure 10, ta). When time Ts2 has elapsed after the switch 90 is closed, the input terminal of the second coupling capacitor 92 is filled with the vertical signal line 85 caused by the smear generated on the vertical signal line 85 during Ts2 and the signal charges in the n rows.
voltage fluctuations are transmitted.
Ｔｓｉ＝Ｔｓ２とするとスメアによる電圧変動は時刻ｔ
、と同一となるため、第２のカップリングコンデンサ９
２の入力端の電圧は時刻ｔ、の時点に比し、ｎ行の信号
電荷による電圧変動分だけが変化する。If Tsi=Ts2, the voltage fluctuation due to smear is at time t
, so the second coupling capacitor 9
Compared to time t, the voltage at the input terminal of No. 2 changes only by the voltage fluctuation due to the signal charges of the n rows.
この結果、第２のカップリングコンデンサ９２の出力端
電圧はリセット電圧Ｖｖ、に、第１の信号電荷による第
２のカップリングコンデンサ９２の入力端電圧変動が第
２のカップリングコンデンサ９２とメモリ容量９７によ
り容量分割された電圧変動を付加した値となる。この電
圧をスイッチ９４を閉じることにより、メモリ容量９７
に保持し、ｎ行の信号の読み出しを完了する（第１０１
！ｌｔ、）。この後、同様にしてｎ＋１行の信号がメモ
リ容量９８に保持される。As a result, the output terminal voltage of the second coupling capacitor 92 becomes the reset voltage Vv, and the input terminal voltage fluctuation of the second coupling capacitor 92 due to the first signal charge increases between the second coupling capacitor 92 and the memory capacitor. The value is obtained by adding voltage fluctuations divided by capacitance by 97. By closing the switch 94, this voltage is applied to the memory capacity 97.
to complete the readout of the n-row signals (101st
! lt,). Thereafter, the signals of the n+1 row are held in the memory capacity 98 in the same manner.
水平走査期間に入ると、ｎ行とｎ＋１行の信号が順に読
み出される。すなわち、水平走査回路８４により、ある
列（ｍ列とする）が選択されると、ｍ列の水平スイッチ
９６が水平走査回路８４の駆動パルスφ、に同期して開
き、水平信号線１０２にはｎ行とｎ＋１行の信号が各メ
モリ容量より読み出され、増幅器１０３を介して出力端
子０ＵＴ１及び○ＵＴ２より外部に出力される。この後
、駆動パルスφ２より水平信号線１０２はリセット電圧
ＶＶ、にリセットされる。この動作が順次行われ、各列
の信号が順次読み出される。When the horizontal scanning period begins, signals on the nth row and the n+1th row are read out in sequence. That is, when a certain column (referred to as column m) is selected by the horizontal scanning circuit 84, the horizontal switch 96 of column m opens in synchronization with the drive pulse φ of the horizontal scanning circuit 84, and the horizontal signal line 102 is The signals of the nth row and the n+1th row are read out from each memory capacity, and are outputted to the outside from the output terminals 0UT1 and UT2 via the amplifier 103. Thereafter, the horizontal signal line 102 is reset to the reset voltage VV by the drive pulse φ2. This operation is performed sequentially, and the signals in each column are sequentially read out.
本実施例においては、ＭＯ８型素子を走査回路として用
いた場合に問題となる容量結合によるスメアは、メモリ
容量９７．９８への信号読み出し前に蓄積容量を飽和前
の状態とし、スメア差動を行うことにより低減すること
ができる。また、ＭＯ８型素子の一つの雑音源であるＫ
ＴＣ雑音をダブルサンプリングを行うことにより低減で
きる。またもう一つの雑音源である増幅器雑音も、増幅
器を列ごとに設け、雑音帯域を下げることにより低減で
きる０以上の結果、従来のＭＯ８型走査回路の持つ高飽
和信号電流、低残像という利点を損なうことなく、低ス
メア低雑音特性を合わせ持つ積層型固体撮像装置を実現
することができる。In this example, the smear caused by capacitive coupling, which is a problem when an MO8 type element is used as a scanning circuit, is solved by setting the storage capacitance to a state before saturation before reading out the signal to the memory capacity 97.98, and creating a smear differential. This can be reduced by In addition, K, which is one of the noise sources of MO8 type elements,
TC noise can be reduced by performing double sampling. In addition, amplifier noise, which is another noise source, can be reduced to 0 or more by providing amplifiers in each column and lowering the noise band. As a result, the advantages of high saturation signal current and low afterimage of the conventional MO8 type scanning circuit are achieved. A stacked solid-state imaging device having low smear and low noise characteristics can be realized without any loss.
なお、光導電膜をアバランシュ動作を行うａ−８ｅで構
成した場合には、信号電荷の発生量が従来素子の１０倍
程度となり、走査基板の読み出し可能電荷量を大きくす
ることが広いダイナミックレンジを持つ装置の実現には
必須となる。このため、走査基板としては、上記第９図
の実施例を含むＭｏＳ型基板を用いることが必要となる
。Note that when the photoconductive film is composed of a-8e that performs avalanche operation, the amount of signal charge generated is about 10 times that of conventional elements, and increasing the amount of charge that can be read from the scanning substrate makes it possible to achieve a wide dynamic range. It is essential to realize the device that has this feature. Therefore, it is necessary to use a MoS type substrate, including the embodiment shown in FIG. 9, as the scanning substrate.
また、以上の実施例においては、Ｐ型基板上にｎ型拡散
層を形成した場合を述べたが、ｎ型基板上にＰ型拡散層
を形成してもよいし、ｎ型基板上にＰ型ウェルを形成し
、このウェル内にｎ型拡散層を形成してもよい。Furthermore, in the above embodiments, a case was described in which an n-type diffusion layer was formed on a P-type substrate, but a P-type diffusion layer may be formed on an n-type substrate, or a P-type diffusion layer was formed on an n-type substrate. A type well may be formed, and an n-type diffusion layer may be formed within this well.
本発明によれば、光電変換特性にニイー特性を持たせる
ことができるので、従来素子に比べ約５程度度の高い飽
和面照度を実現し、広いダイナミックレンジを得ること
ができる。According to the present invention, since the photoelectric conversion characteristic can have a knee characteristic, it is possible to realize a saturated surface illuminance that is about 5 degrees higher than that of conventional elements, and to obtain a wide dynamic range.
また、飽和信号電流を従来素子に比べ５倍以上に向上す
ることにより広いダイナミックレンジを実現できる。Furthermore, by increasing the saturation signal current by more than five times compared to conventional elements, a wide dynamic range can be realized.
第１図、第４図、第５図、第６図、第７図及び第８図は
いずれも本発明による固体撮像素子の実施例の断面構造
図、第２図は第１図、実施例の光導電膜の膜にかかる電
界と信号電流密度の関係を示す図、第３図は第１図の実
施例の光電変換特性を示す図、第９図は本発明による撮
像装置の一実施例の回路構成図、第１０図は第９図実施
例の動作説明のための駆動パルスタイミングを示す図で
ある。
２・・・ａ −Ｓｅ
５・・・高抵抗
７−２・・・クランプトランジスタゲート電極６−３・
・・クランプトランジスタドレイン拡散層１５・・・Ｍ
Ｏ８容量上部電極
１６・・・ＭＯ８容量絶縁膜
１７・・・高抵抗ＭＯ８容量電極
８７・・・増幅器
８９、９２・・・カップリングコンデンサ９０、９３・
・・クランプスイッチ
９７、９８・・・メモリ容量
代理人弁理士 中 村 純之助
−−−−・・透光＋１電緬
第１図
０．０１
０．１ １ １０
面照、４（ｌｘｌ
第３図
電１− Ｖ／Ｌ （ｘｌｏ６Ｖ／ａｎ）第２図
７−２−−−−・クラ；γトラ）シ゛スタケ一ト電極８
Ｌ
Ｓ５
第」０図FIG. 1, FIG. 4, FIG. 5, FIG. 6, FIG. 7, and FIG. 8 are all cross-sectional structural diagrams of embodiments of the solid-state imaging device according to the present invention, and FIG. FIG. 3 is a diagram showing the photoelectric conversion characteristics of the embodiment of FIG. 1, and FIG. 9 is an embodiment of the imaging device according to the present invention. FIG. 10 is a diagram showing drive pulse timing for explaining the operation of the embodiment shown in FIG. 2... a -Se 5... High resistance 7-2... Clamp transistor gate electrode 6-3.
...Clamp transistor drain diffusion layer 15...M
O8 capacitor upper electrode 16...MO8 capacitor insulating film 17...High resistance MO8 capacitor electrode 87...Amplifiers 89, 92...Coupling capacitors 90, 93...
・・Clamp switch 97, 98・・Memory capacity agent Junnosuke Nakamura---・・Transparent + 1 Electric Burmese Figure 1 0.01 0.1 1 10 Surface light, 4 (lxl Figure 3) Voltage 1-V/L (xlo6V/an) Fig. 2 7-2--Cl;
L S5 No. 0 Figure
Claims (1)
た複数の画素電極を設け、上記透光性電極と画素電極間
にターゲット電圧を印加する光電変換部と、上記光電変
換部で発生した電荷を蓄積する荷蓄積部と、上記電荷蓄
積部から所定の時間に電荷を取り出す信号読み出し部を
もつ撮像装置において、上記ターゲット電圧が上記光導
電膜の光感度が増幅作用を持つ領域に設定され、上記画
素電極と上記電荷蓄積部との間に抵抗体を設けて構成さ
れたことを特徴とする固体撮像装置。 ２、請求項１記載において、上記電荷蓄積部の一部を上
記抵抗体の上記電荷蓄積部側を一方の電極とし、絶縁膜
を構成要素とする容量素子で構成したことを特徴とする
固体撮像装置。 ３、光導電極の一面に透光性電極を他面に画素に対応し
た複数の画素電極を設け上記透光性電極と画素電極との
間にターゲット電圧を印加する光電変換部と、半導体基
体に上記複数の画素電極のそれぞれに電気的に接続され
上記光電変換部で発生した電荷を蓄積する電荷蓄積部と
、上記電荷蓄積部から所定の時間に電荷を取り出す半導
体スイッチを持つ信号読み出し部とを有する撮像装置に
おいて、上記電荷蓄積部の一部が上記半導体スイッチを
一方の電極とし、絶縁体を構成要素とする容量素子で構
成されたことを特徴とする固体撮像装置。 ４、請求項第１、第２又は第３記載において、上記光導
電膜が非晶質セレン膜で構成されたことを特徴とする固
体撮像装置。 ５、請求項第１、第２、第３又は第４記載において、上
記電荷蓄積部に電荷蓄積部の電圧を一定の電圧にクラン
プするためのトランジスタを付加して構成されたことを
特徴とする固体撮像装置。[Claims] 1. Photoelectric conversion in which a transparent electrode is provided on one side of a photoconductive film and a plurality of pixel electrodes corresponding to pixels are provided on the other side, and a target voltage is applied between the transparent electrode and the pixel electrode. In the imaging device, the target voltage is set to the photoconductive film, and includes a charge storage section that stores charges generated in the photoelectric conversion section, and a signal readout section that extracts charges from the charge storage section at a predetermined time. A solid-state imaging device characterized in that sensitivity is set in a region having an amplification effect, and a resistor is provided between the pixel electrode and the charge storage section. 2. The solid-state imaging device according to claim 1, wherein a part of the charge storage section is constituted by a capacitive element having one electrode on the charge storage section side of the resistor and an insulating film as a component. Device. 3. A photoelectric conversion section for applying a target voltage between the light-transmitting electrode and the pixel electrode by providing a light-transmitting electrode on one surface of the photoconductive electrode and a plurality of pixel electrodes corresponding to pixels on the other surface, and a semiconductor substrate. A charge storage section that is electrically connected to each of the plurality of pixel electrodes and stores charges generated in the photoelectric conversion section; and a signal readout section that has a semiconductor switch that extracts charges from the charge storage section at a predetermined time. 1. A solid-state imaging device comprising: a part of the charge storage section comprising a capacitive element having the semiconductor switch as one electrode and an insulator as a component. 4. A solid-state imaging device according to claim 1, wherein the photoconductive film is composed of an amorphous selenium film. 5. In the first, second, third, or fourth claim, the charge storage section is configured by adding a transistor for clamping the voltage of the charge storage section to a constant voltage. Solid-state imaging device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1028614A JPH02208974A (en) | 1989-02-09 | 1989-02-09 | Solid-state image sensing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1028614A JPH02208974A (en) | 1989-02-09 | 1989-02-09 | Solid-state image sensing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02208974A true JPH02208974A (en) | 1990-08-20 |
Family
ID=12253438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1028614A Pending JPH02208974A (en) | 1989-02-09 | 1989-02-09 | Solid-state image sensing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02208974A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3966557B2 (en) * | 1995-08-11 | 2007-08-29 | 株式会社東芝 | Image system, solid-state imaging device semiconductor integrated circuit used therein, and differential output method |
| JP2015115357A (en) * | 2013-12-09 | 2015-06-22 | 浜松ホトニクス株式会社 | Radiation image sensor |
| CN107004690A (en) * | 2015-11-12 | 2017-08-01 | 松下知识产权经营株式会社 | Optical sensor |
| JP2019024200A (en) * | 2018-08-06 | 2019-02-14 | キヤノン株式会社 | Photoelectric conversion device, photoelectric conversion system |
| JP2019068131A (en) * | 2017-09-28 | 2019-04-25 | 日本放送協会 | Laminated solid-state imaging apparatus and method of reducing random noise therein |
| JP2020170869A (en) * | 2009-11-06 | 2020-10-15 | 株式会社半導体エネルギー研究所 | Image sensor |
-
1989
- 1989-02-09 JP JP1028614A patent/JPH02208974A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3966557B2 (en) * | 1995-08-11 | 2007-08-29 | 株式会社東芝 | Image system, solid-state imaging device semiconductor integrated circuit used therein, and differential output method |
| JP2020170869A (en) * | 2009-11-06 | 2020-10-15 | 株式会社半導体エネルギー研究所 | Image sensor |
| JP2022032053A (en) * | 2009-11-06 | 2022-02-24 | 株式会社半導体エネルギー研究所 | Image sensor |
| JP2015115357A (en) * | 2013-12-09 | 2015-06-22 | 浜松ホトニクス株式会社 | Radiation image sensor |
| KR20160096623A (en) * | 2013-12-09 | 2016-08-16 | 하마마츠 포토닉스 가부시키가이샤 | Radiation image sensor |
| CN105981172A (en) * | 2013-12-09 | 2016-09-28 | 浜松光子学株式会社 | Radiation image sensor |
| US9761631B2 (en) | 2013-12-09 | 2017-09-12 | Hamamatsu Photonics K.K. | Radiation image sensor |
| EP3082164B1 (en) * | 2013-12-09 | 2022-06-01 | Hamamatsu Photonics K.K. | Radiation image sensor |
| CN107004690A (en) * | 2015-11-12 | 2017-08-01 | 松下知识产权经营株式会社 | Optical sensor |
| CN107004690B (en) * | 2015-11-12 | 2021-05-14 | 松下知识产权经营株式会社 | Optical sensor |
| JP2019068131A (en) * | 2017-09-28 | 2019-04-25 | 日本放送協会 | Laminated solid-state imaging apparatus and method of reducing random noise therein |
| JP2019024200A (en) * | 2018-08-06 | 2019-02-14 | キヤノン株式会社 | Photoelectric conversion device, photoelectric conversion system |
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