JPS5910029A - Analog-digital convertion method - Google Patents
Analog-digital convertion methodInfo
- Publication number
- JPS5910029A JPS5910029A JP11923582A JP11923582A JPS5910029A JP S5910029 A JPS5910029 A JP S5910029A JP 11923582 A JP11923582 A JP 11923582A JP 11923582 A JP11923582 A JP 11923582A JP S5910029 A JPS5910029 A JP S5910029A
- Authority
- JP
- Japan
- Prior art keywords
- output
- bits
- converter
- conversion
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
- H03M1/146—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages all stages being simultaneous converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
- H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はアナログ電圧をデジタル変換器変換方法に関し
、その目的Ｕ低分解能のＡ−１）変換器で高分解能の変
換を実施することができる変換方法を提供するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for converting an analog voltage to a digital converter, and its purpose is to provide a conversion method capable of performing high-resolution conversion with a low-resolution A-1) converter. be.
Ｎｔ 近、ｍ：子オーブンレンジ、ルームエアーコンデ
ィショナ等の家庭電化製品でｌ’Ｊ： Ａ−１） ＆換
器内蔵ｉ１；Ｊのマイクロコンピュータがムく使用さｉ
している。Nt Near, m: Home appliances such as submicrowave ovens and room air conditioners l'J: A-1) & built-in converter i1; J's microcomputer is often used i
are doing.
ここで内蔵きれているｌｉ１記Ａ−１）変換器は、１ト
１１分解ｆｉｔ；のものけ高価になるなどの坤由により
低分解能Ｌ’、 １ｔ１１常、８ヒツト〕のものが使用
される。しかし、少しでも精度の高い制御が実行できる
ように、廉価で高分解能の変換器が望まれている。The built-in transducer here has a low resolution L', 1t11 resolution, 1t11 resolution, and 8 hits, because it is expensive. . However, an inexpensive, high-resolution converter is desired so that control can be executed with as much precision as possible.
本弁明のＡ−Ｄ変換方法は、人力未知型Ｌ１こと基準電
圧を比較して前記人力未知電圧が何れのレベル区分に属
するかを判定し７、この判定されたレベル（べ分の最低
電圧を前記入力未知電圧から差引いて７−Ｊ−ｖＪり・
デジタル変換器の人力に印加し、このアナログ・デシタ
）Ｖ変換器のＮ１ヒッ１−〔イトｌし、Ｎ。The A-D conversion method of the present defense compares the human-powered unknown type L1, also known as the reference voltage, to determine which level category the human-powered unknown voltage belongs to7, and then converts the determined level (the lowest voltage of the Subtracted from the input unknown voltage is 7-J-vJ.
Apply power to the digital converter and apply this analog digitizer to the N1 input of the V converter.
は′！番数〕の変換出力を上位側ヒツト出力とし前記最
低′電圧に相当するＮ２ヒント〔但し、Ｎ２は整数〕ヲ
」ユ位側ビット出力として（Ｎ 、 −１−Ｎ ２）ヒ
ントの変換出力を得ることを特徴とし、廉価な低分解能
のＡ−１）変換器で高分解能のデシタ）Ｖ変換を実行で
きる効果がある。teeth'! The conversion output of the N2 hint [however, N2 is an integer] which corresponds to the above-mentioned lowest voltage is the upper bit output. It has the advantage of being able to perform high-resolution decimal (decimal) V conversion with an inexpensive low-resolution A-1) converter.
以下、本発明の変換方法を具体的な実施例に基づいて説
明する。The conversion method of the present invention will be explained below based on specific examples.
第１図は８ヒツトのＡ−Ｄ変換器（１）に外部回路を春
ノ加して１０ヒツトの使換出力を得る場合の構成を示す
、（２）は人力未知電圧Ｅｉｎが印加ぴれる入力端子、
（３） Ｉｒ１ 定’ＫＣ圧’７４１ ｉＭ、（Ｒ，）
〜（Ｒ，）はｎ＋＋記定電圧電源（３）の出力′電圧
分圧用の抵抗で、その抵抗値はＲ，＝Ｒ２＝Ｒ，に設定
きれている。 （４）〜（７）は反転入力←→い１各ｈ
’ｉ、 １８ η１圧 ０ ホ ル ト 、 ｅ、ホ
ル ト 、 ｅ２ホ ル ト 、ｅ５ホルトが印加され
非反転入力（１）に前記人力未知電圧Ｅ ｉ ｎが印加
された演算増幅器で、この演算増幅Ｈ（４Ｊ 〜（７）
の出力には、それぞれＥｉｎ 、 （Ｅｉｎ−ｅ 、
） 。Figure 1 shows the configuration when an external circuit is added to an 8-hit A-D converter (1) to obtain a 10-hit reusable output. (2) shows the configuration when an unknown human voltage Ein is applied. input terminal,
(3) Ir1 constant 'KC pressure'741 iM, (R,)
.about.(R,) is a resistor for dividing the output' voltage of the n++ specified voltage power supply (3), and its resistance value is set to R,=R2=R. (4) to (7) are inverted inputs←→1 each h
'i, 18 η1 pressure 0 Holt, e, Holt
This operational amplifier H(4J to (7)
The outputs of are Ein, (Ein-e,
).
（Ｅｉｎ−ｅ２）、（Ｅｉｎ−ｅ、）の電圧が発生する
。（８） 〜ＯＩＪは前に６演算増１噛器（４）〜（７
）の出力電圧Ｅ。、Ｅ１＋ Ｅ ２ ＊ ｈ ３のレベ
ル判定を行うコンパレータで、ここで前記Ａ−Ｄ変換器
（１）のフルヌケ−）ｖＦ、５時のＡ−Ｄ変換器（１）
の入力電圧を−ＥＭＡｘ〔ここでＥＭＡｘ−ｅ、〕とす
ると、各コンパレータ（８）〜ＯυはそれぞれＥ。＜
ＥＭ Ａ ｚ ＋ ０ 〈Ｅｌ＜ＥＭ Ａ Ｘ ＋０４
Ｅ ２ ＜ ＥＭ Ａ Ｘ １０ ≦Ｅ ３＜ ＫＭ
Ａ Ｘ ｋ検出して出力が論理レベル″Ｈ”に反転す
るよう構成されている。Voltages (Ein-e2) and (Ein-e,) are generated. (8) ~OIJ has 6 operations incremented by 1 bit (4) ~ (7
) output voltage E. , E1 + E 2 * h 3 is a comparator that determines the level of the A-D converter (1), where the full null of the A-D converter (1)) vF, 5 o'clock A-D converter (1)
When the input voltage of is -EMAx [here, EMAx-e], each of the comparators (8) to Oυ is E. <
EM A z + 0 <El<EM A X +04
E 2 < EM A X 10 ≦E 3 < KM
It is configured so that the output is inverted to logic level "H" upon detection of A.times.k.
αつ〜ｑυは一端がそれぞれ前記演算増幅器（４）〜（
７）の出力に接続され他端相σが接続されたアナ口〃・
ヌ・ｆラグ−で、このアナログ・スイッチ（２）〜０つ
はそれぞれそのレベル区分のコンパレータ（８）〜Ｏｔ
ｌの出力が論理レベル“Ｈ”に反転１．た時にメイク状
態となっで０ｉ１記Ａ−Ｄ変換器（１）の人力に印加さ
れる。ｏＱは０１１記Ｊンバレータ（８）〜θυのうち
の出力が論理レベル“１１”に反転しているコンパレー
タが属するレベル区分の最低電圧に相当する２ビットの
デシタル１１号を出力するコーグで、コンパレータ（８
ン〜０υがそれぞれ論理レベル“Ｈ”に反転した場合に
はコータ（１り出力には、基準電圧０ ＋ ｅ 、＋
６２ 、ｅ ５に柑尚する２ヒツトのデジタル信号とし
て下記表の信号を出力する。α and qυ have one end connected to the operational amplifiers (4) to (
7) Connected to the output of the hole and connected to the other end phase σ.
These analog switches (2) to 0 are respectively the comparators (8) to Ot for that level division.
The output of l is inverted to logic level "H" 1. When it is in the make state, the manual power is applied to the A-D converter (1) described in 0i1. oQ is a comparator that outputs 2-bit digital number 11 corresponding to the lowest voltage of the level division to which the comparator belongs, whose output among the J inverters (8) to θυ of 011 is inverted to logic level "11". (8
When the voltages 0υ to 0υ are respectively inverted to the logic level “H”, the coater (1 output has reference voltages 0 + e, +
62, e The signals shown in the table below are output as two digital signals corresponding to 5.
く表〉
０７）ｅよ並−直列変換器で、Ａ−Ｄ変換器（１）出力
の８ビットケ１−６γ側ヒツト、コーダ四出力の２ヒツ
トを上位側ビットとして受は入れて、ヒツト直列で変換
出力０樽を順次出力する。Table 07) In the parallel-serial converter e, accept the 8 bits of the output of the A-D converter (1) as the 1-6γ side hits and the 2 hits of the 4 outputs of the coder as the upper bits, and convert the The conversion output 0 barrels are output one after another.
第２図は入力未知電圧Ｅｉｎに対する演算増幅器（４）
〜（７）の出力電圧Ｅ。−Ｅ５を表わす。例えば人力未
知電圧Ｅｉｎがｅ、≦Ｅ ｉ ｎ ＜ ｅ ２の場合、
コンパレータ（９）出力が反転してアナログ・スイッチ
θ］がメイク状態となり、（Ｅｉｎ−ｅ、）がＡ−Ｄ
ｉ換器（１）の入力に印加されて８ビツトのデジタル信
号〔例えば“（）ｏｏｏｏｏｏｏ” 〕に変換される。Figure 2 shows the operational amplifier (4) for the input unknown voltage Ein.
~(7) Output voltage E. - represents E5. For example, if the unknown human voltage Ein is e, ≦E in < e 2,
The output of the comparator (9) is inverted, the analog switch θ] becomes the make state, and (Ein-e,) becomes A-D.
It is applied to the input of the i-converter (1) and converted into an 8-bit digital signal (for example, "()oooooooo").
この時、ゴーダ０１出力は前記表から”０１”となり、
並−直列変換器αηには上位ビットから順に０１０００
（３００００”の１０ピツ］・の変換出力α綽がビット
並列で入力される。At this time, Gouda 01 output becomes "01" from the above table,
01000 is input to the parallel-serial converter αη in order from the upper bit.
(10 bits of 30,000'') conversion output α is input in parallel bits.
なお、上記実施例では、各基準電圧０．ｅ、 、ｅ２．
ｅ。Note that in the above embodiment, each reference voltage is 0. e, , e2.
e.
と前記人力未知電圧Ｅｉｎ （！：を４つの演算増幅器
（４）〜（７）を用いて同時に比較して入力未知電圧が
何れのレベル区分に属するかを判定したが、これは、基
準電圧を順次切換えて時分割でレベル区分の判定を実施
しても同様の効果が得られる。and the human input unknown voltage Ein (!:) were compared simultaneously using four operational amplifiers (4) to (7) to determine which level category the input unknown voltage belongs to. A similar effect can be obtained by sequentially switching and determining the level classification in a time-sharing manner.
以上説明のように本発明のＡ−Ｄ変換方法によると、低
分解能のＡ−１）変換器とわずかの外部回路を付加する
だけで高価な面分解能のＡ−１）変換と同等の変換出力
が得られ、製品コストの低廉化に寄与できるものでるる
１．As explained above, according to the A-D conversion method of the present invention, a conversion output equivalent to that of the expensive surface resolution A-1) conversion can be obtained by simply adding a low-resolution A-1) converter and a few external circuits. 1. This can contribute to lower product costs.
第１図は本発明のＡ〜１）変換方法の具体的な一実施例
の構成図、第２図は第１図の人出方特性図である。
Ｕ）・・・Ａ−１）変換器、（３）・・・定電圧電源、
（４）〜（７）・・・演＋ｉ ｍ ＋＋１Ｉ１１器、（
８）〜０υ・・・コンパレータ、ａａａｉ・・・アナロ
グ・スイッチ、ｏＱ・・・コーグ、Ｅ＋ｎ・・・人カ未
知電圧代理人 森 本 義 弘FIG. 1 is a block diagram of a specific embodiment of the conversion method A to 1) of the present invention, and FIG. 2 is a diagram showing the turnout characteristics of FIG. 1. U)...A-1) Converter, (3)... Constant voltage power supply,
(4) ~ (7)... performance + i m ++1I11 instrument, (
8) ~0υ...Comparator, aaai...Analog switch, oQ...Korg, E+n...Unknown voltage agent Yoshihiro Morimoto
Claims (1)
電圧が何れのレベル区分に属するかを判定し、この判定
されたレベル区分の最低電圧を前記人力未知電圧から差
引いてアナログ・デジタル変換器の入力に印加し、この
アナログ・デジタ／Ｉ／変換器のＮ１ビット〔但し、Ｎ
、は整数〕の変換出力をＦ位側ビット出力とし前記最低
電圧に相当するＮ２ビット〔但し、Ｎ２は整数〕を上位
側ヒツト出力として（Ｎ、＋Ｎ２１ビットの変換出力を
得るＡ−Ｄ変換方法。[Claims] 1. Comparing the input unknown voltage and a reference voltage to determine which level classification the input unknown voltage belongs to, and subtracting the lowest voltage of the determined level classification from the manual unknown voltage. is applied to the input of the analog-to-digital converter, and the N1 bit of this analog-to-digital/I/converter [however, N
, is an integer] as the F-order bit output, and the N2 bits corresponding to the lowest voltage (N2 is an integer) as the high-order hit output (A-D conversion method to obtain a conversion output of N, +N21 bits) .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11923582A JPS5910029A (en) | 1982-07-08 | 1982-07-08 | Analog-digital convertion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11923582A JPS5910029A (en) | 1982-07-08 | 1982-07-08 | Analog-digital convertion method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5910029A true JPS5910029A (en) | 1984-01-19 |
Family
ID=14756302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11923582A Pending JPS5910029A (en) | 1982-07-08 | 1982-07-08 | Analog-digital convertion method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5910029A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03274918A (en) * | 1990-03-26 | 1991-12-05 | Mitsubishi Electric Corp | A/d converter |
| JP2007192770A (en) * | 2006-01-23 | 2007-08-02 | Sukegawa Electric Co Ltd | Vacuum feed through for thermocouple |
| JP2012227126A (en) * | 2011-04-07 | 2012-11-15 | Nissan Motor Co Ltd | Apparatus and method for manufacturing bagged electrode |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5235968A (en) * | 1975-09-16 | 1977-03-18 | Sony Corp | Analog digital convertor |
| JPS5623026A (en) * | 1979-08-03 | 1981-03-04 | Nec Corp | Analog-digital conversion unit |
-
1982
- 1982-07-08 JP JP11923582A patent/JPS5910029A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5235968A (en) * | 1975-09-16 | 1977-03-18 | Sony Corp | Analog digital convertor |
| JPS5623026A (en) * | 1979-08-03 | 1981-03-04 | Nec Corp | Analog-digital conversion unit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03274918A (en) * | 1990-03-26 | 1991-12-05 | Mitsubishi Electric Corp | A/d converter |
| JP2007192770A (en) * | 2006-01-23 | 2007-08-02 | Sukegawa Electric Co Ltd | Vacuum feed through for thermocouple |
| JP2012227126A (en) * | 2011-04-07 | 2012-11-15 | Nissan Motor Co Ltd | Apparatus and method for manufacturing bagged electrode |
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