JPS5898927A - Etching method for silicon substrate - Google Patents
Etching method for silicon substrateInfo
- Publication number
- JPS5898927A JPS5898927A JP19680081A JP19680081A JPS5898927A JP S5898927 A JPS5898927 A JP S5898927A JP 19680081 A JP19680081 A JP 19680081A JP 19680081 A JP19680081 A JP 19680081A JP S5898927 A JPS5898927 A JP S5898927A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- groove
- grooves
- depth
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 title claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 4
- 229910052710 silicon Inorganic materials 0.000 title claims description 4
- 239000010703 silicon Substances 0.000 title claims description 4
- 239000013078 crystal Substances 0.000 abstract description 7
- 230000001419 dependent effect Effects 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 description 8
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 241001648319 Toronia toru Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001805 chlorine compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、同一シリコン（以下５ｉと記す）基板に深さ
の異なる複数の微細なエツチング溝を形成するエツチン
グ方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an etching method for forming a plurality of fine etching grooves with different depths in the same silicon (hereinafter referred to as 5i) substrate.
ヒドラジン（Ｎ＊Ｈｔ ）や水酸化カリウム（ＫＯＨ）
を用いたウェットエツチング法およびＣＣＺ、やＰｃｔ
、などの塩素化合物ガスを用いたプラズマエツチングの
ごときいわゆるドライエツチング法では、ｓｔｗｔ晶面
に依存し九エツチングが可能である。第１図に示すよう
に、このようなエツチング法を（１００）面を主表面と
する３ｉ基板１に適用すると（１００Ｊ面に対し約５５
−傾斜し九（ｌ ｌ 、ｌ ）面２がほとんどエツチン
グされずに残り、７字形の溝３となってエツチングが停
止する九め、溝の幅を調節することによってエツチング
深さを変えることができる。しかし、この場合の溝の幅
は、深さの約１．４倍に制約され、これ以上微細な溝を
形成することはできない。Hydrazine (N*Ht) and potassium hydroxide (KOH)
Wet etching method using CCZ, Pct
In a so-called dry etching method such as plasma etching using a chlorine compound gas such as , etching is possible depending on the stwt crystal plane. As shown in FIG. 1, when such an etching method is applied to a 3i substrate 1 whose main surface is the (100) plane (approximately 55
- The inclined nine (l l, l) surface 2 remains almost unetched, forming a figure 7-shaped groove 3 where etching stops; the etching depth can be changed by adjusting the width of the groove. can. However, the width of the groove in this case is limited to about 1.4 times the depth, and it is not possible to form a groove any finer than this.
本発明は、Ｓｉ基板に深さの異なる溝を形成する方法に
おいて、従来の方法よりもさらに微細な溝の形成が可能
なエツチング方法を提供することを目的とする。An object of the present invention is to provide an etching method for forming grooves of different depths in a Si substrate, which allows formation of finer grooves than conventional methods.
以下、本発明を実施例を参照して詳細に説明する。Hereinafter, the present invention will be explained in detail with reference to Examples.
実施例
（１００３面を主表面とするＳｉ基板を従来の結晶面依
存性のエツチング法を用いてエツチング差り、をもうけ
てエツチングを終了するまで停止しないようにする。こ
のようにして第１のエツチング工程により、まず段差り
、をもうけた後、第２図（ロ）Ｋ示すように狭い幅り、
の溝１１が所定の深さＤＩ になるように、結晶面依存
性がなくサイドエツチング量の少ない第２のエツチング
工程を用いてエツチングを追加する。この第２のエツチ
ング工程に適したエツチング法としては例えば、ドライ
エツチング法の一種でめるＣＣｌ２とＯ２の混合ガスを
用いた反応性スパッタエッチフグ法が適し％ Ｏ，混合
比２０％、ガス圧力５ｔａｂ高周波電力密度０．４ Ｗ
／ｃｍ”のエツチング条件ではエツチングマスク１６で
あるＳｔＯ，に対してＢ ｉ。Example (A Si substrate having a main surface of the 1003 plane is etched using a conventional crystal plane dependent etching method to create an etching difference and not to stop until the etching is completed. In this way, the first etching process is performed. Through the etching process, a step is first created, and then a narrow width is created as shown in Figure 2 (b) K.
Etching is added using a second etching process which is not dependent on the crystal plane and has a small amount of side etching so that the groove 11 has a predetermined depth DI. As an etching method suitable for this second etching step, for example, a reactive sputter etching method using a mixed gas of CCl2 and O2, which is a type of dry etching method, is suitable. 5tab high frequency power density 0.4W
/cm'' etching condition, B i with respect to StO, which is the etching mask 16.
を−択的にエツチングでき（選択比２０）かつサイドエ
ツチングをなくすことができる。can be selectively etched (selection ratio 20) and side etching can be eliminated.
Ｓｓ結晶の（１００）面と（１１１）面のなす角度が５
５度であるため、上記エツチング法で形成できる溝の幅
は次の範囲になる。The angle between the (100) and (111) planes of the Ss crystal is 5
5 degrees, the width of the groove that can be formed by the above etching method is in the following range.
０＜Ｌｌ ＜１．４Ｄ。0<Ll <1.4D.
Ｌｌ ＞ Ｌｌ ＋ １．４ ＤＩ
Ｌ、については段差Ｄ！の１．４倍まで、Ｌ、について
は下限なく微細溝を形成することが可能でるる。For Ll > Ll + 1.4 DI L, step D! It is possible to form fine grooves with no lower limit for L up to 1.4 times that of L.
第３図は本発明によるバイポーラＬＳＩのＣＮ分離構造
（コレクタとのコンタクトをとる領域を絶縁分離した構
造）の例である。深い溝２１は素子間の絶縁分離に用い
るためＮ０層２２を突き抜ける深さとし、浅い溝２３は
エミッタおよびベースを形成する領域２４とコレクタの
コンタクト領域２５を分離するためにＮ０鳴２２に到達
する深さとする。このよりなＳｉエツチングを行った後
に熱酸化膜２６を形成し、平坦化のためにＳＳＯ。FIG. 3 is an example of a CN isolation structure (a structure in which a region making contact with a collector is insulated and isolated) of a bipolar LSI according to the present invention. The deep groove 21 is deep enough to penetrate through the N0 layer 22 in order to provide isolation between elements, and the shallow groove 23 is deep enough to reach the N0 layer 22 in order to separate the region 24 forming the emitter and base from the contact region 25 of the collector. Satoru. After this further Si etching, a thermal oxide film 26 is formed and SSO is applied for planarization.
−？ＰＯｔｙｓｔなどの充填材２７で溝を埋め込んでＣ
Ｎ分離構造が完成する。このよりなＣＮ分離法では素子
間の絶縁分離用の深い溝２１とＣＮ分離用の浅い溝２３
を同時に形成できかつ溝を微細にできるので素子の高集
積化が可能になる。また溝の下部には傾斜２８．２９が
できるため、熱処理工程で生じる応力の溝の下部への集
中を緩和できる。−? Fill the groove with filler 27 such as POtyst and fill it with C.
The N separation structure is completed. In this more advanced CN isolation method, a deep trench 21 for insulation isolation between elements and a shallow trench 23 for CN isolation
Since the grooves can be formed at the same time and the grooves can be made finer, higher integration of the device becomes possible. Further, since the slopes 28 and 29 are formed at the bottom of the groove, concentration of stress generated in the heat treatment process at the bottom of the groove can be alleviated.
以上説明したように本発明によれば、エツチングマスク
を一度形成するだけで深さの異なるエツチング溝を同時
に形成でき、かつ溝の幅を微細にすることができる。さ
らにエツチングは段差をもうけるエツチングと最終的な
深さを調節するエツチングに分けて行うため、溝の深さ
の制御性が良い。また、本エツチングを用いてＣＮ分離
の絶縁分離構造を微細に形成することができる。As described above, according to the present invention, etching grooves of different depths can be simultaneously formed by forming an etching mask once, and the width of the grooves can be made fine. Furthermore, since the etching is performed separately into etching to create a step and etching to adjust the final depth, the depth of the groove can be easily controlled. Further, by using this etching, an insulating isolation structure of CN isolation can be formed finely.
第１図は結晶面依存性のエツチング形状を示す断面図、
第２図は本発明のエツチング工程を示す断面図、第３図
は本発明を用いたＣＮ分離構造を示す断面図である。
ｌ・・・Ｓｉ基板、２・・・傾斜面、３・・・溝。
代理人 弁理士 薄田利幸
１！ｉ １ 図
茅 ２ 図
（イ）
（口２
亨 ３ 図
１Figure 1 is a cross-sectional view showing the etching shape depending on the crystal plane.
FIG. 2 is a cross-sectional view showing the etching process of the present invention, and FIG. 3 is a cross-sectional view showing a CN isolation structure using the present invention. l...Si substrate, 2...slanted surface, 3...groove. Agent Patent Attorney Toshiyuki Usuda 1! i 1 Figure 2 Figure (a) (口2 Toru 3 Figure 1
Claims (1)
よりエツチング幅に応じた深さの異なる複数の溝を同一
基板内に形成する第１の工程とへ溝の深さを増す第２の
エツチング工程とから成ることを特徴とするシリコン基
板のエツチング方法。1. A first step in which a plurality of grooves with different depths according to the etching width are formed in the same substrate by an etching method that leaves the (111) plane of the silicon substrate, and a second etching step in which the depth of the grooves is increased. A method for etching a silicon substrate, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19680081A JPS5898927A (en) | 1981-12-09 | 1981-12-09 | Etching method for silicon substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19680081A JPS5898927A (en) | 1981-12-09 | 1981-12-09 | Etching method for silicon substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5898927A true JPS5898927A (en) | 1983-06-13 |
Family
ID=16363852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19680081A Pending JPS5898927A (en) | 1981-12-09 | 1981-12-09 | Etching method for silicon substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5898927A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02153551A (en) * | 1988-12-05 | 1990-06-13 | Nec Corp | Manufacture of semiconductor device |
| US5316618A (en) * | 1990-03-16 | 1994-05-31 | Westonbridge International Limited | Etching method for obtaining at least one cavity in a substrate |
| KR100414199B1 (en) * | 2001-01-05 | 2004-01-07 | 주식회사 오랜텍 | Method of fabricating a structure of silicon wafer using wet etching |
| JP2007200980A (en) * | 2006-01-24 | 2007-08-09 | Fuji Electric Device Technology Co Ltd | Semiconductor device, and method for manufacturing same |
| JP2012253219A (en) * | 2011-06-03 | 2012-12-20 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| JP2015133459A (en) * | 2014-01-16 | 2015-07-23 | 株式会社ディスコ | Method for dividing wafer |
-
1981
- 1981-12-09 JP JP19680081A patent/JPS5898927A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02153551A (en) * | 1988-12-05 | 1990-06-13 | Nec Corp | Manufacture of semiconductor device |
| US5316618A (en) * | 1990-03-16 | 1994-05-31 | Westonbridge International Limited | Etching method for obtaining at least one cavity in a substrate |
| KR100414199B1 (en) * | 2001-01-05 | 2004-01-07 | 주식회사 오랜텍 | Method of fabricating a structure of silicon wafer using wet etching |
| JP2007200980A (en) * | 2006-01-24 | 2007-08-09 | Fuji Electric Device Technology Co Ltd | Semiconductor device, and method for manufacturing same |
| JP2012253219A (en) * | 2011-06-03 | 2012-12-20 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| US8816430B2 (en) | 2011-06-03 | 2014-08-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing same |
| JP2015133459A (en) * | 2014-01-16 | 2015-07-23 | 株式会社ディスコ | Method for dividing wafer |
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