JPS5895874A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5895874A JPS5895874A JP56194715A JP19471581A JPS5895874A JP S5895874 A JPS5895874 A JP S5895874A JP 56194715 A JP56194715 A JP 56194715A JP 19471581 A JP19471581 A JP 19471581A JP S5895874 A JPS5895874 A JP S5895874A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- providing
- wirings
- layers
- solar battery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 230000006870 function Effects 0.000 abstract description 3
- 230000006386 memory function Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 abstract 10
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 abstract 1
- 230000003915 cell function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
- H01L31/02008—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier for solar cells or solar cell modules
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Engineering & Computer Science (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は積層構造の半導体集積回路素子において、少
なくとも一つの層に太陽電池を設けることによって電源
を供給するようにした半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit element having a stacked structure, in which a solar cell is provided in at least one layer to supply power.
積層構造の半導体集積回路素子を構成する際各層間の配
線を形成する−が最も困難である。各層間の配線には電
源の配線と各層間の信号の伝達配線とがある。このうち
電源の配線は各層又はいくつかの層に太wJWt池を設
ける事によって1層内の配線のみで1層間の配線が必要
なくなり、配線が絃らせる参になる。When constructing a semiconductor integrated circuit element having a stacked structure, the most difficult task is to form interconnections between each layer. The wiring between each layer includes a power supply wiring and a signal transmission wiring between each layer. For the power supply wiring, by providing a thick wJWt cell in each layer or several layers, the wiring between the layers is not necessary because only the wiring is within one layer, and the wiring becomes more efficient.
以下、この発明の実施例を図について説明する。Embodiments of the present invention will be described below with reference to the drawings.
第1図において、(1)〜(3)は積層構造の半導体集
積回路の各層、例えば(1)は光電変換素子をHするイ
メージ七ンサー/d、(2)は論理機能を有する層、(
3)は記憶機能を有する層、(4)は各層又はそのうち
のい(つかの層において、太陽電池機能を有する部分、
(5)は光(例えば太陽光、又は蛍光灯から?りらnる
)である。In FIG. 1, (1) to (3) are each layer of a semiconductor integrated circuit with a stacked structure, for example, (1) is an image sensor/d for H photoelectric conversion elements, (2) is a layer having a logical function, (
3) is a layer having a memory function; (4) is a portion having a solar cell function in each layer or some of the layers;
(5) is light (for example, from sunlight or fluorescent lights).
このように積層構造の内部に太ix池(4)を備える事
により各層間の電気的接続部が少なくなり配線の数も減
少する。又、電源が必要ない事からこの素子を光が存在
する場所ならばいかなる場所においても使用できる。In this way, by providing the thick IX pond (4) inside the laminated structure, the number of electrical connections between each layer is reduced, and the number of wirings is also reduced. Additionally, since no power source is required, this device can be used anywhere where light is present.
なお、この太陽電池(4)は必ずしも各層に設ける必要
はなく、少なくとも一つの層に設けるものであってもよ
い。Note that this solar cell (4) does not necessarily need to be provided in each layer, and may be provided in at least one layer.
図はこの発明の一実施例を示す半導体装置の断面図であ
る。内申(υはイメージセンサ層、(2〕は論mm能層
、(31)ハ記憶機能層、(4)ハ太li#!lvt池
、(5)ハ光源である。
代地人 sth信−The figure is a sectional view of a semiconductor device showing an embodiment of the present invention. (υ is the image sensor layer, (2) is the logic layer, (31) is the memory function layer, (4) is the light source, (5) is the light source.
Claims (1)
又は複数の層において太陽電池を具備し。 電圧を流を各層に供給する事により、各層間の電源の配
線を減らす事を特徴とする半導体装置。[Scope of Claim] A semiconductor integrated circuit device having a stacked structure, comprising a solar cell in one or more layers thereof. A semiconductor device characterized by reducing power supply wiring between each layer by supplying voltage and current to each layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56194715A JPS5895874A (en) | 1981-11-30 | 1981-11-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56194715A JPS5895874A (en) | 1981-11-30 | 1981-11-30 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5895874A true JPS5895874A (en) | 1983-06-07 |
Family
ID=16329037
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56194715A Pending JPS5895874A (en) | 1981-11-30 | 1981-11-30 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5895874A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5483386A (en) * | 1977-12-15 | 1979-07-03 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1981
- 1981-11-30 JP JP56194715A patent/JPS5895874A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5483386A (en) * | 1977-12-15 | 1979-07-03 | Matsushita Electric Ind Co Ltd | Semiconductor device |
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