JPS5895837A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable operation at high speed by forming a reverse conduction type region into a field region under a wiring layer. CONSTITUTION:The first N conduction type source regions 2, 2' and drain regions 3, 3' are shaped onto a P type silicon single crystal substrate 1 in mutually separated form, and gate oxide films 4, 4' by silicon dioxide and gate electrodes 5, 5' by N conduction type polysilicon are molded among the source regions and the drain regions. The second N conduction type semiconductor layer 14 having conduction type reverse to an insulating region 13 complementing active regions 12, 12' into which semiconductor elements uniting the N conduction type layers 2, 3, 2', 3' and the gate insulating films 4, 4' are formed is buried into the insulating region 13 so as not to contact with the active regions 12, 12'.

Description

【発明の詳細な説明】 本発明は半導体集積回路装置に係り、特にフィールド領
域や配線層下の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a field region and a structure under a wiring layer.

従来の半導体集積回路装置は、−導電型半導体基板に複
数個の半導体素子を形成する活性領域とこれらの活性領
域間を電気ｉに絶縁分離するフィールド領域と、このフ
ィールド領域に設けられた絶縁膜と、この絶縁膜上を這
って素子間を電気的に接続する配線とで構成されていた
。そして、絶縁領域表面は全て同−導電型の半導体で形
成されていたために、配線と絶縁領域間には絶縁膜によ
って形成される静電容量が負荷され、高速動作が妨げら
れるという欠点があった。− 零発ＩｊＩの目的は、従来のこの種の集積回路装置の上
記欠点を減少させ、高速動作が可能な半導体集積回路を
提供すること１ＩＣＴｏる。A conventional semiconductor integrated circuit device includes an active region in which a plurality of semiconductor elements are formed on a conductive type semiconductor substrate, a field region for electrically insulating and separating these active regions, and an insulating film provided in this field region. and wiring that ran over this insulating film to electrically connect the elements. Furthermore, since the surfaces of the insulating regions were all made of semiconductors of the same conductivity type, the capacitance formed by the insulating film was loaded between the wiring and the insulating regions, which hindered high-speed operation. . - The purpose of the zero-source IjI is to reduce the above-mentioned drawbacks of conventional integrated circuit devices of this type and to provide a semiconductor integrated circuit capable of high-speed operation.

本発明の特徴は、−導電型半導体基板に検数の素子領域
が設けられ、これらの複数の素子領域間のフィールド領
域に絶縁膜が設けられ、この絶縁膜上を延在する配線層
が設けられた半導体集積回路装置において、この配線層
下のフィールド領域に逆導電型領域が設けられている半
導体集積回路装置にある。The features of the present invention are as follows: - A conductive type semiconductor substrate is provided with a plurality of element regions, an insulating film is provided in a field region between these plurality of element regions, and a wiring layer extending over the insulating film is provided. In the semiconductor integrated circuit device according to the present invention, an opposite conductivity type region is provided in a field region under the wiring layer.

例えば、−導電型半導体基板に、複数個の半導体素子を
形成する活性領域と、活性領域間を電気的に絶縁分離す
る、絶縁膜で覆われる絶縁領域とこの絶縁膜上を這って
これら素子間を電気的に接絖する配線とで形成される半
導体集積回路において、活性領域と絶縁領域との境界以
外の配線で覆われた絶縁領域表面に、配線で覆われない
絶縁領域と逆導電ＷＯ牛牛体体層埋込まれていることを
特徴とする半導体集積回路装置である。For example, on a conductive type semiconductor substrate, there is an active region in which a plurality of semiconductor elements are formed, an insulating region covered with an insulating film that electrically insulates and separates the active regions, and an insulating region that extends over the insulating film between these elements. In a semiconductor integrated circuit formed by wiring that electrically connects the active region and the insulating region, the surface of the insulating region covered with the wiring other than the boundary between the active region and the insulating region has a reverse conductivity between the insulating region not covered with the wiring and the reverse conductivity. This is a semiconductor integrated circuit device characterized by being embedded in a body layer.

すなわち、この半導体集積回路装置は、−導電型半導体
基板に複数個の帯導体素子を形成する活性領域と、活性
領域間な電気的に絶縁分離する、絶縁膜で覆われる絶縁
領域と、骸絶縁膜上を這って被素子間を電気的に接続す
る配線とで構成され且、活性領域と絶縁領域との境界以
外の、配線で覆われた絶縁領域表面に、配線で覆われな
い絶縁領域表面と逆導電瀝の半導体層が塩込まれている
ことを４１黴とし、配線と、配線で覆われない絶縁領域
とで形成される静電容量を、誼絶縁膜による静電容量と
、諌瀧込半導体層と該配線で覆われない絶縁領域とで形
成されるＰｎ＊合空乏層との直列後続とすることｋよっ
て配線の寄生静電容量を滅らし高速動作を可能ならしめ
るものである。That is, this semiconductor integrated circuit device includes an active region in which a plurality of strip conductor elements are formed on a conductive type semiconductor substrate, an insulating region covered with an insulating film that electrically insulates and separates the active region, and a skeleton insulating region. The surface of the insulating region, which is composed of wiring that extends over the film and electrically connects the devices to be used, and which is covered with the wiring other than the boundary between the active region and the insulating region, and the surface of the insulating region that is not covered with the wiring. The fact that the semiconductor layer with the opposite conductivity is salted is called "41", and the capacitance formed between the wiring and the insulating area not covered by the wire is called "capacitance due to the insulating film" and "Isataki". The series connection of the Pn* combined depletion layer formed by the embedded semiconductor layer and the insulating region not covered by the wiring eliminates the parasitic capacitance of the wiring and enables high-speed operation.

以下、本発明の一夾施例について図を用い乍ら特徴を詳
しく説明する０ 第１図（ａ）、（ｂ）は、本発明の金属酸化膜半導体−
（以後、ＭＯＢと略す）ＩＩ集積回路における実施例を
説明する、夫々、平面図と、そのｘ−ｘ’での断面図で
ある。Ｐ型シリコン単結晶基板１上に互いに分離して第
１のｎ導電型ソース領域２，２′及びドレーン領域３．
３／が形成され、ソース領域とドレーン領域との間に祉
二酸化シリコンによるゲート酸化膜４．４’　、ｎ導電
製ポリシリ；ンによるゲート電極５．５’が設けられて
いる。そして、厚さ０．４〜１．０μｍの気相成長法に
よる二酸化シリコン膜６にｎ導電型層を表面に導出する
為のコンタクト孔７１〜７ｄ、熱酸化による厚さ０．５
〜１．０μｍの二階化シリコン膜Ｂ上にあるポリシリコ
ン配線９を被覆する二酸化シリコン膜６にはコンタクシ
孔１０が各々設けられている。さらに、ドレーン３とゲ
ート電極５′とはコンタクト孔７ｂ、１０．アルミ晶つ
ム配６１１１．ポリシリコン配線９によって電気的に接
続されており、ｎ導電型層２．Ｂ、２’　、８’とゲー
ト絶縁膜４゜４Ｉを合併した帯導体素子を形成する活性
領域１２．１２’　（第１図（＆）で斜線を施した領域
）の補集合である絶縁領域１３には活性領域１２゜１２
’と接触しない様にして、絶縁領域１３と逆導電型であ
る第２のれ導電型半導体層１４が濶込重れている。第１
のｍＴｌ１層２．２’　、３．３’と第２のｎ１１層１
４とは距離ｙ、ｙ’を置いて活性領域１２と同領域１２
’がｎ！１層１４を介して電気的に接続されない様に、
離して形成されている。Hereinafter, features of one embodiment of the present invention will be explained in detail with reference to the drawings. Figures 1(a) and 1(b) show a metal oxide film semiconductor of the present invention.
(Hereinafter, abbreviated as MOB) They are a plan view and a cross-sectional view taken along line xx', respectively, for explaining an embodiment of the II integrated circuit. First n-conductivity type source regions 2, 2' and drain regions 3. are separated from each other on a P-type silicon single crystal substrate 1.
A gate oxide film 4.4' made of silicon dioxide and a gate electrode 5.5' made of n-conductive polysilicon are provided between the source region and the drain region. Then, contact holes 71 to 7d for leading out an n-conductivity type layer to the surface of the silicon dioxide film 6 formed by a vapor phase growth method with a thickness of 0.4 to 1.0 μm, and a thickness of 0.5 μm formed by thermal oxidation.
A contact hole 10 is provided in each silicon dioxide film 6 covering the polysilicon wiring 9 on the second-level silicon film B with a thickness of 1.0 μm. Further, the drain 3 and the gate electrode 5' are connected to the contact holes 7b, 10. Aluminum crystal size 6111. It is electrically connected by polysilicon wiring 9, and the n-conductivity type layer 2. An insulating region that is a complement of the active region 12, 12' (the shaded area in FIG. 1 (&)) forming a band conductor element that combines B, 2', 8' and the gate insulating film 4°4I. 13 has an active region 12°12
The insulating region 13 and the second opposite conductivity type semiconductor layer 14, which is an opposite conductivity type, overlap each other so as not to contact with the insulating region 13. 1st
mTl1 layer 2.2', 3.3' and second n11 layer 1
4 is the active region 12 and the same region 12 at a distance y, y'.
'ga n! so as not to be electrically connected through the first layer 14.
are formed separately.

従つて、第ｔａｌｌ（−のム、Ｄ部の構造紘、従来０Ｍ
０８１１集積回路のものと一致する。第１図（ａ）の１
．０１！の構造が本発明実施例に特有のものであるＯ 第２図（ａ）　−（ｄ）は、夫々、第１図（ａ）Ｋおけ
るアル々ニウム配４１１１のム、Ｂ部、ポリシリコン配
線９の０．Ｄ部の基板１に対する単位面積当りの静電寝
ｔ（以下、容量だけで、単位面積当りの静電容量を表わ
す）の等価回路で参り、各々は気相成長による二階化シ
リコン膜６による容量１５．熱酸化による二酸化シリコ
ン１１８による容量１６゜ｎ型層１４と２Ｍ１基板１と
で形成されるＰｎ接合空乏層による容量１７とで構成さ
れている。尚、ｎ型層１４は、選択酸化法によって基板
に埋設して被着される二酸化シリコン膜８を形成する前
に７オトレジストをマスクとしてリンをイオン注入で所
望の量を注入して形成する。Therefore, the structure of the D part, the conventional 0M
0811 integrated circuit. Figure 1 (a) 1
．． 01! FIGS. 2(a) to 2(d) show the structure of the aluminum wire 4111 in FIG. 1(a) K, the B part, and the polysilicon wiring, respectively. 0 of 9. This is an equivalent circuit of the electrostatic capacity t per unit area (hereinafter, only capacitance refers to capacitance per unit area) with respect to the substrate 1 in part D, each of which is the capacitance due to the two-story silicon film 6 formed by vapor phase growth. 15. It is composed of a capacitance 16° n-type layer 14 made of silicon dioxide 118 formed by thermal oxidation and a capacitance 17 made of a Pn junction depletion layer formed by the 2M1 substrate 1. The n-type layer 14 is formed by ion-implanting a desired amount of phosphorus using a 7-photoresist as a mask before forming the silicon dioxide film 8 buried in the substrate by selective oxidation.

以下、＆９シリコン配線９対基板１間容量について数量
的に本発明の詳細な説明するが、−アル主ニウム配線１
１対基板１間容量についても同様に考えていけばよい。Hereinafter, the present invention will be described in detail quantitatively regarding the capacitance between the &9 silicon wiring 9 and the substrate 1.
The capacitance between one board and one board can be considered in the same way.

二酸化シリコン膜８の膜厚ｔを０．５ａｍ＋ｎ型層１４
．Ｐ基板１のドナー、アクセプタ濃度を、夫々、ＮＤ、
Ｎム（＝１×１０１１１国−”　）　ｌ　ＮＤ　＞＞Ｎ
ムとすれば、空乏層の拡がりは階段接合で十分近似でき
るから、真空の誘電率、゛二酸化シリコンの比誘電率。The thickness t of the silicon dioxide film 8 is 0.5 am + the n-type layer 14
．． The donor and acceptor concentrations of the P substrate 1 are respectively ND,
Nmu (=1×10111 countries-”) l ND >>N
Since the spread of the depletion layer can be sufficiently approximated by a step junction, the dielectric constant of vacuum and the relative dielectric constant of silicon dioxide.

シリコンの比誘電率を夫々、８゜（＝８．８Ｘ１０　　
Ｐ／ｍ）　ｅ　＃　ａｔｏ、　（３，８）ｔ　ａ　ｓｔ
　（−１１−５）とすると、直ちに第１図（ａ）の０．
Ｄ部のポリシリコン配線、対基板間容量Ｏｅ、Ｏｄは次
式より求まる。The dielectric constant of silicon is 8° (=8.8X10
P/m) e #ato, (3,8)t a st
(-11-5), immediately 0.
The capacitances Oe and Od between the polysilicon wiring and the substrate in the D section are determined from the following equations.

Ｏｄ−コ■悲！ を 但しｓ　ｖｎｇφνは夫々、ｎ型層１４の電位％Ｐ基板
１の７エルｔレベルである。今％　ｖＨ−ｏ　ｃＶ：ｌ
。Od-ko ■ Sad! However, each of s vngφν is at the 7 elt level of the potential %P of the n-type layer 14 and the substrate 1 . Now% vH-o cV:l
.

Ｗｉ度ｔｒ　３０　［Ｃ］　トＬテｌｔ算ｔｈｉｆＯ＠
中４．１ｘｌＯ−’［ＰＦ／７１”）、　０ｄ４＝７Ｘ
１０−’（ＰＦ／７１”）、　Ｏ＠１０ｄ４＋０．５９
となり、°特にポリシリコン配線９に電圧が印加された
場合、例えば５〔ｖ〕印加の場合にはｖｎ中２．５〔ｖ
〕テアルカラ０゜ノミＯｃ４：３　Ｘ　１０−’　（１
）Ｆ／７１”）に減少する。したがって、ＣｃＺＯｄ中
０．４３となる。Wi degree tr 30 [C] To L telt calculation thifO@
Medium 4.1xlO-'[PF/71"), 0d4=7X
10-'(PF/71"), O@10d4+0.59
Especially when a voltage is applied to the polysilicon wiring 9, for example, when 5 [V] is applied, 2.5 [V] in vn.
]Thealkara 0゜Flea Oc4:3 X 10-' (1
) F/71”). Therefore, it becomes 0.43 in CcZOd.

先に述べた様に容量Ｏｄは従来の集積回路におけるｌリ
シリコン配線対基板間容量と一致するから本構造Ｏ集積
回路装置の同容量は従来と比較して少なくとも４割減少
していることになり、半導体集積回路装置の高速動作を
可能にすることが分かる。集積度が向上するにつれて選
択酸化法等で絶縁領域に被着させる二酸化シリコン膜８
の膜厚は°活性領域への開展のくい込みを防ぎ、微細パ
ターンを実現する為、またアルミニウム等の配線を微細
化する為にも薄くする必要があり、本発明の効果はより
顕著に現われる。As mentioned earlier, since the capacitance Od matches the capacitance between the silicon wiring and the substrate in the conventional integrated circuit, the same capacitance of the integrated circuit device with this structure is reduced by at least 40% compared to the conventional one. , it can be seen that high-speed operation of the semiconductor integrated circuit device is possible. As the degree of integration increases, a silicon dioxide film 8 is deposited on the insulating region by selective oxidation or the like.
It is necessary to reduce the film thickness in order to prevent the development from penetrating into the active region, to realize fine patterns, and to miniaturize wiring such as aluminum, and the effects of the present invention will be more pronounced.

なお、本実施例でａｄｏｓ型集積画集積回路装置したが
、相補型絶縁ゲート電界効果半導体集積回路装置、バイ
ポーラ型集積回路装置等にも同様に適用できることはい
うまでも表い。Although this embodiment uses an ADOS type integrated circuit device, it goes without saying that the present invention can be similarly applied to complementary type insulated gate field effect semiconductor integrated circuit devices, bipolar type integrated circuit devices, and the like.

以上、説明した様に本発明は半導体集積回路装置、特に
モノリシック集積回路装置におけるアルミニウム配線、
ポリシリコン配線等の対基板間静電容量を大幅に減少さ
せる為に、集積回路装置の高速動作に寄与するものであ
る。As explained above, the present invention relates to aluminum wiring in a semiconductor integrated circuit device, particularly in a monolithic integrated circuit device.
This contributes to high-speed operation of integrated circuit devices because it significantly reduces capacitance between substrates such as polysilicon wiring.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）、　（ｂ）は、夫々、本発明をＭＯａ型集
型口積回路装置用した実施例の平面図と、そのＸ−Ｘ／
での断面図、第２図（ａ）〜（ｄ）は第１図（ｓ＋）に
おける配線のム、Ｂ、０．Ｄ各部における単位面積当り
の対基板間静電容量の等価回路、である◇なお図におい
て、１・・・・・・Ｐ型単結晶基板、２゜２’　、３．
３’・・・・・・第一のｎ導電型層、４，４’・・・・
・・ゲート絶縁膜、５．５’・・・・・・多結晶シリコ
ンゲート電極、６，８・・・・・・二酸化シリコン膜、
７ｍ＃７ｄ、１０・・・・・・コンタクＦ１９・・・・
・ψ多結晶シリコン配線、１１・・・・・・アルミニウ
ム配線、１２゜１２’・・・・：・活性領域、１３・・
・・・・絶縁領域％１４・・・用第２Ｏｎ導電型層、１
５・・・・・・二酸化シリコン膜６の静電容量、１６°
°°°°°二酸化シリコン８の静電容量、１７・・・・
・・第２のｎ導電型層１４と基板ｌとのｐｍ接合、であ
る。FIGS. 1(a) and 1(b) are respectively a plan view of an embodiment in which the present invention is applied to an MOa type integrated integrated circuit device, and its X-X/
The cross-sectional views in FIGS. 2(a) to 2(d) show the wiring patterns, B, 0. D: Equivalent circuit of capacitance to substrate per unit area at each part ◇In the figure, 1... P-type single crystal substrate, 2°2', 3.
3'...first n conductivity type layer, 4,4'...
...Gate insulating film, 5.5'...Polycrystalline silicon gate electrode, 6,8...Silicon dioxide film,
7m #7d, 10...Contact F19...
・ψ polycrystalline silicon wiring, 11... Aluminum wiring, 12° 12'...: Active region, 13...
... second On conductivity type layer for insulation region %14, 1
5...Capacitance of silicon dioxide film 6, 16°
°°°°°Capacitance of silicon dioxide 8, 17...
. . . a pm junction between the second n-conductivity type layer 14 and the substrate l.

Claims (1)

【特許請求の範囲】[Claims] 一導電型牛導体基板に複数の素子領域が設けられ、紋複
歌の素子領域間のフィールド領域に絶縁膜が設けられ、
該絶縁膜上を延在する配線層が設けられた半導体集積回
路装置において、前記配線層下の前記フィールド領域に
逆導電型領域が設けられていることを特徴とする半導体
集積回路装置。A plurality of element regions are provided on a conductive substrate of one conductivity type, and an insulating film is provided in a field region between the element regions of the single conductivity type.
A semiconductor integrated circuit device including a wiring layer extending over the insulating film, wherein an opposite conductivity type region is provided in the field region under the wiring layer.