JPS5893328A - Method of flattening insulating layer - Google Patents
Method of flattening insulating layerInfo
- Publication number
- JPS5893328A JPS5893328A JP19223681A JP19223681A JPS5893328A JP S5893328 A JPS5893328 A JP S5893328A JP 19223681 A JP19223681 A JP 19223681A JP 19223681 A JP19223681 A JP 19223681A JP S5893328 A JPS5893328 A JP S5893328A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- film
- etching
- silicon oxide
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 33
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000001020 plasma etching Methods 0.000 claims abstract description 14
- 239000007789 gas Substances 0.000 claims description 16
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 1
- ZMZDMBWJUHKJPS-UHFFFAOYSA-M Thiocyanate anion Chemical compound [S-]C#N ZMZDMBWJUHKJPS-UHFFFAOYSA-M 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 17
- 239000000758 substrate Substances 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 74
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 37
- 229910052814 silicon oxide Inorganic materials 0.000 description 37
- 239000004065 semiconductor Substances 0.000 description 10
- 239000004020 conductor Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000009499 grossing Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- IYLGZMTXKJYONK-ACLXAEORSA-N (12s,15r)-15-hydroxy-11,16-dioxo-15,20-dihydrosenecionan-12-yl acetate Chemical compound O1C(=O)[C@](CC)(O)C[C@@H](C)[C@](C)(OC(C)=O)C(=O)OCC2=CCN3[C@H]2[C@H]1CC3 IYLGZMTXKJYONK-ACLXAEORSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 150000001282 organosilanes Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- IYLGZMTXKJYONK-UHFFFAOYSA-N ruwenine Natural products O1C(=O)C(CC)(O)CC(C)C(C)(OC(C)=O)C(=O)OCC2=CCN3C2C1CC3 IYLGZMTXKJYONK-UHFFFAOYSA-N 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、凹凸を有する下地表面に形成された絶縁層を
平坦化する方法に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for planarizing an insulating layer formed on an uneven underlying surface.
発明の技術的背景とその問題点
半導体集積回路の如き小形電子装置を製作する場合、絶
縁層と導体層とを順次形成すると共に写真蝕刻法により
上記絶縁層および導体層を所定のノ臂ターンに加工す゛
るため、いくつかの膜層の厚さになぞらえた高さ変化が
生ずる。この高さ変化拡、装置表面に非常に大きな段差
を生じさせ、ときにはオーパーツＸノブした縁となるこ
ともある。そして、このような段差がある表面上に導体
層、例えばアルミニウム膜を真空蒸着等の手段で付着さ
せた場合、アルミニウム膜が段差の側面で薄くなったシ
、段差が急峻で微細なホール状になつそいるところでは
全く付着しない状態となり、導体層の断線が生じ、製品
の歩留りを悪くする他、製品使用時の故障率を高めるこ
とにもなる。Technical background of the invention and its problems When manufacturing a small electronic device such as a semiconductor integrated circuit, an insulating layer and a conductive layer are sequentially formed, and the insulating layer and conductive layer are formed into predetermined turns using photolithography. Due to the processing, height changes occur that are similar to the thickness of several film layers. This height change can result in very large steps on the surface of the device, sometimes resulting in rough edges. When a conductive layer, such as an aluminum film, is deposited on a surface with such a step by means such as vacuum evaporation, the aluminum film becomes thinner on the sides of the step, and the step becomes steep and forms a fine hole. In some areas, it will not adhere at all, causing disconnection of the conductor layer, which will not only reduce the yield of the product, but also increase the failure rate during product use.
従来、上述した導体層の断線を防止するために、導体層
を形成する前の絶縁膜表面をなだらかにする方法として
、例えば５ｉｎ２に燐を含ませたガラス層を１０００
（’Ｃ）以上の加熱処理によって塑性流動させる所謂ガ
ラスフロー法やオルガノシラン等の有機系物質を塗布し
て焼結する所開倭布法等が知られている。Conventionally, in order to prevent the above-mentioned disconnection of the conductor layer, as a method of smoothing the surface of the insulating film before forming the conductor layer, for example, a 5 in 2 glass layer containing phosphorus was coated with 1000
('C) Known methods include the so-called glass flow method in which the material is plastically fluidized by the above heat treatment, and the open cloth method in which an organic material such as organosilane is coated and sintered.
しかし、。前記がラスフロー法では高温処理が心安なた
めに導体層として低融点金属、例えばアルミニウムが形
成され死後にさらに導体層を設けるための相互間の絶縁
膜には適用できず、また半導体基板内に予め導入されて
いる不純物、例、えば燐、砒素、硼素等がガラス７０−
の高温処理過程で再分布するため半導体装置の高密度化
および高速化に限界がある等の欠点がある。but,. In the last flow method, a low-melting point metal such as aluminum is formed as a conductor layer because high-temperature processing is safe, and it cannot be applied to an insulating film between layers to provide a conductor layer after death. Introduced impurities such as phosphorus, arsenic, boron, etc.
Because of the redistribution during the high-temperature treatment process, there are drawbacks such as limitations in increasing the density and speed of semiconductor devices.
一方、前記塗布法では緻密な絶縁膜を得るのが回磁なた
め吸湿性が大き七、また−ンホールが多い等のためアル
ミニウムの導体層が腐蝕したり、配線相互間にリーク電
流が生じたりする欠点がある。On the other hand, with the above coating method, a dense insulating film is obtained by rotating the magnet, which has high hygroscopicity, and also has many holes, which can lead to corrosion of the aluminum conductor layer and leakage current between wiring lines. There are drawbacks to doing so.
また９集積回路における横方向の誘電体分離を形成する
ために被着絶縁層を使用することは、被着絶縁層を平坦
化して、基板の凸領域上の絶縁層を凹領域に被着された
絶縁層と共平面にする効果的方法がないために非常に制
限されている。このような誘電体分離集積回路の製造に
おいては半導体基板にお対る複数個のポケット領域を分
離するための溝が基板表面に形成される。9 The use of deposited insulating layers to form lateral dielectric isolation in integrated circuits also allows the deposited insulating layer to be planarized and the insulating layer on convex areas of the substrate to be deposited in the concave areas. is severely limited by the lack of an effective method to make it coplanar with the insulating layer. In manufacturing such dielectrically isolated integrated circuits, grooves are formed on the surface of the semiconductor substrate to separate a plurality of pocket regions on the semiconductor substrate.
そして、この溝に誘電体を満たすために用いられる従来
の選択酸化法によればバードビークやバードヘッドとよ
ばれる前記溝の・ヤターンに対応する大きな起伏が生じ
るという欠点がある。The conventional selective oxidation method used to fill the grooves with dielectric material has the disadvantage that large undulations corresponding to the grooves, called bird's beaks and bird's heads, occur.
このような問題を解決するものとして本発明者等線、反
応性イ芽ンエッチング法を利用した絶縁層の平坦化方法
を先に提案した（特願昭５５−１３０７５４号、特願昭
５５−１５０１７９号）。これらの提案は、凹凸を有す
る下地表面に窒化シリコン膜を形成し、例えばＣＦ４と
Ｈ２との混合ガスを用いた反応性イオンエツチング法に
ょシ前記会化シリコン膜表面をエツチング除去すること
によシ窒化シリコン膜表面を平坦にする方法である。ま
た、窒化シリコン膜以外の絶縁膜、例えば酸化シリコン
膜上に窒化シリコン膜を積層した後、前述したと同様な
方法、即ち、ＣＦ４とＨ２ガスを用いた反応性イオンエ
ツチング法で窒化シリコン膜と酸化シリコン膜のエツチ
ング速度がｔヨホ等しくなるエツチング条件下で窒化シ
リコン膜および酸化シリコン膜の表面をエツチング除去
するととＫよ）酸化シリコン膜表面をｆ坦にする方法で
ある。In order to solve this problem, the present inventors previously proposed a method for planarizing an insulating layer using isoline, reactive etching (Japanese Patent Application No. 130754/1983, No. 150179). These proposals involve forming a silicon nitride film on an uneven base surface and etching the surface of the silicon nitride film using, for example, a reactive ion etching method using a mixed gas of CF4 and H2. This is a method for flattening the surface of a silicon nitride film. In addition, after laminating a silicon nitride film on an insulating film other than a silicon nitride film, for example, a silicon oxide film, the silicon nitride film is etched using the same method as described above, that is, a reactive ion etching method using CF4 and H2 gas. In this method, the surfaces of the silicon nitride film and the silicon oxide film are etched away under etching conditions such that the etching rate of the silicon oxide film is equal to t, and the surface of the silicon oxide film is flattened.
しかしながら、酸化シリコン膜表面を平坦にする先の発
明方法にあっては、エツチングの進行とともに酸化シリ
コン膜に比べて窒化シリコン膜のエツチング速度が遅く
な壽、および酸化シリコン膜上に形成した窒化シリコン
膜の厚さが凸部および凹部底面に比べて凹部気量で下地
膜差分だけ厚くなることによって、°酸化シリコン膜表
面に凹凸が生じると云う問題があった。However, in the method of the invention for flattening the surface of a silicon oxide film, as the etching progresses, the etching rate of the silicon nitride film is slower than that of the silicon oxide film, and the silicon nitride film formed on the silicon oxide film There is a problem in that unevenness occurs on the surface of the silicon oxide film because the thickness of the film becomes thicker by the amount of base film difference due to the amount of air in the recesses compared to the bottom surfaces of the convex parts and the recessed parts.
例えば第１図（、）に示すごとく半導体基板１上に絶縁
膜２を介して厚さ１〔μｍ〕の第１のアル１＝ウム配線
ノ母ターン３を反応性イオンエツチング法で形成した段
差上に酸化シリコン膜４を形成し次いで酸化シリコン膜
４上に窒化シリコン膜５を積層する。次いでＣＦ４とＨ
ｌとの混合ガスを用いた反応性イオンエツチング法で窒
化シリコンｊＩ５および酸化シリコン膜４の表面を除去
した場合第１図（ｂ）に示すような凹凸が酸化シリコン
膜４表面に残存する。そして、この酸化シリコン膜４表
面に、例えば第２のアルミニレム配線ノ豐ターンを形成
した場合酸化シリコン膜４表面の凹部にアルミニウムが
残シ配線間のシｍ −ト不良をひきおこしたシ、またア
ルミニウムの被覆性が不充分なために完全に平坦な酸化
シリコン膜上にｉ成したアルミニウム配線の通電寿命ニ
比べて１０〜５０（ト）程度短かい等の問題があった。For example, as shown in FIG. 1(a), a step is formed by forming a first aluminum wiring mother turn 3 with a thickness of 1 [μm] on a semiconductor substrate 1 via an insulating film 2 by a reactive ion etching method. A silicon oxide film 4 is formed thereon, and then a silicon nitride film 5 is laminated on the silicon oxide film 4. Then CF4 and H
When the silicon nitride jI5 and the surface of the silicon oxide film 4 are removed by a reactive ion etching method using a mixed gas with l, unevenness as shown in FIG. 1(b) remains on the surface of the silicon oxide film 4. If, for example, a second aluminum layer wiring pattern is formed on the surface of this silicon oxide film 4, aluminum may remain in the recesses on the surface of the silicon oxide film 4, causing a defect in the wiring between the wirings. Due to the insufficient coverage of the silicon oxide film, there were problems such as the current lifespan being about 10 to 50 (t) shorter than that of aluminum wiring formed on a completely flat silicon oxide film.
この様な配線の信頼性の低下は下地段差が接近する程顕
著にな〕半導体集積回路の黴細化を阻害していた。This deterioration in wiring reliability becomes more pronounced as the underlying steps get closer together, and has hindered the growth of mold in semiconductor integrated circuits.
発明の目的
本発明は上記事情を考慮して表されたもので、その目的
とするところは、凹凸を有する下地表面上に平坦な絶縁
層を形成することのできる絶縁層の平坦化方法を提供す
ることＫある。Purpose of the Invention The present invention was developed in consideration of the above circumstances, and its purpose is to provide a method for planarizing an insulating layer that can form a flat insulating layer on an uneven underlying surface. There's K things to do.
発明の概要
本発明は、凹凸を有する下地表面に窒化シリコン以外の
第１の絶縁層を形成したのち、反応性イオンエツチング
法を用いて上記第１の絶縁層の表面をエツチングし該絶
縁層の段差をなだらかにし、次いで、上記第１の絶縁層
上に窒化シリコンを主成分とする第２の絶縁層を形成し
、しかるのち、上記第２の絶縁層の凹領域のエツチング
速度が凸領域のエツチング速度よシ遅い反応性イオンエ
ツチング法を用いて上記ｆｓ２の絶縁層および前記第１
の絶縁層の表面をエツチングするようにした方法である
・
発明の効果
本発明によれば、最初のエツチングによシ第１の絶縁層
の段差をなだらかＫしているので、第２の絶縁層の膜厚
が上記段差細面上で極端に厚くなることを防止すること
ができる。したがって、次のエツチングにより第１の絶
縁層の表面に凹凸を残すことなく第１の絶縁層表面を確
実に平坦化することができる。また、高温処理を必要と
せず、低温処理のみで夾現し得るので、半導体装置の高
密度化および高速化にも有効である。Summary of the Invention The present invention involves forming a first insulating layer other than silicon nitride on an uneven base surface, and then etching the surface of the first insulating layer using a reactive ion etching method. After smoothing the step, a second insulating layer containing silicon nitride as a main component is formed on the first insulating layer, and then the etching rate of the concave areas of the second insulating layer is equal to that of the convex areas. The fs2 insulating layer and the first
Effects of the Invention According to the present invention, since the step of the first insulating layer is made gentle by the first etching, the surface of the second insulating layer is etched. It is possible to prevent the film thickness from becoming extremely thick on the stepped narrow surface. Therefore, the surface of the first insulating layer can be reliably flattened by the next etching without leaving any unevenness on the surface of the first insulating layer. Furthermore, since high-temperature processing is not required and the formation can be achieved only by low-temperature processing, it is effective for increasing the density and speed of semiconductor devices.
発明の実施例 以下、本発明の詳細を図示の実施例によって説明する。Examples of the invention Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第２図（、）〜（・）は本発明を２層構造の配線形成に
適用した一実施例を示す断面図である。まず、第２図（
ａ） Ｋ示す如く能動素子や受動素子が形成された、例
えばシリコン基板１１上に絶縁膜１２を被着し死後必゛
要な接続孔を開けて、この孔も含め前記絶縁ｊｌＪＪ上
にアルミニウム膜１３をスノ臂ツタ法あるいは電子ビー
ム蒸着法により被着し、その／臂ターニングヲｃ ｃｔ
４トｃｔ２との混合ガスを用いた反応性イオンエツチン
グ法等によ）行なった下地上に第１の絶縁層として、例
えば８１Ｈ４とＮ２０ガスを用いてグロー放電を応用し
たプラズマ気相成長法によシ酸化シリコン膜１４を形成
した。アルミニウム配線ツヤターンは実際にはその配線
巾および配線間隔が異なるものが画一的に多数形成され
能動素子や受動素子の相互を接続して集積回路を構成し
ている。第２図（、）にはアルミニウム膜厚を約１〔μ
ｍ〕アルミニウム配線層の巾を約２ （＃１１１）、隣
接するアルミニウム配線層の間隔を約２〔＾ｍ〕として
酸化シリコン膜１４を約１〔μｍ〕被着した場合の断面
形状を示した。酸化シリコン膜１４の厚さは最終的に平
坦な表面形状を得るために、下地段差の少くとも半分以
上にすることが望ましい。FIGS. 2(,) to 2(·) are cross-sectional views showing an embodiment in which the present invention is applied to forming wiring in a two-layer structure. First, Figure 2 (
a) As shown in K, an insulating film 12 is deposited on, for example, a silicon substrate 11 on which active elements and passive elements are formed, and after death, the necessary connection holes are made, and an aluminum film is formed on the insulating film including these holes. No. 13 is deposited by the snow ivy method or the electron beam evaporation method, and the /arm turning is performed.
For example, as a first insulating layer on the underlayer formed by reactive ion etching using a mixed gas of 81H4 and N20 (reactive ion etching method using a mixed gas of 81H4 and N20), for example, a plasma vapor phase epitaxy method applying glow discharge using 81H4 and N20 gas is applied. A silicon oxide film 14 was formed. Actually, a large number of aluminum wiring gloss turns are uniformly formed with different wiring widths and wiring intervals, and active elements and passive elements are connected to each other to form an integrated circuit. Figure 2 (,) shows the aluminum film thickness of approximately 1 [μ
m] The cross-sectional shape is shown when the width of the aluminum wiring layer is approximately 2 (#111), the interval between adjacent aluminum wiring layers is approximately 2 [^m], and the silicon oxide film 14 is deposited approximately 1 [μm]. . The thickness of the silicon oxide film 14 is desirably at least half the thickness of the underlying step in order to ultimately obtain a flat surface shape.
次に第２図（ｂ）に示す如く、前記酸化シリコン換１４
０表面をＣ，Ｆ、とＮ２との混合ガスを用いた反応性イ
オンエツチング法でエツチング除去する。エツチング除
去後、残存せしめた酸化シーリコン８１４の段差部側面
はチー／ｌ−状となる。Next, as shown in FIG. 2(b), the silicon oxide conversion 14
The 0 surface is etched away by reactive ion etching using a mixed gas of C, F, and N2. After etching is removed, the side surface of the stepped portion of the remaining oxidized silicone 814 becomes chi/l-shaped.
このターンや一角はＮ２が多い程小さくなる。このエツ
チング現象は新しい実験事実に基づくものであり、異方
性のドライエツチング法において陰極降下電圧によりグ
ロー放電中から引出されたイオン種が酸化シリコン族に
対して斜めに衡突する鵬エツチングの進行を阻害するＣ
−Ｆ／リマ−が付着しにくいためと考えられる。事実Ｃ
，Ｆ、 Ｋ対してＮ２添加量を５０（２）以上にした場
合酸化シリコン膜の段差縁部を除いて凹部底面および凸
部にＣ−Ｆ／９マーの付着が観察された。The more N2 there is, the smaller this turn or corner will be. This etching phenomenon is based on a new experimental fact, and is the progress of etching in which ion species extracted from the glow discharge by the cathode drop voltage obliquely balance against the silicon oxide group in the anisotropic dry etching method. C inhibits
This is thought to be because -F/rimer is difficult to adhere to. Fact C
, F, and K, when the amount of N2 added was 50(2) or more, adhesion of C-F/9mer was observed on the bottom surfaces of the recesses and on the convex parts except for the step edges of the silicon oxide film.
尚、本実施例でのエツチングは平行平板型の装置を用い
高周波電力印加側に試料をおき、高周波電力ｔ ｏ ｏ
（ｗ）、圧力１．３３ （Ｐａ）、Ｃ，Ｆ６流量２４
〔Ｃシー、〕でＨ２流量を２〜１２〔６シー、〕で行な
った。上記エツチング条件においてＣ，Ｆ、 、ｌ！／
スに対してＮ２ｆスを２０ Ｃ９６′）以上添加した場
合酸化シリコン膜１４の段差部側間のテーノ譬−角紘約
４５（”）になる。このテーノ中−エッチング効果はＮ
２添加量が１０（２）以上から顕著にみられる。また、
−添加量を５０Ｃ％３以上にした場合には酸化シリコン
膜１４表面の一部にＣ−Ｆ４！リマーが付着するが、こ
のＣ−Ｆポリマ一層は０２ガスのプラズマ雰囲気にさら
すことによって除去することができる。In the etching in this example, a parallel plate type device was used, the sample was placed on the high frequency power application side, and the high frequency power to
(w), pressure 1.33 (Pa), C, F6 flow rate 24
The H2 flow rate was set at 2 to 12 [6 C]. Under the above etching conditions, C, F, , l! /
When more than 20 C96') of N2f gas is added to the silicon oxide film 14, the etching effect between the stepped portions of the silicon oxide film 14 becomes approximately 45 ('').
This is noticeable when the amount of 2 added is 10(2) or more. Also,
- When the amount of addition is 50C%3 or more, C-F4! Although remer is deposited, this C-F polymer layer can be removed by exposure to a plasma atmosphere of 02 gas.
次に、第２図（ｃ）に示す如く前記酸化シリコン膜１４
上に窒化シリコン膜１５を例えばＳｉＨ４とＮＨ３ガス
とを用いてプラズマ気相成長法によシ０．３〔μｍ〕以
上の厚さ形成する。この窒化シリコン膜の厚さが薄い場
合、最終工程での酸化シリコン膜表面の平坦性が悪くな
る。続いてＣＦ４とＨ２／／スを用いた反応性イオンエ
ツチング法により窒化シリコン膜１５の凹部のエツチン
グ速度が凸部に比べて遅く、かつ凸部での窒化シリコン
膜１５と酸化シリコン膜１４のエツチング速度かはぼ等
しい条件、例えばＣＦ４にＨ２を２５Ｃ＠添加し高周波
電力ｉ ｓ ｏ （ｗ）、圧力１．３３ （Ｐａ） 腑
なうことによシ酸化シリコン、膜１４の表面は第２図（
ｄ）に示す如くなだらかな状態となる。酸化シリコン膜
１４のなだらかな表面は、前記第ψ図（ｂ）に示した工
程で述べた窒化シリコン膜１５を形成する前に酸化シリ
コン膜１４の段差部側面を約７０〔つ以下にすることに
よシ得られた。 。Next, as shown in FIG. 2(c), the silicon oxide film 14
A silicon nitride film 15 is formed thereon to a thickness of 0.3 [μm] or more using, for example, SiH4 and NH3 gas by plasma vapor deposition. If this silicon nitride film is thin, the surface flatness of the silicon oxide film in the final step will be poor. Subsequently, a reactive ion etching method using CF4 and H2 was used to ensure that the etching rate of the concave portions of the silicon nitride film 15 was slower than that of the convex portions, and that the silicon nitride film 15 and silicon oxide film 14 were etched at the convex portions. Under conditions where the speed is approximately equal, for example, 25C@ of H2 is added to CF4, high frequency power is o (w), pressure is 1.33 (Pa), the surface of the silicon oxide film 14 is as shown in Fig. 2. (
It becomes a gentle state as shown in d). The smooth surface of the silicon oxide film 14 is obtained by making the side surface of the stepped portion of the silicon oxide film 14 less than about 70 degrees before forming the silicon nitride film 15 described in the step shown in FIG. ψ (b). I got it very well. .
このようにして表面を平坦にした酸化シリコン膜１４上
に第２図（・）に示す如く絶縁膜１＃を被着した後、写
真蝕刻法によシ所定領域に層間接続用の開孔部を形成し
、その後第２導体層として例えばアルミニウム配線／臂
ターフ１１を形成した。かくして得られた第２導体層１
１の配線特性を調べた結果、隣接する配線間のシ璽−ト
不良は皆無であシ、また配線の通電寿命も完全に平坦な
酸化シリコン膜上に形成した配線と同等の寿命が得られ
半導体装置の信頼性が大巾に改善されることが判った。After depositing the insulating film 1# on the silicon oxide film 14 whose surface has been flattened in this manner as shown in FIG. was formed, and then, for example, an aluminum wiring/arm turf 11 was formed as a second conductor layer. Second conductor layer 1 thus obtained
As a result of investigating the wiring characteristics of No. 1, there were no sheet defects between adjacent wirings, and the wiring life when conducting electricity was equivalent to that of wiring formed on a completely flat silicon oxide film. It has been found that the reliability of semiconductor devices is greatly improved.
第３図（、）〜（ｄ）は本発明を素子間分離工程に適用
した他の実施例を示す断面図である。まず、第３図（、
）に示す如く誘電体分離用の溝がパターニングされた基
板２１１の上に酸化シリコン膜２２を形成する。なお−
これ以降の第３図（ｂ）〜（ｄ）に示す工程は先の実施
例で述べたと同様な方法で行なった。また、本実施例で
は基板２１に・９ターニングされた溝の深さを約１〔声
ｍ〕、巾を２〔μｍ〕とした。図中２３は窒化シリコン
膜である。FIGS. 3(a) to 3(d) are cross-sectional views showing another embodiment in which the present invention is applied to an element isolation process. First, Figure 3 (,
), a silicon oxide film 22 is formed on a substrate 211 patterned with grooves for dielectric isolation. Note-
The subsequent steps shown in FIGS. 3(b) to 3(d) were carried out in the same manner as described in the previous example. In addition, in this embodiment, the depth of the groove formed by nine turns on the substrate 21 was approximately 1 [meter], and the width was approximately 2 [μm]. In the figure, 23 is a silicon nitride film.
かくして本実施例方法によれば、誘電体を低温工程だけ
で分離用の溝に完全に埋め込みその表面を平坦にでき、
従来の選択酸化法の隣に化シルバードピーク、ノ々−ド
ヘッドによる素子領域の寸法誤差がなくな〕これを０．
１〔μｍ〕以下に抑えることができ、かつ高集積化が可
能となった。さらに、高温長時間熱処理工程が不要にな
りへためフィールド領域の不純物の再分布によるしみ出
しがなくな）、これによ多素子特性の低下はほとんどみ
られなくなり高集積化も可能になった。しかも、絶縁膜
を完全にフィールド領域に埋め込む事が可能になシ、フ
ィールド領域周辺での段差は、０．１ （＃１１１）以
下に抑えることができる。こ９丸め、段差部で金属配線
が薄くなったり切断されたシする現象がなくなシ、配線
の信頼性が著しく向上し製品の歩留シが向上した。また
、本発明による素子間分離はＭＯＳ型およびバイポーラ
型半導体装置に適用できることは勿論である。Thus, according to the method of this embodiment, the dielectric can be completely buried in the isolation groove using only a low-temperature process, and its surface can be flattened.
Next to the conventional selective oxidation method, there is no dimensional error in the device area due to silvered peaks and node heads.
It was possible to suppress the thickness to 1 [μm] or less, and it became possible to achieve high integration. Furthermore, since a high-temperature, long-time heat treatment process is no longer necessary, there is no seepage due to redistribution of impurities in the field region), and as a result, there is almost no deterioration in multi-element characteristics, making it possible to achieve high integration. Moreover, it is possible to completely bury the insulating film in the field region, and the height difference around the field region can be suppressed to 0.1 (#111) or less. This eliminates the phenomenon of metal wiring becoming thin or being cut at stepped portions, significantly improving the reliability of the wiring and improving product yield. Furthermore, it goes without saying that the element isolation according to the present invention can be applied to MOS type and bipolar type semiconductor devices.
なお、本発明は上述した各実施例に限定されるものでは
ない。前記各実施例では本発明を第一導体層の上に被着
し九絶縁層に適用、或いは導体層を形成する以前の絶縁
層に適用した例について述べたが本発明は半導体装置の
製造工１で生ずる。すべての凹凸に適用することができ
る。Note that the present invention is not limited to the embodiments described above. In each of the above embodiments, the present invention is applied to a first conductive layer and applied to an insulating layer, or an insulating layer before a conductive layer is formed. Occurs at 1. Can be applied to all uneven surfaces.
また第１の絶縁層の段差部側面をなだらかにするエツチ
ング方法および第２の絶縁層の凹領域のエツチング速度
が凸領域のエツチング速度に比べて小さいエツチング方
法として、 Ｃ，Ｆ、 とＨ２およびＣＦ４とＨ２ガ
スを用いた場合について説明したが、この他０２Ｆ、
、 ＣＦ、Ｂｒ等のガスを用いることが出来、また水素
をＨ２の形で加える代わシにＣＨＦ、ガスを用いて４良
い、さらに、館１の絶縁層の段差部側面をなだらかにす
るエツチング処理方法として、第１の絶縁層上にレジス
ト、オルガノシリケートガラス等の有機膜を塗布し前記
第１の絶縁層と有機膜のエツチング速度がｉｆぼ等しく
なる反応性イオンエツチング条件下で有機膜および第１
の絶縁層表面をエツチング除去しても良い。また、第１
の絶縁層としてノラズマ気相成長法による酸化シリコン
膜を用いたが、常圧あるいは減圧下に保った反応室にお
いて熱分解法によシ生成した酸化シリコン換、スノや！
夕法で生成した酸化シリコン膜を用いて龜良く、また酸
化シリコ・ン膜に燐等を添加したいわゆるシリケートガ
ラス膜を用いても良い。その他、本発明の要旨を逸脱し
ない範囲で、種々変形して実施することができる。Further, as an etching method for smoothing the side surface of the stepped portion of the first insulating layer and an etching method for etching the concave areas of the second insulating layer at a lower etching rate than the etching rate for the convex areas, C, F, H2 and CF4 are used. Although we have explained the case using H2 gas, in addition to 02F,
, CF, Br, and other gases can be used, and CHF gas can be used instead of adding hydrogen in the form of H2.Furthermore, etching treatment can be performed to smooth the side surface of the stepped portion of the insulating layer of Building 1. As a method, an organic film such as resist or organosilicate glass is coated on the first insulating layer, and the organic film and the organic film are etched under reactive ion etching conditions such that the etching rate of the first insulating layer and the organic film are approximately equal if. 1
The surface of the insulating layer may be removed by etching. Also, the first
A silicon oxide film produced by the Norasma vapor phase epitaxy method was used as the insulating layer, but the silicon oxide film produced by the thermal decomposition method in a reaction chamber maintained at normal pressure or reduced pressure was used as an insulating layer.
It is possible to use a silicon oxide film produced by the drying method, or to use a so-called silicate glass film in which phosphorus or the like is added to a silicon oxide film. In addition, various modifications can be made without departing from the gist of the present invention.
第１図（、）〜（ｂ）は従来の絶縁層平坦化工程を示す
断面図、第２図（、）〜（・）は本発明を２層構造の配
線形成工程に適用した一実施例を示す断面図、第３図（
、）〜（ｄ）は本発明を素子間分離工程に適用した他の
実施例を示す断面図である。
１．１１．２１・・・半導体基板、２，１２ ・絶縁層
、３．１３．７７・・・アルミニウ〜ム薄膜、４゜１４
．２２・・・酸化シリコン膜（第１の絶縁層）、層）。
出願人代理人 弁理士 鈴 江 武 彦：：
第１図
第２図
４
第２図Figures 1 (,) to (b) are cross-sectional views showing a conventional insulating layer planarization process, and Figures 2 (,) to (•) are an embodiment in which the present invention is applied to a two-layer interconnection formation process. A cross-sectional view showing the
, ) to (d) are cross-sectional views showing other embodiments in which the present invention is applied to an element isolation process. 1.11.21... Semiconductor substrate, 2,12 - Insulating layer, 3.13.77... Aluminum thin film, 4゜14
．． 22...Silicon oxide film (first insulating layer). Applicant's representative Patent attorney Takehiko Suzue: Figure 1 Figure 2 Figure 4 Figure 2
Claims (3)
の絶縁層を形成する工程と、反応性イオンエツチング法
を用いて上記第１の絶縁層の表面をエツチングし該絶縁
層の段差をなだらかにする工程と、上記エツチングされ
た第１の絶縁層上の窒化シリコンを主成分とする第２の
絶縁層を形成する工程と、上記第２の絶縁層の凹領域の
エツチング速度が凸領域のエツチング速度より遅い反応
性イオンエツチング法を用いて上６１第２の絶縁層およ
び前記第１の絶縁層の表面をエツチングする工程とを具
備したことを特徴とする絶縁層の平坦化方法。(1) A first material other than silicon nitride on the uneven base surface
forming an insulating layer on the etched first insulating layer; etching the surface of the first insulating layer using a reactive ion etching method to smoothen the steps of the first insulating layer; forming a second insulating layer mainly composed of silicon nitride; and using a reactive ion etching method in which the etching rate of the concave areas of the second insulating layer is slower than the etching rate of the convex areas. 1. A method for planarizing an insulating layer, comprising the step of etching surfaces of a second insulating layer and the first insulating layer.
際し、水素を含む炭素のノ・ロダン化物を反応性ガスと
して用いたことを特徴とする特許請求の範囲第１項記載
の絶縁層の平坦化方法。(2) A method for planarizing an insulating layer according to claim 1, characterized in that, when using each of the reactive ion etching methods, a rhodanide of carbon containing hydrogen is used as a reactive gas. .
ガスを用いたことを特徴とする特許請求の範囲第２項記
載の絶縁層の平坦化方法。(3) The method for planarizing an insulating layer according to claim 2, wherein a mixed gas of C, F, and H2 is used as the reactive gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19223681A JPS5893328A (en) | 1981-11-30 | 1981-11-30 | Method of flattening insulating layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19223681A JPS5893328A (en) | 1981-11-30 | 1981-11-30 | Method of flattening insulating layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5893328A true JPS5893328A (en) | 1983-06-03 |
Family
ID=16287911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19223681A Pending JPS5893328A (en) | 1981-11-30 | 1981-11-30 | Method of flattening insulating layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893328A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60121795A (en) * | 1983-12-06 | 1985-06-29 | 東京応化工業株式会社 | Method of producing multilayer circuit board |
| JPS60217644A (en) * | 1984-04-12 | 1985-10-31 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS61144849A (en) * | 1984-12-19 | 1986-07-02 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPS61501738A (en) * | 1984-04-04 | 1986-08-14 | アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド | Double planarization method for multilayer metallization of integrated circuit structures |
| EP0441653A2 (en) * | 1990-02-09 | 1991-08-14 | Applied Materials, Inc. | Improvements in process for planarizing an integrated circuit structure using low melting inorganic material |
-
1981
- 1981-11-30 JP JP19223681A patent/JPS5893328A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60121795A (en) * | 1983-12-06 | 1985-06-29 | 東京応化工業株式会社 | Method of producing multilayer circuit board |
| JPH0534839B2 (en) * | 1983-12-06 | 1993-05-25 | Tokyo Ohka Kogyo Co Ltd | |
| JPS61501738A (en) * | 1984-04-04 | 1986-08-14 | アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド | Double planarization method for multilayer metallization of integrated circuit structures |
| JPS60217644A (en) * | 1984-04-12 | 1985-10-31 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS61144849A (en) * | 1984-12-19 | 1986-07-02 | Seiko Epson Corp | Manufacture of semiconductor device |
| EP0441653A2 (en) * | 1990-02-09 | 1991-08-14 | Applied Materials, Inc. | Improvements in process for planarizing an integrated circuit structure using low melting inorganic material |
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