JPS5887634A - Processing sequential managing system - Google Patents
Processing sequential managing systemInfo
- Publication number
- JPS5887634A JPS5887634A JP56186511A JP18651181A JPS5887634A JP S5887634 A JPS5887634 A JP S5887634A JP 56186511 A JP56186511 A JP 56186511A JP 18651181 A JP18651181 A JP 18651181A JP S5887634 A JPS5887634 A JP S5887634A
- Authority
- JP
- Japan
- Prior art keywords
- address
- program
- task
- control block
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W99/00—Subject matter not provided for in other groups of this subclass
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はグ調グツムのＴＡＳＫスケジェールを管理する
処ｍｓ序管理方式に関するＯ
複数のプログラムの実行を、タスク（ＴＡＳＫ）の概、
ｔＫようて管理するタスク管理方式が広く知られている
。従来のタスクスケジ一−ル管理方式は、プログラムに
対応するタスク制御ブロック（ＴＣＢ）１−設け、こ０
ＴＣＨに基づいてタスクのスケジェール（待ち行列）ｆ
管理する。従来の管理方式を図によりて説明する６＠１
図は従来方式の説明図であり、１＊ Ｌ ３＊
４Ｆｉタスク制御ブロツク（ＴＣＢ）、Ａ１．Ａ自＠
Ａｍ ＠ Ａｍけプログラムの配置アドレス、Ｅ、Ｈは
欄、Ｌｌ、Ｌ雪Ｌ・、Ｌ番はりンク橢、Ｐ＊ｅ Ｐ＠
＝ Ｐ＊−Ｐ番はプログラム、ＱＴＦｉキエーターミナ
ル、Ｓｌ。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a process order management method for managing the TASK schedule of a group of programs.
A task management method that manages tasks in a timely manner is widely known. In the conventional task schedule management method, a task control block (TCB) corresponding to a program is provided.
Schedule (queue) f of tasks based on TCH
to manage. Explaining the conventional management method with diagrams 6@1
The figure is an explanatory diagram of the conventional method, and 1*L 3*
4Fi Task Control Block (TCB), A1. A self @
Am @ Amke program location address, E, H are columns, Ll, L snow L・, L number is link 橢, P*e P@
= P*-P number is program, QTFi terminal, Sl.
８審５８１１８４はステータス情報、Ｔ亀、Ｔ曾Ｔ＝−
７４はＴＣＢの７）’しｘｆあルｏ譲１１１ＪＣおいて
、ＴＣＢＩ〜３には、プログラムＰ＊〜Ｐ−の配置アド
レスＡｌ〜Ａｓと、ステータス情報８１〜Ｓａとが書込
まれており、また各’Ｉ’ＣＢ１及び２のりンク欄Ｌａ
及びり、には、それぞれ次Ｋｌ！行さするべきプログラ
ム対応ＴＣＨのアドレス（ＴＩ、丁ａ）が書込オれてり
ンクさ釣ている・キューテーブルＱＴの＊ＨＫは、最初
Ｋｍ行される先願タスクの制御ブロック［’ＣＢ１）の
アドレスＴＩが格納され、ｔた欄′ＥＫは最終タスクの
制御ブロック（ＴＣＢ３）のアドレスＴｓが格納されて
いる。従うてＴＣＢけ、ＴＣＢｌからＴＣＢ３へＯ順序
で採り上けられ、この順序でプログラムＰ１〜Ｐａが嘴
行されるととになる。さて、仁のような状！ＩＩにおい
て新たにタスクが発生した場合（換言すわば奥行さるべ
きプログラムＰａｔ生じたとき）、ＴＣＢ４を前記ＴＣ
Ｂりンクに挿入する必要があり、これには次の処理手ｌ
１ＩＩｔ必要とする０
■ 最終ＴＣＢ ３０りンク橢Ｌ・に、ＴＣＢ４のアド
レスＴ４Ｖｒ書込む・
■ キエーター２ナルＱＴＯ欄ＥのアドレスＴ・をアド
レスＴ４に書き替える。8th judge 581184 is status information, T turtle, T so T = -
74 is TCB's 7) 'shixfalo transfer 111JC, in TCBI~3, placement addresses Al~As of programs P*~P- and status information 81~Sa are written, Also, link column La of each 'I'CB1 and 2
The following Kl! The address (TI, D) of the TCH corresponding to the program to be executed has been written and the link has been changed. *HK of the queue table QT is the control block ['CB1 ) is stored, and in column 'EK, the address Ts of the control block (TCB3) of the final task is stored. Accordingly, the TCBs are picked up from TCB1 to TCB3 in the order O, and the programs P1 to Pa are executed in this order. Well, it's like Jin! When a new task occurs in II (in other words, when a program Pat that should be deepened occurs), TCB4 is changed to the TC
B link, which requires the following procedure:
1IIt Required 0 ■ Write address T4Vr of TCB4 to final TCB 30 link L・ ■ Rewrite address T・ of keyator 2-null QTO field E to address T4.
以上のように従来方式では、新たにタスクが発生した場
合、リンク再Ｓｔ成のために上紀Ｏ■項及び０項の処理
手順を必要とするが、■璃の処理手順を省略することが
できれば、処理システムＯ処理効率を着しく向上すゐこ
とが可能となるＱ本発明は上記の点に着目したものであ
シーリンクの再−成を不要とする処班馳序管理方式の提
供を目的とする。As described above, in the conventional method, when a new task occurs, the processing steps in Sections 0 and 0 of the above article are required to re-create the link, but it is possible to omit the processing steps in Section 1. If possible, it will be possible to significantly improve the processing efficiency of the processing system.The present invention focuses on the above points, and provides a processing order management method that does not require re-creation of the sea link. purpose.
本発明は、複数のグーグラムの奥行順序を管理する方式
において、館ｌのデータ欄に書き込まれたアドレス情報
によシリングされ、第２のデータ１１に実行待ちプログ
ラムの配「ドレスが書き込すれ、第３のデータ欄に前記
実行待ちプログラムの実行に関わる状態情報が書き込ま
れる第２の制御ブロックｆ複数個用意し、更に実行待ち
となっている前記グログラムの第１１！行待ち１ａグラ
ムを記載すると共にジ曹ブＯ発生に伴うプロダラムＯ記
敏待ちとなりている前ｔ！嬉２０制御ブｑツクＯアドレ
ス管記載する第１の制御ブ牌ツクとを設け、前記プログ
ラムの実行順序會ジｌプの発生と消滅に基づいて前１１
８諏２０制御ブロツクのアドレス指定を更新する事で行
う事を特徴とする処理順序管理方式である◎
以下、本発明を図面によフて説明する。第２１１１１は
本発明の一実施例を説−するブロック図、第３図は本発
明Ｏ−一実施例処Ｉｌ？説明するブロック図であ）、Ｂ
、、Ｂ、、Ｂ番は制御ブロック（ｔ）ｓｂ、、ｂ、６の
アドレス−ｈｂ、、ｂ、、ｔ）ｓｅｔ制御ブロック、Ｃ
はカウンタ欄、Ｅ、ＨはＴＣＢのアドレス管示す欄、Ｋ
ｍ ＊ Ｋｍ ｇ Ｋｓけグログラム配量アドレス記入
−１その他は第１図と同一である。第２図に示すように
本発明はタスク制御ブロック（ｂｔ〜ｂ自）Ｋ予め所定
のリンクを投は喪ことｔ％像とする。この制御ブロック
ｔＤｓＩは、処理システムで発生するタスクの最大数を
力、＜−できるものとする６！ｆ１施例では制御ブロッ
ク数を３ ｍ （ｂ ＊〜ｂｓ）とし、プログラムの最
大数も３個（Ｐｓ〜ｐａ）とするＯ第２図における制御
ブロックｂ、−ｍｂ、 Ｏりンク欄り富〜ＬｓＫは、図
示のように次の制御ブロックのアドレスが予め格納され
為事でリンクされている。例えば制御ブ訪ツクｂ、Ｏリ
ンク−Ｌ＊ＫＦｉ−制御ブロックｂ。The present invention is a system for managing the depth order of a plurality of Goograms, in which the address information of a program waiting to be executed is written in the second data 11, and Prepare a plurality of second control blocks f in which status information related to the execution of the program waiting for execution is written in the third data column, and further write the 11th! line waiting 1a program of the program waiting for execution. At the same time, a first control block is provided in which a control block O address table is written waiting for program O memory due to the occurrence of a program execution order, and a first control block is provided in which the program execution order table is written. Based on the occurrence and extinction of
This is a processing order management method characterized by updating the address designation of the 8th and 20th control block. The present invention will be explained below with reference to the drawings. 21111 is a block diagram illustrating one embodiment of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. In the block diagram to explain), B
,,B,,B number is the address of control block (t)sb,,b,6-hb,,b,,t)set control block,C
is a counter column, E and H are columns indicating TCB address pipe, K
m * Km g Ks grogram ration address entry-1 Other details are the same as in FIG. As shown in FIG. 2, according to the present invention, the task control blocks (bt to b) K have a predetermined link set in advance as a t% image. This control block tDsI allows the maximum number of tasks that can occur in the processing system to be <6! In the f1 example, the number of control blocks is 3 m (b * ~ bs), and the maximum number of programs is also 3 (Ps ~ pa). ~LsK stores the address of the next control block in advance and is linked by reason as shown in the figure. For example, control block b, O-link-L*KFi-control block b.
ＯアドレスＢ・が格納されているＯそ【、て最後の制御
ブロックｂ、のりンク欄り、には、先頭の制御ブロック
ｂ、０アドレスＢｉが格納されているので、リンク状に
りンクされていることＫなるＯまえキエーターンナルＱ
Ｔのカウンタ欄Ｃは実行待ちタスク数Ｏカウンタである
・こＯカウンタ欄Ｃが「０」の場合には、実行すべきジ
ョブ、りまシタスフが存在しないことを示すものとする
Ｏ従りてキエーターＺナルＱＴの欄ＨＫ設定さｒたアド
レスＢｓＫよ多制御ブロックｂｌが指定されても、第２
＠０場合には、グログラムの実行は行わｈｆｋい・しか
し実行すべきタスクが発生した（例えばプログラムＰ＊
ｃ［行が必要となりた）場合ＫＨ−プ璽タグラムＰ＋０
配會アドレスＡグーグラムＰ＠がタスクとして蝿り上げ
もね１実行待ち状１１ＫＪわることＫなる。Since the first control block b and the 0 address Bi are stored in the last control block b and the link field where the O address B is stored, they are linked in the form of a link. What I'm doing K Naru O Mae Kie Turn Naru Q
The counter column C of T is the number of tasks waiting to be executed. If the counter column C is "0", it indicates that there is no job or job to be executed. Even if multiple control blocks bl are specified by the address BsK set in column HK of Keyator Z null QT, the second
If @0, the program is not executed.However, a task to be executed has occurred (for example, program P*
If c [line is needed), KH-Paragram P+0
Even if the distribution address A and Google P@ are passed as a task, 1 execution waiting state 11KJ will be changed.
上記のアドレスＡ１０投足手ｍ１ｍ３図によりて説明す
る。第３８（ａ）Ｆｉ初期状態を示し、タスク（例えば
プログラムＰＫ）が発生した場合には、第２図における
プログラムＰ−の配置アドレスＡｓ管、制御ブロックｂ
ｔｏアドレス欄ＫｉＫ書き込む。またキ轟−ターンナル
Ｑ’ｌ’０９ＥＯアドレスＢ、をアドレスＢ＊に１オた
カウンタ欄ＣｔｒＱＪからｒｌＪＫ書替える０従９て＃
Ｉ３図（ｂ）に示すようにリンク結合状態となる・次は
プログラムＰ・Ｏ実行（タスクの発生）が必要となうた
場合には、第３１１（Ｃ）Ｋ示すように、制御ブロック
ｂ−Ｏアドレス欄に＊にプログラムＰｅＯ配會アドレス
Ａ−ヲ書き込ミ、ｔ ＊ 定ＪＬ −ｆｉ −Ｚ ｔ
＃ Ｑ Ｔ ０４１１１ Ｅ 。This will be explained using the address A10 pitcher m1m3 diagram above. 38(a) Fi shows the initial state, and when a task (for example, program PK) is generated, the arrangement address As tube of program P- in FIG. 2, control block b
Write KiK in the to address field. Also, change the address B of Ki-Todoroki Turnal Q'l'09EO to address B* and rewrite rlJK from CtrQJ to 0 and #
As shown in Figure I3 (b), the link connection state is established.Next, if program P/O execution (task generation) is required, control block b- Write the program PeO distribution address A- in * in the O address column, t * Fixed JL -fi -Z t
# Q T 04111 E.
アドレスｔＢ、からＢｓＫ−管たカウンタｓＣをｒｌＪ
から「２」に書替える・このようＫｌｈたにタスクが発
生した場合には、そのタスクに関わるプ買グラムのアド
レスを制御ブ四ツタ（ｂ璽〜ｔ）ｓ）Ｋ＃＆定し、キ１
−ターンナルの最終タスクのアドレスデータを更新する
の一１ｍ’ｔ’よいＯ従来方式では、新た表タスクが発
生し九場合ＫＦｉ、その新タスクのＴＣＢがリンクされ
る旧最終タスクのＴＣＨのアドレスデータＯｌ！新を必
要としたが、本発明はこれを省略することができるＯ
以上Ｏように本発明は、タスク発生に伴うアドレスデー
タ更ｆＩＯ処理手順が、従来方式より少なくて済むので
処理効率を著しく向上しうる利点を有する・殊に１６ビ
ツトのリイクーリセッす、例えばインテル社の８０８６
のように、アドレス設定にセグメントとオフセットの２
つのアドレス値によシ、アドレス計算を行うようなプロ
セッサでは本発明によるアドレス設定の処理手順の省略
は、極めて効果的なものとなる・Address tB, BsK-tube counter sC rlJ
・If a task like this occurs, set the address of the program related to that task in the control block (b~t)s)K#&, and 1
- Update the address data of the final task of the turn. In the conventional method, when a new table task occurs, KFi, the address data of the TCH of the old final task to which the TCB of the new task is linked. Ol! However, this can be omitted with the present invention. As described above, the present invention significantly improves processing efficiency because the number of address data updating and IO processing procedures required when a task occurs is reduced compared to the conventional method. 16-bit re-cooling reset, such as Intel's 8086
The segment and offset are set in the address setting as shown below.
For processors that perform address calculations based on two address values, the omission of the address setting process according to the present invention is extremely effective.
り
＃Ｅ１図は従来方式を説明するブロッ＃図、′ｌＸＺ図
は本発−の一実施例Ｖｒ観明するブロック図１第３図は
本発明の一実施例の処理を説明するブロック図であ抄、
図中に用いた符号は次Ｏ通シであゐ０１＝ ２ｅ ３
ｅ ４はタスク制御ブロック（ＴＣＢ）Ａｍ ｅ Ａｔ
ａ Ａｓ ｅ Ａ４はプログラムの配置アドレス、Ｂ
ｅ−Ｂ聰ｍＢ−１ｄ制御ブロツク（ｂ、。
ｂ、、 ｂａ ）１２）アドレス、ｂｈｅ ｂｌｍ
ｂ・は制御グ謬ツク１Ｃはカウンタ欄、Ｅ、ＨはＴ
ＣＢアドレスを示す顧、Ｋｍ ｅ Ｋｍ ＊ Ｋｍはグ
ロダラム配壷アドレス配入欄、Ｌ婁ＨＬｍ ＠ Ｌｓ
＠ Ｌ４はリンク機、ＱＴＦｉキ１−ターｉナル、Ｓｓ
＠５−８−．８ｍはステータス情報、Ｔｓ＊Ｔ＊ｔＴａ
ａＴ、 ＦｉＴｃＢのアドレスを示す。
′ｆ７／ 吊
ＱＴ
稟 ２− 酎Figure #E1 is a block diagram for explaining the conventional system, and Figure 1XZ is a block diagram for viewing an embodiment of the present invention. Figure 3 is a block diagram for explaining the processing of an embodiment of the present invention. Ahsho,
The symbols used in the diagram are as follows: 01 = 2e 3
e 4 is the task control block (TCB) Am e At
a As e A4 is the program location address, B
e-B unit B-1d control block (b,. b,, ba) 12) address, bhe blm
b. is the control error 1C is the counter column, E and H are T
Km indicates the CB address, Km e Km * Km is the Grodarum address input field, L HLm @ Ls
@ L4 is a link machine, QTFi terminal, Ss
@5-8-. 8m is status information, Ts*T*tTa
Indicates the address of aT and FiTcB. 'f7/ Suspension QT 稟 2- Shochu
Claims (1)
第１のデータ機に書き込まわたアドレス情報によりリン
クされ、第２のデータ欄に実行待ちグログラムの配置ア
ドレスが書き込まれ、第３、のデータ欄に前記実行待ち
プログラムの実行に関わる状態情報が書き込まれる第２
の制御ブロックを襟数個用意し、更に実行待ちとなって
いる咄紀プログラムＯ第１ＩＩ行持ちプログラム管記載
すると共にジＭ”ｊｌＤ発生に伴うプログラムの記載待
ちとな９ている前記第２の制御ブロックのアドレスを記
載する＃！１の制御ブロックとを設け、前記グログラム
の実行順序をジ冒ブＯ発生と消滅に基づいて前記第２０
ｆｌｔｌＪＩｉｔｌブロツクのアドレス指定ｔ−吏飴す
る事で行う事を特徴とする処理順序管理方式・In a method for managing the execution order of multiple programs,
Linked by the address information written in the first data machine, the location address of the program waiting to be executed is written in the second data column, and the status information related to the execution of the program waiting to be executed is written in the third data column. Second
We prepared several control blocks for the above, and also recorded the 1st and 12th control programs waiting to be executed, as well as the second program waiting to be written due to the occurrence of the program. A control block #!1 in which the address of the control block is written is provided, and the execution order of the program is determined based on the occurrence and disappearance of the program.
A processing order management method characterized by specifying the address of the fltlJIitl block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56186511A JPS5887634A (en) | 1981-11-20 | 1981-11-20 | Processing sequential managing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56186511A JPS5887634A (en) | 1981-11-20 | 1981-11-20 | Processing sequential managing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5887634A true JPS5887634A (en) | 1983-05-25 |
| JPS6342293B2 JPS6342293B2 (en) | 1988-08-23 |
Family
ID=16189778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56186511A Granted JPS5887634A (en) | 1981-11-20 | 1981-11-20 | Processing sequential managing system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5887634A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6242238A (en) * | 1985-08-19 | 1987-02-24 | Nec Corp | Storage device for queue |
| JPS638831A (en) * | 1986-06-28 | 1988-01-14 | Fujitsu Ltd | Ring type queue control system |
| JPH01173137A (en) * | 1987-12-26 | 1989-07-07 | Fujitsu Ltd | Queue control system |
| JPH0424748A (en) * | 1990-05-15 | 1992-01-28 | Matsushita Electric Ind Co Ltd | Parallel processing processor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH034779U (en) * | 1989-06-06 | 1991-01-17 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5556272A (en) * | 1978-10-20 | 1980-04-24 | Hitachi Ltd | Queue control system on load share system |
-
1981
- 1981-11-20 JP JP56186511A patent/JPS5887634A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5556272A (en) * | 1978-10-20 | 1980-04-24 | Hitachi Ltd | Queue control system on load share system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6242238A (en) * | 1985-08-19 | 1987-02-24 | Nec Corp | Storage device for queue |
| JPS638831A (en) * | 1986-06-28 | 1988-01-14 | Fujitsu Ltd | Ring type queue control system |
| JPH01173137A (en) * | 1987-12-26 | 1989-07-07 | Fujitsu Ltd | Queue control system |
| JPH0424748A (en) * | 1990-05-15 | 1992-01-28 | Matsushita Electric Ind Co Ltd | Parallel processing processor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6342293B2 (en) | 1988-08-23 |
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