JPS5887634A - Processing sequential managing system - Google Patents
Processing sequential managing systemInfo
- Publication number
- JPS5887634A JPS5887634A JP56186511A JP18651181A JPS5887634A JP S5887634 A JPS5887634 A JP S5887634A JP 56186511 A JP56186511 A JP 56186511A JP 18651181 A JP18651181 A JP 18651181A JP S5887634 A JPS5887634 A JP S5887634A
- Authority
- JP
- Japan
- Prior art keywords
- address
- program
- task
- control block
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W99/00—Subject matter not provided for in other groups of this subclass
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はグ調グツムのTASKスケジェールを管理する
処ms序管理方式に関するO
複数のプログラムの実行を、タスク(TASK)の概、
tKようて管理するタスク管理方式が広く知られている
。従来のタスクスケジ一−ル管理方式は、プログラムに
対応するタスク制御ブロック(TCB)1−設け、こ0
TCHに基づいてタスクのスケジェール(待ち行列)f
管理する。従来の管理方式を図によりて説明する6@1
図は従来方式の説明図であり、1* L 3*
4Fiタスク制御ブロツク(TCB)、A1.A自@
Am @ Amけプログラムの配置アドレス、E、Hは
欄、Ll、L雪L・、L番はりンク橢、P*e P@
= P*−P番はプログラム、QTFiキエーターミナ
ル、Sl。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a process order management method for managing the TASK schedule of a group of programs.
A task management method that manages tasks in a timely manner is widely known. In the conventional task schedule management method, a task control block (TCB) corresponding to a program is provided.
Schedule (queue) f of tasks based on TCH
to manage. Explaining the conventional management method with diagrams 6@1
The figure is an explanatory diagram of the conventional method, and 1*L 3*
4Fi Task Control Block (TCB), A1. A self @
Am @ Amke program location address, E, H are columns, Ll, L snow L・, L number is link 橢, P*e P@
= P*-P number is program, QTFi terminal, Sl.
8審581184はステータス情報、T亀、T曾T=−
74はTCBの7)’しxfあルo譲111JCおいて
、TCBI〜3には、プログラムP*〜P−の配置アド
レスAl〜Asと、ステータス情報81〜Saとが書込
まれており、また各’I’CB1及び2のりンク欄La
及びり、には、それぞれ次Kl!行さするべきプログラ
ム対応TCHのアドレス(TI、丁a)が書込オれてり
ンクさ釣ている・キューテーブルQTの*HKは、最初
Km行される先願タスクの制御ブロック[’CB1)の
アドレスTIが格納され、tた欄′EKは最終タスクの
制御ブロック(TCB3)のアドレスTsが格納されて
いる。従うてTCBけ、TCBlからTCB3へO順序
で採り上けられ、この順序でプログラムP1〜Paが嘴
行されるととになる。さて、仁のような状!IIにおい
て新たにタスクが発生した場合(換言すわば奥行さるべ
きプログラムPat生じたとき)、TCB4を前記TC
Bりンクに挿入する必要があり、これには次の処理手l
1IIt必要とする0
■ 最終TCB 30りンク橢L・に、TCB4のアド
レスT4Vr書込む・
■ キエーター2ナルQTO欄EのアドレスT・をアド
レスT4に書き替える。8th judge 581184 is status information, T turtle, T so T = -
74 is TCB's 7) 'shixfalo transfer 111JC, in TCBI~3, placement addresses Al~As of programs P*~P- and status information 81~Sa are written, Also, link column La of each 'I'CB1 and 2
The following Kl! The address (TI, D) of the TCH corresponding to the program to be executed has been written and the link has been changed. *HK of the queue table QT is the control block ['CB1 ) is stored, and in column 'EK, the address Ts of the control block (TCB3) of the final task is stored. Accordingly, the TCBs are picked up from TCB1 to TCB3 in the order O, and the programs P1 to Pa are executed in this order. Well, it's like Jin! When a new task occurs in II (in other words, when a program Pat that should be deepened occurs), TCB4 is changed to the TC
B link, which requires the following procedure:
1IIt Required 0 ■ Write address T4Vr of TCB4 to final TCB 30 link L・ ■ Rewrite address T・ of keyator 2-null QTO field E to address T4.
以上のように従来方式では、新たにタスクが発生した場
合、リンク再St成のために上紀O■項及び0項の処理
手順を必要とするが、■璃の処理手順を省略することが
できれば、処理システムO処理効率を着しく向上すゐこ
とが可能となるQ本発明は上記の点に着目したものであ
シーリンクの再−成を不要とする処班馳序管理方式の提
供を目的とする。As described above, in the conventional method, when a new task occurs, the processing steps in Sections 0 and 0 of the above article are required to re-create the link, but it is possible to omit the processing steps in Section 1. If possible, it will be possible to significantly improve the processing efficiency of the processing system.The present invention focuses on the above points, and provides a processing order management method that does not require re-creation of the sea link. purpose.
本発明は、複数のグーグラムの奥行順序を管理する方式
において、館lのデータ欄に書き込まれたアドレス情報
によシリングされ、第2のデータ11に実行待ちプログ
ラムの配「ドレスが書き込すれ、第3のデータ欄に前記
実行待ちプログラムの実行に関わる状態情報が書き込ま
れる第2の制御ブロックf複数個用意し、更に実行待ち
となっている前記グログラムの第11!行待ち1aグラ
ムを記載すると共にジ曹ブO発生に伴うプロダラムO記
敏待ちとなりている前t!嬉20制御ブqツクOアドレ
ス管記載する第1の制御ブ牌ツクとを設け、前記プログ
ラムの実行順序會ジlプの発生と消滅に基づいて前11
8諏20制御ブロツクのアドレス指定を更新する事で行
う事を特徴とする処理順序管理方式である◎
以下、本発明を図面によフて説明する。第21111は
本発明の一実施例を説−するブロック図、第3図は本発
明O−一実施例処Il?説明するブロック図であ)、B
、、B、、B番は制御ブロック(t)sb、、b、6の
アドレス−hb、、b、、t)set制御ブロック、C
はカウンタ欄、E、HはTCBのアドレス管示す欄、K
m * Km g Ksけグログラム配量アドレス記入
−1その他は第1図と同一である。第2図に示すように
本発明はタスク制御ブロック(bt〜b自)K予め所定
のリンクを投は喪ことt%像とする。この制御ブロック
tDsIは、処理システムで発生するタスクの最大数を
力、<−できるものとする6!f1施例では制御ブロッ
ク数を3 m (b *〜bs)とし、プログラムの最
大数も3個(Ps〜pa)とするO第2図における制御
ブロックb、−mb、 Oりンク欄り富〜LsKは、図
示のように次の制御ブロックのアドレスが予め格納され
為事でリンクされている。例えば制御ブ訪ツクb、Oリ
ンク−L*KFi−制御ブロックb。The present invention is a system for managing the depth order of a plurality of Goograms, in which the address information of a program waiting to be executed is written in the second data 11, and Prepare a plurality of second control blocks f in which status information related to the execution of the program waiting for execution is written in the third data column, and further write the 11th! line waiting 1a program of the program waiting for execution. At the same time, a first control block is provided in which a control block O address table is written waiting for program O memory due to the occurrence of a program execution order, and a first control block is provided in which the program execution order table is written. Based on the occurrence and extinction of
This is a processing order management method characterized by updating the address designation of the 8th and 20th control block. The present invention will be explained below with reference to the drawings. 21111 is a block diagram illustrating one embodiment of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. In the block diagram to explain), B
,,B,,B number is the address of control block (t)sb,,b,6-hb,,b,,t)set control block,C
is a counter column, E and H are columns indicating TCB address pipe, K
m * Km g Ks grogram ration address entry-1 Other details are the same as in FIG. As shown in FIG. 2, according to the present invention, the task control blocks (bt to b) K have a predetermined link set in advance as a t% image. This control block tDsI allows the maximum number of tasks that can occur in the processing system to be <6! In the f1 example, the number of control blocks is 3 m (b * ~ bs), and the maximum number of programs is also 3 (Ps ~ pa). ~LsK stores the address of the next control block in advance and is linked by reason as shown in the figure. For example, control block b, O-link-L*KFi-control block b.
OアドレスB・が格納されているOそ【、て最後の制御
ブロックb、のりンク欄り、には、先頭の制御ブロック
b、0アドレスBiが格納されているので、リンク状に
りンクされていることKなるOまえキエーターンナルQ
Tのカウンタ欄Cは実行待ちタスク数Oカウンタである
・こOカウンタ欄Cが「0」の場合には、実行すべきジ
ョブ、りまシタスフが存在しないことを示すものとする
O従りてキエーターZナルQTの欄HK設定さrたアド
レスBsKよ多制御ブロックblが指定されても、第2
@0場合には、グログラムの実行は行わhfkい・しか
し実行すべきタスクが発生した(例えばプログラムP*
c[行が必要となりた)場合KH−プ璽タグラムP+0
配會アドレスAグーグラムP@がタスクとして蝿り上げ
もね1実行待ち状11KJわることKなる。Since the first control block b and the 0 address Bi are stored in the last control block b and the link field where the O address B is stored, they are linked in the form of a link. What I'm doing K Naru O Mae Kie Turn Naru Q
The counter column C of T is the number of tasks waiting to be executed. If the counter column C is "0", it indicates that there is no job or job to be executed. Even if multiple control blocks bl are specified by the address BsK set in column HK of Keyator Z null QT, the second
If @0, the program is not executed.However, a task to be executed has occurred (for example, program P*
If c [line is needed), KH-Paragram P+0
Even if the distribution address A and Google P@ are passed as a task, 1 execution waiting state 11KJ will be changed.
上記のアドレスA10投足手m1m3図によりて説明す
る。第38(a)Fi初期状態を示し、タスク(例えば
プログラムPK)が発生した場合には、第2図における
プログラムP−の配置アドレスAs管、制御ブロックb
toアドレス欄KiK書き込む。またキ轟−ターンナル
Q’l’09EOアドレスB、をアドレスB*に1オた
カウンタ欄CtrQJからrlJK書替える0従9て#
I3図(b)に示すようにリンク結合状態となる・次は
プログラムP・O実行(タスクの発生)が必要となうた
場合には、第311(C)K示すように、制御ブロック
b−Oアドレス欄に*にプログラムPeO配會アドレス
A−ヲ書き込ミ、t * 定JL −fi −Z t
# Q T 04111 E 。This will be explained using the address A10 pitcher m1m3 diagram above. 38(a) Fi shows the initial state, and when a task (for example, program PK) is generated, the arrangement address As tube of program P- in FIG. 2, control block b
Write KiK in the to address field. Also, change the address B of Ki-Todoroki Turnal Q'l'09EO to address B* and rewrite rlJK from CtrQJ to 0 and #
As shown in Figure I3 (b), the link connection state is established.Next, if program P/O execution (task generation) is required, control block b- Write the program PeO distribution address A- in * in the O address column, t * Fixed JL -fi -Z t
# Q T 04111 E.
アドレスtB、からBsK−管たカウンタsCをrlJ
から「2」に書替える・このようKlhたにタスクが発
生した場合には、そのタスクに関わるプ買グラムのアド
レスを制御ブ四ツタ(b璽〜t)s)K#&定し、キ1
−ターンナルの最終タスクのアドレスデータを更新する
の一1m’t’よいO従来方式では、新た表タスクが発
生し九場合KFi、その新タスクのTCBがリンクされ
る旧最終タスクのTCHのアドレスデータOl!新を必
要としたが、本発明はこれを省略することができるO
以上Oように本発明は、タスク発生に伴うアドレスデー
タ更fIO処理手順が、従来方式より少なくて済むので
処理効率を著しく向上しうる利点を有する・殊に16ビ
ツトのリイクーリセッす、例えばインテル社の8086
のように、アドレス設定にセグメントとオフセットの2
つのアドレス値によシ、アドレス計算を行うようなプロ
セッサでは本発明によるアドレス設定の処理手順の省略
は、極めて効果的なものとなる・Address tB, BsK-tube counter sC rlJ
・If a task like this occurs, set the address of the program related to that task in the control block (b~t)s)K#&, and 1
- Update the address data of the final task of the turn. In the conventional method, when a new table task occurs, KFi, the address data of the TCH of the old final task to which the TCB of the new task is linked. Ol! However, this can be omitted with the present invention. As described above, the present invention significantly improves processing efficiency because the number of address data updating and IO processing procedures required when a task occurs is reduced compared to the conventional method. 16-bit re-cooling reset, such as Intel's 8086
The segment and offset are set in the address setting as shown below.
For processors that perform address calculations based on two address values, the omission of the address setting process according to the present invention is extremely effective.
り
#E1図は従来方式を説明するブロッ#図、′lXZ図
は本発−の一実施例Vr観明するブロック図1第3図は
本発明の一実施例の処理を説明するブロック図であ抄、
図中に用いた符号は次O通シであゐ01= 2e 3
e 4はタスク制御ブロック(TCB)Am e At
a As e A4はプログラムの配置アドレス、B
e−B聰mB−1d制御ブロツク(b、。
b、、 ba )12)アドレス、bhe blm
b・は制御グ謬ツク1Cはカウンタ欄、E、HはT
CBアドレスを示す顧、Km e Km * Kmはグ
ロダラム配壷アドレス配入欄、L婁HLm @ Ls
@ L4はリンク機、QTFiキ1−ターiナル、Ss
@5−8−.8mはステータス情報、Ts*T*tTa
aT、 FiTcBのアドレスを示す。
′f7/ 吊
QT
稟 2− 酎Figure #E1 is a block diagram for explaining the conventional system, and Figure 1XZ is a block diagram for viewing an embodiment of the present invention. Figure 3 is a block diagram for explaining the processing of an embodiment of the present invention. Ahsho,
The symbols used in the diagram are as follows: 01 = 2e 3
e 4 is the task control block (TCB) Am e At
a As e A4 is the program location address, B
e-B unit B-1d control block (b,. b,, ba) 12) address, bhe blm
b. is the control error 1C is the counter column, E and H are T
Km indicates the CB address, Km e Km * Km is the Grodarum address input field, L HLm @ Ls
@ L4 is a link machine, QTFi terminal, Ss
@5-8-. 8m is status information, Ts*T*tTa
Indicates the address of aT and FiTcB. 'f7/ Suspension QT 稟 2- Shochu
Claims (1)
第1のデータ機に書き込まわたアドレス情報によりリン
クされ、第2のデータ欄に実行待ちグログラムの配置ア
ドレスが書き込まれ、第3、のデータ欄に前記実行待ち
プログラムの実行に関わる状態情報が書き込まれる第2
の制御ブロックを襟数個用意し、更に実行待ちとなって
いる咄紀プログラムO第1II行持ちプログラム管記載
すると共にジM”jlD発生に伴うプログラムの記載待
ちとな9ている前記第2の制御ブロックのアドレスを記
載する#!1の制御ブロックとを設け、前記グログラム
の実行順序をジ冒ブO発生と消滅に基づいて前記第20
fltlJIitlブロツクのアドレス指定t−吏飴す
る事で行う事を特徴とする処理順序管理方式・In a method for managing the execution order of multiple programs,
Linked by the address information written in the first data machine, the location address of the program waiting to be executed is written in the second data column, and the status information related to the execution of the program waiting to be executed is written in the third data column. Second
We prepared several control blocks for the above, and also recorded the 1st and 12th control programs waiting to be executed, as well as the second program waiting to be written due to the occurrence of the program. A control block #!1 in which the address of the control block is written is provided, and the execution order of the program is determined based on the occurrence and disappearance of the program.
A processing order management method characterized by specifying the address of the fltlJIitl block.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56186511A JPS5887634A (en) | 1981-11-20 | 1981-11-20 | Processing sequential managing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56186511A JPS5887634A (en) | 1981-11-20 | 1981-11-20 | Processing sequential managing system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5887634A true JPS5887634A (en) | 1983-05-25 |
JPS6342293B2 JPS6342293B2 (en) | 1988-08-23 |
Family
ID=16189778
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56186511A Granted JPS5887634A (en) | 1981-11-20 | 1981-11-20 | Processing sequential managing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5887634A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6242238A (en) * | 1985-08-19 | 1987-02-24 | Nec Corp | Storage device for queue |
JPS638831A (en) * | 1986-06-28 | 1988-01-14 | Fujitsu Ltd | Ring type queue control system |
JPH01173137A (en) * | 1987-12-26 | 1989-07-07 | Fujitsu Ltd | Queue control system |
JPH0424748A (en) * | 1990-05-15 | 1992-01-28 | Matsushita Electric Ind Co Ltd | Parallel processing processor |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH034779U (en) * | 1989-06-06 | 1991-01-17 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5556272A (en) * | 1978-10-20 | 1980-04-24 | Hitachi Ltd | Queue control system on load share system |
-
1981
- 1981-11-20 JP JP56186511A patent/JPS5887634A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5556272A (en) * | 1978-10-20 | 1980-04-24 | Hitachi Ltd | Queue control system on load share system |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6242238A (en) * | 1985-08-19 | 1987-02-24 | Nec Corp | Storage device for queue |
JPS638831A (en) * | 1986-06-28 | 1988-01-14 | Fujitsu Ltd | Ring type queue control system |
JPH01173137A (en) * | 1987-12-26 | 1989-07-07 | Fujitsu Ltd | Queue control system |
JPH0424748A (en) * | 1990-05-15 | 1992-01-28 | Matsushita Electric Ind Co Ltd | Parallel processing processor |
Also Published As
Publication number | Publication date |
---|---|
JPS6342293B2 (en) | 1988-08-23 |
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