JPS5877310A - Balanced transformerless amplifier - Google Patents

Balanced transformerless amplifier

Info

Publication number
JPS5877310A
JPS5877310A JP56174495A JP17449581A JPS5877310A JP S5877310 A JPS5877310 A JP S5877310A JP 56174495 A JP56174495 A JP 56174495A JP 17449581 A JP17449581 A JP 17449581A JP S5877310 A JPS5877310 A JP S5877310A
Authority
JP
Japan
Prior art keywords
output
signal
amplifier
stage
differential amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56174495A
Other languages
Japanese (ja)
Other versions
JPH0440886B2 (en
Inventor
Shigeru Saito
茂 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp, Pioneer Electronic Corp filed Critical Pioneer Corp
Priority to JP56174495A priority Critical patent/JPS5877310A/en
Publication of JPS5877310A publication Critical patent/JPS5877310A/en
Publication of JPH0440886B2 publication Critical patent/JPH0440886B2/ja
Granted legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To decrease the number of components and to simplify the circuit constitution, by amplifying an input signal at a differential amplifier and current- amplifying an inverted output picked up respectively from transistors (TRs) of the differential amplifier. CONSTITUTION:A signal inputted to an input terminal IN is voltage-amplified at a voltage amplifying stage 10, picked up at a balanced output from the 2nd stage differential amplifier as a balanced output and a signal is generated at an output point D of a TRQ3, which is opposite in phase and equal to the amplitude of a signal at an output point C of a TRQ4. Output signals of the TRs Q3, Q4 are current-amplified at current amplifying stages 11, 12 to simplify a balanced transformerless BTL amplifier and to decrease the number of components. Further, a feedback circuit 13 is a circuit which feeds back a signal of the stages 11 and 12 to the 1st stage differential amplifier of the voltage amplifying stage 10 as an inverted input, can also be simplified.

Description

【発明の詳細な説明】 本発明はバランスド・トツンスホーマレス(以下BTL
と略記する)増幅器に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention is a balanced totsu homeless (hereinafter referred to as BTL
(abbreviated as) related to amplifiers.

低電源電圧で大出力を得ることのできる増幅器としてB
TL増輻儀が用いられる。
B as an amplifier that can obtain high output with low power supply voltage
TL magnification is used.

従来のIITL増幅器はたとえば第1WAK示す如く、
反転増幅器1、電圧増幅段2シよび電流増幅段3からな
る第1の電力増幅器4、第1の電力増幅器と同様に構成
された第2の電力増幅器Sを必要とし、部品点数が多く
、回路が複雑になる欠点があつ九、なお・は負荷として
のスピーカである。
The conventional IITL amplifier is, for example, as shown in the first WAK.
It requires a first power amplifier 4 consisting of an inverting amplifier 1, a voltage amplification stage 2, and a current amplification stage 3, and a second power amplifier S configured in the same way as the first power amplifier. The other drawback is that it becomes complicated, and the other is the speaker as a load.

本発明は上記にかんがみなされたもので上記の欠点を解
消して、部品点数が少なくかつ回路構成が簡単なIIT
L増幅器を提供することを目的とする。
The present invention has been made in view of the above, and solves the above-mentioned drawbacks, and provides an IIT with a small number of parts and a simple circuit configuration.
The purpose of the present invention is to provide an L amplifier.

以下、本発明を実施例によシ説明する。The present invention will be explained below using examples.

第2図は本発明の一実施例の回路図である。FIG. 2 is a circuit diagram of one embodiment of the present invention.

10は電圧増幅段を、11および12は電圧増幅段10
かもの出力および反転出力で駆動されスピーカーを駆動
する電流増幅段であり、ISa負帰遺回路である。
10 is a voltage amplification stage, 11 and 12 are voltage amplification stages 10
This is a current amplification stage that is driven by the duck output and the inverted output to drive the speaker, and is an ISa negative feedback circuit.

電圧増幅段10社入力電圧が印加されるトランジスタq
1および負帰還回路13の出力電圧が印加されるトラン
ジスタQmおよび定電流源回路Iとからなる初段の差動
増IIl器ムと、初段の差動増幅器ムの出力をそれぞれ
増幅するトランジスタ魁およびq4からなる第2段の差
動増幅器Bとからなっている。
Voltage amplification stage 10 transistor q to which input voltage is applied
1 and negative feedback circuit 13 to which the output voltages are applied, and a first-stage differential amplifier IIl consisting of a transistor Qm and a constant current source circuit I; and a transistor q4 that amplifies the output of the first-stage differential amplifier, respectively. and a second stage differential amplifier B consisting of.

電流増幅段11社第2段の差動増幅wbBのトランジス
タq4の出力を電流増幅するコンプリメンタリ接続のト
ランジスタQs  、Q・ IQ?および1.とかもな
っている、tた電流増幅段12は第21&の差動増#l
i器Bのト2ンジスタQsO出カを電流増幅するコンプ
リメンタリ接続のトランジスタQ@ −Ql・5Qst
シよびq13′とからなっている。
Current amplification stage 11 companies Complementary connection transistor Qs, Q・IQ? that current amplifies the output of transistor q4 of the second stage differential amplification wbB. and 1. The current amplification stage 12 is the 21st & differential amplifier #l.
Complementary connected transistor Q@-Ql・5Qst that current amplifies the output of transistor QsO of i-device B
It consists of shi and q13'.

一方、負#l11回路13は電流増幅段11の出力端1
点の(1号が、電流増幅R12の出力端1点の信号と逆
相のため、1点の信号を反転して1点の信号と混合して
増幅し、電圧増幅段1oの初段の差動増幅器ムに反転入
力として帰還するための回路である。
On the other hand, the negative #l11 circuit 13 is connected to the output terminal 1 of the current amplification stage 11.
Since the point (No. 1) has the opposite phase to the signal at the output terminal 1 of the current amplifier R12, the signal at the 1 point is inverted, mixed with the signal at the 1 point, and amplified, and the difference at the first stage of the voltage amplification stage 1o is This is a circuit for feeding back to the dynamic amplifier as an inverting input.

いま電圧増幅段100入力端子INK入力信号が印加さ
れた場合、各段の信号の状態は第2図において正弦波状
の図で示しである。
When the INK input signal is applied to the input terminal of the voltage amplification stage 100, the state of the signal at each stage is shown by a sine wave diagram in FIG.

入力信号線電圧増幅段10で電圧増幅されるが、その出
力段である第2段の差動増幅器Bから平衡出力として取
シ出される。すなわち、トランジスタq、の出力点り点
には、トランジス1りq、の出力点0点の信号と逆相で
あって線輪の全く等しい信号が発生している。従ってこ
のトランジスタQaeq4の出力信号を電流増幅段11
および12で電流増幅することにより、別途に反転増@
器を必要としなくなJ)、BTL1gl路が簡単となシ
、部品点数が減少するととになる。
The voltage is amplified in the input signal line voltage amplification stage 10, and is taken out as a balanced output from the second stage differential amplifier B, which is the output stage. That is, at the output point of transistor q, a signal is generated that is in opposite phase to the signal at the output point 0 of transistor 1 and q, and has exactly the same line ring. Therefore, the output signal of this transistor Qaeq4 is transmitted to the current amplification stage 11.
By amplifying the current with and 12, the inversion increase @
The BTL 1gl path is simplified, and the number of parts is reduced.

を九電圧増幅段10に負帰還をかけない形の増幅器を用
いれば、負帰還回路13は省略することができる。
If an amplifier that does not apply negative feedback to the voltage amplification stage 10 is used, the negative feedback circuit 13 can be omitted.

また負帰還をかける場合においても、第3図に示す如く
1点の信号をトランジスタQslで反転し、y*o*号
と加えるようにすることで、負帰還回路を簡略化するこ
ともできる。
Further, even when negative feedback is applied, the negative feedback circuit can be simplified by inverting the signal at one point with a transistor Qsl and adding it to y*o* as shown in FIG.

以上説明した如く本発明によれば、入力信号を増幅する
電圧増噛声を差動増幅器で構成し、前記差動増aSを構
成するトランジスタからそれぞれ反転出力を取シ出し、
電流増幅するようにし九ことによ)、従来のBTL増幅
器の如く別途反転回路を必要とせず、回路構成が簡単罠
なって、部品点数も減少する。
As explained above, according to the present invention, the voltage amplification voice for amplifying the input signal is configured by a differential amplifier, and the inverted outputs are taken from each transistor constituting the differential amplification aS,
By amplifying the current, unlike the conventional BTL amplifier, a separate inverting circuit is not required, the circuit configuration is simple, and the number of parts is reduced.

また、従来のBTL増幅器の如く一方の電力増幅器にの
み反転増幅器を通した信号を印加して亀り増幅する必要
もないために、2つの電力増幅器間における時間遅れも
生ずること社なくなる。
Further, unlike the conventional BTL amplifier, there is no need to apply a signal passed through an inverting amplifier to only one power amplifier to amplify the signal, so there is no need to cause a time delay between the two power amplifiers.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来のBTL増幅器の回路図、第2図は本発
明の一実施例の回路図、第3図は第2図における負帰還
回路°の他の例を示す回路図である。 10−一電圧増幅段、11′に−よび12・・・電流増
幅段、13・・・負111111回路、ム・・・初段の
差動増幅器、B・・・第2段の差動増幅器、X −・定
電流源回路。 特許出願人  パイオニア株式金社
FIG. 1 is a circuit diagram of a conventional BTL amplifier, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a circuit diagram showing another example of the negative feedback circuit shown in FIG. 10-1 voltage amplification stage, 11'-12... current amplification stage, 13... negative 111111 circuit, M... first stage differential amplifier, B... second stage differential amplifier, X - Constant current source circuit. Patent applicant Pioneer Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 入力信置を増幅する電圧増幅段を差動増幅器で構成し、
前記差動増幅器を構成するトランジスタからそれぞれ反
転出力をkiie出し、取シ出し九反転出力を各別に電
流増幅するようにしてなること10黴とするバランスド
・トランスホーマレス増幅器。
The voltage amplification stage that amplifies the input signal is composed of a differential amplifier,
10. A balanced transformerless amplifier, wherein an inverted output is output from each of the transistors constituting the differential amplifier, and each of the inverted outputs is amplified as a current.
JP56174495A 1981-11-02 1981-11-02 Balanced transformerless amplifier Granted JPS5877310A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56174495A JPS5877310A (en) 1981-11-02 1981-11-02 Balanced transformerless amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56174495A JPS5877310A (en) 1981-11-02 1981-11-02 Balanced transformerless amplifier

Publications (2)

Publication Number Publication Date
JPS5877310A true JPS5877310A (en) 1983-05-10
JPH0440886B2 JPH0440886B2 (en) 1992-07-06

Family

ID=15979484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56174495A Granted JPS5877310A (en) 1981-11-02 1981-11-02 Balanced transformerless amplifier

Country Status (1)

Country Link
JP (1) JPS5877310A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4806813A (en) * 1986-03-20 1989-02-21 Canon Kabushiki Kaisha Motor
JPH0486320U (en) * 1990-11-30 1992-07-27
US5399986A (en) * 1993-12-20 1995-03-21 Yen; Wailit Isolated multi-output power amplifier

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5478956A (en) * 1977-12-07 1979-06-23 Hitachi Ltd Amplified output circuit
JPS5615607A (en) * 1979-07-14 1981-02-14 Iseki Agricult Mach Detector for tilling depth and direction control in tiller
JPS5757621U (en) * 1980-09-19 1982-04-05

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2244781C3 (en) * 1972-09-13 1979-03-22 Robert Bosch Gmbh, 7000 Stuttgart Ignition system for internal combustion engines

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5478956A (en) * 1977-12-07 1979-06-23 Hitachi Ltd Amplified output circuit
JPS5615607A (en) * 1979-07-14 1981-02-14 Iseki Agricult Mach Detector for tilling depth and direction control in tiller
JPS5757621U (en) * 1980-09-19 1982-04-05

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4806813A (en) * 1986-03-20 1989-02-21 Canon Kabushiki Kaisha Motor
JPH0486320U (en) * 1990-11-30 1992-07-27
US5399986A (en) * 1993-12-20 1995-03-21 Yen; Wailit Isolated multi-output power amplifier

Also Published As

Publication number Publication date
JPH0440886B2 (en) 1992-07-06

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