JPS5871648A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5871648A JPS5871648A JP56169474A JP16947481A JPS5871648A JP S5871648 A JPS5871648 A JP S5871648A JP 56169474 A JP56169474 A JP 56169474A JP 16947481 A JP16947481 A JP 16947481A JP S5871648 A JPS5871648 A JP S5871648A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- resistance
- film
- silicon layer
- high resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 229910052796 boron Inorganic materials 0.000 abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 7
- 239000011574 phosphorus Substances 0.000 abstract description 7
- -1 phosphorus ions Chemical class 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000002513 implantation Methods 0.000 abstract 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005056 compaction Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置に関するものである。[Detailed description of the invention] The present invention relates to a semiconductor device.
近年のＬＳＩの集積度の向上に伴なって、例えばスタチ
ック塩のメモリー素子等では、セル内の負荷素子に半導
体抵抗素子を用いるようになってきている。プロセス上
の簡易さから首へは、多結晶シリコン層により抵抗素子
を形成するのが盛んであるが、従来のこの種の素子は、
その高い抵抗値の制御という事で素子寸法が大きくなる
という欠点を有していた。With the recent improvement in the degree of integration of LSIs, semiconductor resistance elements have come to be used as load elements in cells, for example, in static salt memory elements. Due to the simplicity of the process, it is popular to form resistance elements using polycrystalline silicon layers, but conventional elements of this type are
Controlling the high resistance value has the disadvantage that the element size becomes large.
本発明は従来のプロセスの容易さを損う事なく製造で龜
、素子寸法が非常に小さく安定し圧扁抵抗を持つ半導体
抵抗素子を提供するものである。The present invention provides a semiconductor resistance element that can be manufactured without sacrificing the ease of conventional processes, has very small element dimensions, is stable, and has compaction resistance.
本発明は２種類の互いに導電性の異なる不純物を含有す
る多結晶シリコン層で形成され圧扁抵抗素子を含む事會
特像とする半導体装置にある。The present invention resides in a semiconductor device which is formed of a polycrystalline silicon layer containing two types of impurities having different conductivities and includes a compressed resistance element.
第１図に従来素子の一例を示す。図に於て１．８は両端
の電極となる低抵抗領域であり、２は、高抵抗領域であ
るが、この抵抗素子を多結晶シリコン層ｔベースにして
作製する場合先づ１．鼠３の全領域に低濃度の不純物イ
オンを打ち込んで高抵抗を持った導電性層となし先後、
２０部分をマスクして高濃度の不純物熱拡散により１．
３の低抵抗領域を形成している。ところが、この種の構
造では、１．３．と２が同導電Ｉ！ｌを有してお如、不
純物湊度の違いのみで、高抵抗部と低抵抗部を形成して
いるため、その後の熱工程によ）、ｌ及び３の高濃度領
域から２の低濃度領域への不純物拡散を考えると、安定
し圧扁抵抗値を得る為には、充分な長さのｔが必要にな
ってくる。実際に即して言えば、不純物がリンの場合１
．３からの拡散によるはいり込みが４μｍ、高抵抗部分
が〜４μｍで、合計のｔは少なくとも１２μｍもの長さ
になる。FIG. 1 shows an example of a conventional element. In the figure, 1.8 is a low-resistance region that becomes the electrodes at both ends, and 2 is a high-resistance region.When manufacturing this resistance element using a polycrystalline silicon layer t as a base, first 1. After implanting low concentration impurity ions into the entire area of mouse 3 to create a conductive layer with high resistance,
1. By masking the 20 parts and thermally diffusing impurities at a high concentration.
3 low resistance regions are formed. However, in this type of structure, 1.3. and 2 are the same conductivity I! Since the high-resistance part and the low-resistance part are formed only by the difference in impurity concentration, the subsequent thermal process changes the high-concentration region of 1 and 3 to the low-concentration region of 2. Considering the diffusion of impurities into the region, a sufficient length t is required in order to obtain a stable compression resistance value. Practically speaking, if the impurity is phosphorus, 1
．． The intrusion due to diffusion from 3 is 4 μm, and the high resistance portion is ~4 μm, making the total t as long as at least 12 μm.
次に本発明の詳細について述べる。Next, details of the present invention will be described.
第２図は、本発明の原理による半導体装置の抵抗素子の
構造で、多結晶シリコン層をペースとしている。４．６
は高濃度に例えばリンを注入した低抵抗部であり、５に
は、前記リン濃度を殆んど打ち消す様に高濃度にリンと
は逆の導電性を与える不純物、例えばボロンを注入する
ｔこのとき、５の部分は、２種の不純物が打ち消し合う
が、非常に低濃度ＫＩＪンが不純物として存在する様に
する。FIG. 2 shows the structure of a resistive element of a semiconductor device according to the principles of the present invention, using a polycrystalline silicon layer as a base. 4.6
is a low-resistance part in which phosphorus, for example, is implanted in a high concentration, and 5 is a low resistance part in which an impurity, for example boron, is implanted in a high concentration to give conductivity opposite to that of phosphorus so as to almost cancel out the phosphorus concentration. At this time, in the part 5, the two types of impurities cancel each other out, but a very low concentration of KIJ is made to exist as an impurity.
これはイオン注入という技術を用いれば制御性良く実現
する事が出来る。このようにボロンを高濃度に打ち込む
為と、あらかじめ全領域（４，５，６）にリンが１６１
１度に存在することから、４，６から５への拡散を全く
考慮する必要がなく、Ｌの長さを非常に短かくできる。This can be achieved with good controllability by using a technique called ion implantation. In order to implant boron at a high concentration in this way, 161 phosphorus was added to the entire area (4, 5, 6) in advance.
Since they exist at once, there is no need to consider the diffusion from 4 and 6 to 5, and the length of L can be made very short.
次に本発明の実施例を図によって説明する。第３図（ａ
）、半導体基板１１に活性領域１２ｔ−形成した後、絶
縁膜１３を介して全面に多結晶シリコン膜１４ｔ−形成
する。その後骸多結晶シリコン膜に導電性を持たせる為
ＫＩＪンのイオン注入をエネルギー１５０ Ｋ−ｖ、ド
ーズ量５Ｘ” ０１Ｂ、、−Ｚで行なって層抵抗値的２
０ Ｋｆｌ／、前後を持たせる。次に第３図（ｂｌ、良
く知られた写真蝕刻技術により、多結晶シリコン層を所
望のパターンに形成してから、第２の不純物であるボロ
ンのイオン注入に備えてマスク窒化膜を３００ＯＡの厚
さに形成し多結晶シリコン層の高抵抗を形成すべき部分
に４μｍ１１度の開口１６に−設ける。その後ボロンの
イオン注入をエネルギー５０Ｋｅｖ、ドーズ量４．８Ｘ
１０ｍで全面に行なう。このとき、Ｂの部分は、開口１
６を通して、ボロンが打ち込まれリンと打ち消し会い１
００ＭΩ／口 前後の層抵抗値となる。第３図（Ｃ１、
その後絶縁膜１７ｔ−形成して、コンタクト穴１８會開
孔してから、アルミ配線電極１９を設は半導体抵抗素子
を完成させる。なお本発明の抵抗素子では、抵抗の両端
部分の層抵抗が従来のものに比べ高目になる事が予想さ
れるが、実際の素子の場合、例えば第４図に示し九スタ
チック型のメモリセルに使用した時この部分の抵抗値は
、全く問題にならない。第４図では２０．２１が本発明
による半導体抵抗素子で、２３．２４がスイッチングト
ランジスタ、２２．２５がトランスファゲートトランジ
スタである。即ち第２図に於て、高抵抗部分として長さ
Ｌの５だけを考えていたものを１長さＬ′の４．５．６
全体として考えればいいわけで、この様な考え方が可能
となったのも本発明の利点の１つである。Next, embodiments of the present invention will be described with reference to the drawings. Figure 3 (a
), after forming an active region 12t- on the semiconductor substrate 11, a polycrystalline silicon film 14t- is formed on the entire surface with an insulating film 13 interposed therebetween. After that, in order to make the skeleton polycrystalline silicon film conductive, ion implantation was performed at an energy of 150 K-v and a dose of 5X''01B, -Z, resulting in a layer resistance value of 2.
0 Kfl/, have front and back. Next, a polycrystalline silicon layer is formed into a desired pattern using a well-known photolithography technique, and a mask nitride film is deposited at 300 OA in preparation for ion implantation of boron, which is the second impurity. An opening 16 of 4 μm and 11 degrees is formed in the portion where the high resistance of the polycrystalline silicon layer is to be formed.Then, boron ions are implanted at an energy of 50 Kev and a dose of 4.8X.
Do this over the entire surface at 10m. At this time, part B is the opening 1
Through 6, boron is driven and cancels with phosphorus 1
The layer resistance value is around 00MΩ/mouth. Figure 3 (C1,
Thereafter, an insulating film 17t is formed, a contact hole 18 is formed, and an aluminum wiring electrode 19 is formed to complete the semiconductor resistance element. In the resistor element of the present invention, it is expected that the layer resistance at both ends of the resistor will be higher than that of the conventional resistor, but in the case of an actual element, for example, the static type memory cell shown in FIG. The resistance value of this part does not matter at all when used for. In FIG. 4, 20.21 is a semiconductor resistance element according to the present invention, 23.24 is a switching transistor, and 22.25 is a transfer gate transistor. That is, in Fig. 2, the high resistance part was considered to be only 5 of length L, but instead of 4.5.6 of length L'.
It is only necessary to think about it as a whole, and one of the advantages of the present invention is that this kind of thinking is possible.
以上、本発明に依れば、従来の製法と殆んど変わらない
簡易さで、素子寸法が１７３以下の高抵抗素子を有する
半導体装置を得ることができる。As described above, according to the present invention, a semiconductor device having a high resistance element having an element size of 173 mm or less can be obtained with almost the same simplicity as the conventional manufacturing method.
第１図は従来技術ｔ７ｒ、す概略断面図であり、第２図
は本発明の原理金示す概略断面図である。第３図（ｍｌ
乃至第３図（Ｃ）は本発明の一実施例を工程順に示す断
面図であり第４図は本発明の応用例を示す回路図である
。
尚、図において１・・・・・・低抵抗部、２・・・・・
・高抵抗部、３・・・・・低抵抗部、４・・・・・低抵
抗部、５・・・・・・高抵抗部、６・・・・・・低抵抗
部、１１・・・・・・半導体基板、１２・・・・・・活
性領域、１３・・・・・・絶縁膜、１４・・・・・・多
結晶シリコン層、１５・・・・・・シリコン窒化膜、１
６・・・・・・開口、１７・・・・・・絶縁膜、１８・
・・・・・開口、１９・・・・・・アルミ配線電極、Ａ
・・・・・・低抵抗部、Ｂ・・・・・・高抵抗部、Ｃ・
・・・・・低抵抗部、２０．２１・・・・・・半導体抵
抗素子、２２，２３，２４．２５・・・・・・トランジ
スタである。FIG. 1 is a schematic sectional view of the conventional technology t7r, and FIG. 2 is a schematic sectional view showing the principle of the present invention. Figure 3 (ml
3C to 3C are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIG. 4 is a circuit diagram showing an application example of the present invention. In the figure, 1...low resistance part, 2...
・High resistance part, 3...Low resistance part, 4...Low resistance part, 5...High resistance part, 6...Low resistance part, 11... ... Semiconductor substrate, 12 ... Active region, 13 ... Insulating film, 14 ... Polycrystalline silicon layer, 15 ... Silicon nitride film, 1
6...Opening, 17...Insulating film, 18.
...Opening, 19...Aluminum wiring electrode, A
...Low resistance part, B...High resistance part, C.
...low resistance section, 20.21 ... semiconductor resistance element, 22, 23, 24.25 ... transistor.
Claims (1)
シリコン層で形成された高抵抗素子を含む事ｔ４１微と
する半導体装置。A semiconductor device including a high resistance element formed of a polycrystalline silicon layer containing two types of impurities having different conductivities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56169474A JPS5871648A (en) | 1981-10-23 | 1981-10-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56169474A JPS5871648A (en) | 1981-10-23 | 1981-10-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5871648A true JPS5871648A (en) | 1983-04-28 |
| JPH0131704B2 JPH0131704B2 (en) | 1989-06-27 |
Family
ID=15887222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56169474A Granted JPS5871648A (en) | 1981-10-23 | 1981-10-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5871648A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582465A (en) * | 1991-09-24 | 1993-04-02 | Victor Co Of Japan Ltd | Semiconductor device and mos fet |
| JP2002016237A (en) * | 2000-06-27 | 2002-01-18 | Hitachi Ltd | Semiconductor ic device and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5529108A (en) * | 1978-08-23 | 1980-03-01 | Hitachi Ltd | Semiconductor resistance element |
-
1981
- 1981-10-23 JP JP56169474A patent/JPS5871648A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5529108A (en) * | 1978-08-23 | 1980-03-01 | Hitachi Ltd | Semiconductor resistance element |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582465A (en) * | 1991-09-24 | 1993-04-02 | Victor Co Of Japan Ltd | Semiconductor device and mos fet |
| JP2002016237A (en) * | 2000-06-27 | 2002-01-18 | Hitachi Ltd | Semiconductor ic device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0131704B2 (en) | 1989-06-27 |
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