JPS5867050A - Resin seal type semiconductor device - Google Patents

Resin seal type semiconductor device

Info

Publication number
JPS5867050A
JPS5867050A JP56165334A JP16533481A JPS5867050A JP S5867050 A JPS5867050 A JP S5867050A JP 56165334 A JP56165334 A JP 56165334A JP 16533481 A JP16533481 A JP 16533481A JP S5867050 A JPS5867050 A JP S5867050A
Authority
JP
Japan
Prior art keywords
resin
stress
sealing
buffer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56165334A
Other languages
Japanese (ja)
Inventor
Yasuhisa Kobayashi
小林　安久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56165334A priority Critical patent/JPS5867050A/en
Publication of JPS5867050A publication Critical patent/JPS5867050A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To relax the stress of sealing resin, and to prevent an effect on a semicondutor element by mounting resin for buffer only to the side surface of the element. CONSTITUTION:A circuit surface 5 is used as an upper surface, the resin 4 for buffer is attached to the whole side surface among the surface exposed of the element 1, and the thickness of the resin in the B direction is thinned and the thickness of the resin in the C direction is thickened, that is, resin stress in the B direction is small and one in the C direction occupies the most part when comparing resin stress. Accordingly, stress due to the shrinkage of resin after sealed with resin is not directly transmitted to the element, and the variation of electric characteristics, etc. can be prevented. Stress due to the expansion or shrinkage of sealing resin is not similarly transmitted to the element 1 even to a temperature change after sealing, and the breakdown of the element 1 can be obviated. There is no danger that connecting wires 3 are detached due to the temperature change after sealing. Since the resin 4 for buffer is coated before the element 1 is mounted and the connecting wires 3 with the outsides are set up, there is no danger that the connecting wires 3 are broken, and yield thereof is improved.

Description

【発明の詳細な説明】 本発明は樹脂封止型半導体装置の構造に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a resin-sealed semiconductor device.

樹脂封止型半導体装置は、そこに使用されている封止樹
脂とリードフレーム、あるいは半導体素子（以下単Ｋｌ
子と呼ぶ）等の部材の熱膨張係数が大きく異なるため、
半導体装置の内部でひずみが起っている。特に封止樹脂
の熱膨張係数拡大きく、又その製造工程上１５０℃以上
の高温で封止樹Ｎ管硬化させるため、半導体装置を使用
する時Ｏｉｉ度即ち常温では封止樹脂が収縮し、かなシ
の応力が素子に加わっている。この封止樹脂の応力によ
り素子の電気的峙性、４Ｉに抵抗値は樹脂封止前と封止
後とでは大きく変動し１時には封止後のｉ１度変化で素
子の破、ＩＩＫＫ至ることがある。素子の集積度が向上
してきた現在、高熱伝導率の封止樹脂は不可欠なものと
なっている。しかし高熱伝導率の封止樹脂はどその成分
の関係から熱膨張率も高くなって匹るのが現状である。Resin-encapsulated semiconductor devices are made up of the encapsulating resin and lead frame used therein, or the semiconductor element (hereinafter simply referred to as Kl).
Because the thermal expansion coefficients of parts such as
Distortion occurs inside the semiconductor device. In particular, the coefficient of thermal expansion of the sealing resin is large, and the sealing resin N tube is cured at a high temperature of 150°C or higher in the manufacturing process, so when semiconductor devices are used, the sealing resin shrinks at room temperature. This stress is applied to the element. Due to the stress of this sealing resin, the electrical resistance of the element, 4I, varies greatly between before and after resin sealing, and a change of 1 degree after sealing can lead to element failure and IIKK. be. Nowadays, as the degree of integration of devices increases, sealing resins with high thermal conductivity have become indispensable. However, the current situation is that sealing resins with high thermal conductivity have comparable high coefficients of thermal expansion due to their components.

この封止樹脂による応力ｔ−緩和するために、従来の半
導体装置は第１図の断面図に示すように、素子マウント
部２に接着された素子ｌｔ皺衝用樹Ｍ４で被覆して封止
樹脂の応力を防ぐ方法や、おるーは応力が加わること管
計算に入れ素子の回路上で抵抗値等をＭ！１して回路を
設計する方法等が考えられてｉるが、第１図による方法
は緩衝効果というその性質上、Ｉｌ衝吊用樹脂熱膨張係
数は大きくせざるを得ない、そのため素子１と接＠線３
との接続部、即ち、第１図の点Ａの部分が樹脂封止後の
温ｆｆ化により離脱する危険性がめる・さらにこの緩衝
用樹脂４ｔ−設ける作業は、素子ｌと外部との接続線３
と會接続した後に行なう几め１作業中この接続ｍ３ｅ破
壊する危険性がある。又回路設計上で抵抗恒等ｔ−調整
する方法は封止樹脂応力による特性変動の割合が一定し
ないため、非常に困難な方法である。In order to alleviate the stress caused by the sealing resin, the conventional semiconductor device is sealed by covering the element lt attached to the element mount part 2 with a wrinkle material M4, as shown in the cross-sectional view of FIG. How to prevent stress in the resin, and how to calculate the resistance value on the circuit of the element by taking into account the fact that stress is applied to the tube M! However, due to the buffering effect of the method shown in Figure 1, the coefficient of thermal expansion of the suspension resin must be increased, so Tangent @ line 3
There is a risk that the connection part with the element 1, that is, the part A in Fig. 1, will come off due to heating after resin sealing.Furthermore, the work of installing this buffer resin 4t will involve connecting the connection line between the element 1 and the outside. 3
There is a risk that this connection m3e will be destroyed during the procedure 1 that will be carried out after the connection is made. Further, the method of adjusting the resistance identity t- in circuit design is a very difficult method because the rate of characteristic variation due to the stress of the sealing resin is not constant.

本発明はかかる欠点を除去した樹脂封止型半導体装置を
提供することにある。The object of the present invention is to provide a resin-sealed semiconductor device that eliminates such drawbacks.

以下本発明の要旨を実施例に基づいて説明する。The gist of the present invention will be explained below based on examples.

本発明の要旨は半導体素子の側面（回路面を上面とする
）のみに緩衝用樹脂を設けることによシ封止樹廁の応力
會緩和し、素子に前述のような影響を与えないようにす
ることにある。第２図は本発明の第１の実施例を示すも
ので（ωは断面図、伽）は平面図である。封止樹脂の膨
張収縮は等方的に起こるものであり、それ故素子に加わ
る応力は封止ｗ脂の厚さに比例することになる。すなわ
ち第２図（−においてＢ方向の樹脂の厚さが薄くＣ方向
半を占めることになる。このことよシ樹脂応力の緩和に
は、素子の側面のみに緩衝用樹脂として封止樹脂よりも
柔らかい材料を用いた緩衝部を設けることによ）、その
効果を十分発揮するものである。The gist of the present invention is to provide a buffering resin only on the side surface of the semiconductor element (with the circuit surface as the top surface), thereby alleviating the stress of the sealing tree and preventing the above-mentioned effects on the element. It's about doing. FIG. 2 shows a first embodiment of the present invention (ω is a sectional view, and ω is a plan view). Expansion and contraction of the sealing resin occurs isotropically, and therefore the stress applied to the element is proportional to the thickness of the sealing resin. In other words, in Figure 2 (-), the thickness of the resin in the B direction is thinner and occupies half of the thickness in the C direction.This means that in order to alleviate the resin stress, it is necessary to use buffer resin only on the sides of the element, rather than the sealing resin. By providing a buffer section made of soft material), this effect can be fully demonstrated.

本発明の第１の実施例は、第２図（ｂ）に示すように１
回路面５を上面とした場合、素子１の露出面のうち側面
全体に緩衝用樹脂を設けたものである。The first embodiment of the present invention is as shown in FIG. 2(b).
When the circuit surface 5 is the upper surface, a buffering resin is provided on the entire side surface of the exposed surface of the element 1.

このようにすると、前述のような樹脂封止後の樹脂の収
縮による応力は直接素子に伝わらなくな）、電気特性等
の変動を防ぐどとが出来る。又、封止後の温度変化に対
しても同様に封止樹脂の膨張又は収縮による応力が素子
１に、伝わらず、素子ｌの破壊を防ぐことが出来る。さ
らに封止後の温度変化で接続線３が離脱するような危険
性は全くない、その上この緩衝用樹脂の被覆は素子１を
マウント後、外部との接続Ｉｉ３を設ける前に行なえる
ため、接続線３を破壊するような危険性は全くない、そ
れ故従来の製造方法を変えることなく歩留シを向上させ
ることが出来る。さらに樹脂系の素子マウント剤を用い
た製造方法においては、その欠点である素子マウント強
度が弱いという点も補うことが出来、かつマウント剤が
素子周辺部にはみ出し電流の漏れが起るような時でも緩
衝用樹脂によりて被覆されるため漏電の心配もなくすこ
とが出来、高信頼度の半導体装置を得ることが出来る。In this way, stress due to shrinkage of the resin after resin sealing as described above is not directly transmitted to the element), and fluctuations in electrical characteristics etc. can be prevented. Furthermore, stress due to expansion or contraction of the sealing resin is not transmitted to the element 1 due to temperature changes after sealing, and destruction of the element 1 can be prevented. Furthermore, there is no risk of the connection wire 3 coming off due to temperature changes after sealing, and furthermore, this buffering resin coating can be done after mounting the element 1 and before making the connection Ii3 with the outside. There is no risk of destroying the connecting wire 3, and therefore the yield can be improved without changing the conventional manufacturing method. Furthermore, the manufacturing method using a resin-based element mounting agent can compensate for the weak element mounting strength, which is a drawback, and can also be used in cases where the mounting agent protrudes to the periphery of the element and causes current leakage. However, since it is covered with a buffering resin, there is no need to worry about electrical leakage, and a highly reliable semiconductor device can be obtained.

この緩衝部を形成する緩衝用樹脂としては、東しシリコ
ーン社製ＪＣＲ−６１０６，−６１０７，−６１０＆−
６１１０，信越化学社製ＫＪＲ−９０１０，−９０２０
゜−９０３０、−９０３１，−９０３４等が使用出来る
。As the buffer resin forming this buffer part, JCR-6106, -6107, -610&- manufactured by Toshi Silicone Co., Ltd.
6110, Shin-Etsu Chemical KJR-9010, -9020
-9030, -9031, -9034, etc. can be used.

第３図は本発明の第２の実施例を示す平面図でおる。こ
れは半導体素子の対向２ｇＡ面のみに緩衝用樹脂４を設
け、半導体装置の長手方向からの封止樹脂応力を緩和し
たものである。樹脂封止型半導体装置の中でも、集積度
の高いものは該装置の幅に比べ長さが大のものが多い、
この嫌な半導体装置においては、第３図に示すＣ８方向
の応力に比べＣＩ方向の応力が非常に大きい、それ故、
第２の実施例においても、封止樹脂応力に対する緩衝効
果は第１の実施例と同じとなることは明らかでるる、こ
の様にすると緩衝用樹脂の使用量が少ないため、コスト
の低減が行なえる。又、製造工程上も対向２側面のみに
緩衝用樹脂を使用すればよいため製造設備も簡略化出来
、歩留ルの向上及びコスト低減も行なえる。FIG. 3 is a plan view showing a second embodiment of the invention. In this case, a buffer resin 4 is provided only on the opposing 2gA surface of the semiconductor element to relieve the stress of the sealing resin from the longitudinal direction of the semiconductor device. Among resin-sealed semiconductor devices, those with a high degree of integration often have a length that is larger than the width of the device.
In this unpleasant semiconductor device, the stress in the CI direction is much larger than the stress in the C8 direction shown in FIG.
It is clear that in the second embodiment, the buffering effect against the stress of the sealing resin is the same as in the first embodiment.In this way, the amount of buffering resin used is small, so costs can be reduced. Ru. Furthermore, since it is only necessary to use the buffering resin on the two opposing sides in the manufacturing process, the manufacturing equipment can be simplified, and the yield can be improved and costs can be reduced.

第４図は本発明の第３の実施例を示す断面図である。こ
れは素子マウント部２が通常の位置よりも婢し下げられ
たリードフレームを使用したものである。FIG. 4 is a sectional view showing a third embodiment of the present invention. This uses a lead frame in which the element mounting portion 2 is lowered than the normal position.

このようにすると緩衝用樹脂の塗布方法として素子の下
面方向より行なうことが出来１例えば素子ｉラント後緩
衝用樹脂を含んだローラーの上を通す等の方法が使用出
来、より自動化された設備を用いることが出来る。これ
によシコストの低減及び歩留夛の向上を計ることが出来
る。In this way, the buffering resin can be applied from the bottom side of the element.For example, after the element is runt, a method such as passing it over a roller containing the buffering resin can be used, and more automated equipment can be used. It can be used. This makes it possible to reduce system costs and improve yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の緩衝用樹脂を設けた樹脂封止型半導体装
置の断面図、第２図（−は本発明の第１の実施例を示す
断面図及び（ｂ）は平面図、第３図は本発明の第２の実
施例を示す断面図、第４図は本発明の第３の実施例を示
す断面図である。 １・・・・半導体素子、２・・・・素子マウント部、３
・・・・接続線、４・・・・緩衝用樹脂、５・・・・回
路面。 第２辺FIG. 1 is a sectional view of a resin-sealed semiconductor device provided with a conventional buffer resin, FIG. 2 is a sectional view showing a first embodiment of the present invention, and FIG. The figure is a cross-sectional view showing a second embodiment of the present invention, and Fig. 4 is a cross-sectional view showing a third embodiment of the present invention. 1... Semiconductor element, 2... Element mount section ,3
... Connection wire, 4 ... Buffer resin, 5 ... Circuit surface. Second side

Claims (1)

【特許請求の範囲】[Claims] 樹脂封止型半導体装置において、マウント部に接着され
専半導体素子の露出面のうち側面部の少なくとも対向す
る２餉面に封止樹脂応力に対する緩衝用樹脂を＊覆した
ことを特徴とする樹脂封止型半導体装置。In a resin-sealed semiconductor device, at least two opposing side surfaces of the exposed surfaces of the dedicated semiconductor element bonded to the mount portion are coated with a resin for buffering the stress of the sealing resin. Stop type semiconductor device.
JP56165334A 1981-10-16 1981-10-16 Resin seal type semiconductor device Pending JPS5867050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56165334A JPS5867050A (en) 1981-10-16 1981-10-16 Resin seal type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56165334A JPS5867050A (en) 1981-10-16 1981-10-16 Resin seal type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5867050A true JPS5867050A (en) 1983-04-21

Family

ID=15810353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56165334A Pending JPS5867050A (en) 1981-10-16 1981-10-16 Resin seal type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5867050A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2617668A1 (en) * 1987-07-03 1989-01-06 Radiotechnique Compelec Device comprising an electronic circuit mounted on a flexible support and flexible board comprising it
JP2012164697A (en) * 2011-02-03 2012-08-30 Mitsubishi Electric Corp Power module for electric power, and semiconductor device for electric power

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2617668A1 (en) * 1987-07-03 1989-01-06 Radiotechnique Compelec Device comprising an electronic circuit mounted on a flexible support and flexible board comprising it
JP2012164697A (en) * 2011-02-03 2012-08-30 Mitsubishi Electric Corp Power module for electric power, and semiconductor device for electric power

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