JPS5859764A - Lapping surface plate - Google Patents

Abstract

PURPOSE:To improve the lapping efficiency and reduce the frequency for correcting the lapping surface plate body and reduce the number of flaws formed on the ground surface of an article by forming radial grooves on the surface of the device itself. CONSTITUTION:Radial grooves 12 are formed on the body 11 of a lower lapping surface plate, in order to facilitate discharge of the free grinding grains and the grinding scrap which are sunk into the grooves 12 and reduce the generation rate of flaws on a semiconductor wafer. As the number of grooves on the lower lapping surface plate is reduced, the number of grinding grains sunk in the grooves 12 is reduced, and the number of grinding grains which contact the ground surface of the semiconductor wafer is increased, and the working time for lapping can be reduced. As radial grooves 12 are formed on the body 11' of the upper lapping surface plate and a grinding-grain feeding hole 13 is formed at the center of the grooves 12, the crossing part of the grooves is not formed, and generation of burr is eliminated in the grinding grain feeding hole 13, and generation of flaws on the semiconductor wafer can be reduced.

Description

【発明の詳細な説明】 本発明はラップ定盤の改良をこ関する。[Detailed description of the invention] The present invention relates to improvements in lap plates.

ラップ盤は工作物の表面を平らでなめらか（こ、かつ高
精度に仕上げるための機械である。例えば、半導体ウェ
ハの如く写真技術を応用してその表面に非常に微細なパ
ターンを転写する場合、表面に局所的な凹凸が存在する
と、転写されるパターンが像ぼけを生じ、これが製造さ
れる半導体素子の性能に悪影響を及ぼす。したがって、
非常に高精度の表面が要求され、表４面仕上げの一工程
としてラッピングが行われる。A lapping machine is a machine that finishes the surface of a workpiece flat, smooth, and with high precision. For example, when applying photographic technology to transfer a very fine pattern onto the surface of a semiconductor wafer, The presence of local irregularities on the surface causes image blurring of the transferred pattern, which adversely affects the performance of the manufactured semiconductor device.
Extremely high-precision surfaces are required, and lapping is performed as a step in finishing the four surfaces.

例えば半導体ウェハの両面ラッピングを行う場合、下ラ
ップ定盤の中央開孔に下ラップ定盤と連動する回転軸を
挿入し、下ラップ定盤上にウェハ設置孔を有するウェハ
キャリアを載置し、ウェハ設置孔にウェハを設置し、さ
らにその上に上ラップ定盤を載置した状態で上ラップ定
盤の砥粒供給孔から砥粒を供給しながら回転軸と連動し
た下ラップ定盤を回転させてラッピングを行う。For example, when performing double-sided lapping of semiconductor wafers, a rotating shaft that interlocks with the lower lap surface plate is inserted into the central opening of the lower lap surface plate, and a wafer carrier having a wafer installation hole is placed on the lower lap surface plate. The wafer is installed in the wafer installation hole, and the upper lap surface plate is placed on top of it. While supplying abrasive grains from the abrasive grain supply hole of the upper lap surface plate, the lower lap surface plate linked to the rotating shaft is rotated. and then wrap it.

ところで、従来ラッピングには例えば第１図に示す如き
構造の下ラップ定盤が用いられている。第１図中Ｊは定
盤本体で、この本体Ｊの表面には遊離砥粒や研摩屑を排
出するための溝２・・・が格子状に多数本設けられてい
る。By the way, conventionally, for lapping, a lower lapping surface plate having a structure as shown in FIG. 1, for example, has been used. J in FIG. 1 is a surface plate main body, and the surface of this main body J is provided with a large number of grooves 2 in a lattice pattern for discharging free abrasive grains and polishing debris.

しかしながら、従来の下ラップ定盤を用いてラッピング
を行った場合、溝２・・が格子状ζこ設けられているた
め、溝２・・・に入った遊離砥粒や研摩屑が定盤外へ排
出されに＜＜、これらが原因となって被研摩物の研摩面
にキズが発生しゃすい。また、同様に定盤本体りにもキ
ズが発生しやすいため、定盤本体りの修正を頻繁に行わ
なければならない。また、溝数が多いため溝２・・・に
入る砥粒が多く、被研摩物の研摩面と接触する砥粒は少
なくなるので、ラッピングの効率が悪いという欠点があ
る。さらに、下ラップ定盤と同様の溝を有する上ラップ
定盤において、砥粒供給孔が溝の交差部ζこ穿設された
場合、パリが発生しやすいため被研摩物の研摩面にキズ
が発生しやすく、このパリを取り除くために上ラップ定
盤の修正を行う必要がある。However, when lapping is performed using a conventional lower lapping surface plate, the grooves 2... are provided in a grid pattern, so loose abrasive grains and abrasive debris that have entered the grooves 2... are removed from the surface plate. These are likely to cause scratches on the polished surface of the object to be polished. In addition, the surface plate body is also susceptible to scratches, so the surface plate body must be repaired frequently. In addition, since there are many grooves, many abrasive grains enter the grooves 2, etc., and fewer abrasive grains come into contact with the polished surface of the object to be polished, so there is a drawback that lapping efficiency is poor. Furthermore, if the abrasive grain supply hole is drilled at the intersection of the grooves on the upper lap surface plate which has the same grooves as the lower lap surface plate, burrs are likely to occur and the polished surface of the object to be polished will be scratched. This is likely to occur, and it is necessary to modify the upper lap surface plate to remove this burr.

本発明は上記里悄に鑑みてなされたものであり、定盤本
体の修正回数を少なくシ、ラッピングの効率をよくする
とともに、被研摩物の研摩面に発生するキズを減少させ
て良質の被研摩物を得ることができるラップ定盤を提供
しようとするものである。The present invention was made in view of the above-mentioned problems, and it reduces the number of corrections of the surface plate body, improves lapping efficiency, and reduces scratches on the polished surface of the object to be polished, thereby producing a high-quality coating. The object of the present invention is to provide a lapping surface plate that can obtain an abrasive object.

以下本発明の実施例を図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.

第２図（ａｌに示す如く、下ラップ定盤は定盤本体１１
ζこ直線状の溝Ｊ２・・・を放射状に多数本設けた構造
になっている。また、第２図［有］）に示す如く、上ラ
ップ定盤は下ラップ定盤と同様に定盤本体、シＪ′に直
線状の溝１２・・・を放射状に多数本設け、さらに砥粒
供給孔１３・・を複数個穿設した構造になっている。As shown in Figure 2 (al), the lower lap surface plate is located at the surface plate body 11.
It has a structure in which a large number of straight grooves J2... are provided radially. In addition, as shown in Fig. 2, the upper lap surface plate, like the lower lap surface plate, has a large number of linear grooves 12 radially formed in the surface plate body and the surface J', and is further polished. It has a structure in which a plurality of grain supply holes 13 are bored.

上述した構造のラップ定盤を用いて半導体ウェハの両面
ラッピングを行うことにより、以下の如き効果を有する
。By performing double-sided lapping of a semiconductor wafer using the lapping platen having the above-described structure, the following effects can be obtained.

（１）下ラップ定盤において溝１２・・・を放射状ζこ
設けたことにより、溝１２・・ｌこ入った遊離砥粒や研
摩屑が定盤外に排出されやすくなり、半導体ウェハのキ
ズ発生率が５０％減少し、また定盤本体１１の修正回数
が１／２以下となった。(1) By providing the grooves 12 radially in the lower lap surface plate, free abrasive grains and abrasive debris contained in the grooves 12 can be easily discharged outside the surface plate, thereby preventing scratches on the semiconductor wafer. The occurrence rate has been reduced by 50%, and the number of corrections to the surface plate body 11 has been reduced to less than 1/2.

（２）下ラップ定盤において溝数が少なくなったことに
より、溝１２・・に入る砥粒が少なく、半導体ウェハの
研摩面に接触する砥粒が多くなったため、ラッピングの
作業時間が２０％短縮でき、また砥粒を節減することが
でき、さらに、溝１２・・の加工に必要な費用が１５係
安価となった。(2) Due to the reduced number of grooves on the lower lapping surface plate, fewer abrasive grains enter the grooves 12, and more abrasive grains come into contact with the polished surface of the semiconductor wafer, which reduces the lapping work time by 20%. The length can be shortened, the amount of abrasive grains can be reduced, and the cost required for processing the grooves 12 has been reduced by 15%.

（３）上ラップ定盤において定盤本体す′の溝１２′・
・・ζこは交差部がなくなり、砥粒供給孔１３・・・が
すべで溝１２′・・の中央に穿設されることにより、砥
粒供給孔１３・・にパリの発生が少なくなったため、半
導体ウェハのキズの発生が減少し、定盤本体、し」′の
修正回数も減少した。(3) Groove 12' on the surface plate body in the upper lap surface plate.
...ζ has no intersection, and the abrasive grain supply holes 13... are all drilled in the center of the grooves 12', which reduces the occurrence of paris in the abrasive grain supply holes 13. As a result, the occurrence of scratches on semiconductor wafers has been reduced, and the number of corrections to the surface plate body has also been reduced.

なお、本発明に係るラップ定盤は第２図（ａ）。The lap surface plate according to the present invention is shown in FIG. 2(a).

（ｂｌに示すものに限らす、第３図に示す如く曲線状の
溝Ｊ　２’・・・を放射状に多数本設けた下ラップ定盤
、あるいは第４図に示す如く外周から内周にまで達する
直線状の溝１２・・・及び外周から内周にまで達しない
直線状の溝１２〃・・・を交互にがつ放射状に多数本設
けた下ラップ定盤でもよい。(Limited to those shown in bl, lower lap surface plate with many curved grooves J2'... radially provided as shown in Fig. 3, or extending from the outer periphery to the inner periphery as shown in Fig. 4) A lower lap surface plate may be used, in which a large number of straight grooves 12 extending from the outer circumference to the inner circumference and a plurality of linear grooves 12 extending from the outer circumference to the inner circumference are provided alternately in a radial manner.

また、本発明ζこ係るラップ定盤は上Ｒｅ実施例の如く
両面ラッピングのみに限らず、片面ラッピングにも同様
に適用できる。Further, the lapping surface plate according to the present invention is not limited to double-sided lapping as in the above Re embodiment, but can be similarly applied to single-sided lapping.

以上詳述した如く本発明によれば、定盤本体の修正を少
なくシ、ラッピングの効率をよくするとともに、被研摩
物の研摩面に発生ずるキズを減少させて良質の被研摩物
を得ることができるラップ定盤を提供できるものである
。As described in detail above, according to the present invention, it is possible to reduce corrections to the surface plate body, improve lapping efficiency, and reduce scratches on the polished surface of the object to be polished, thereby obtaining a high-quality object to be polished. It is possible to provide a lap surface plate that can perform

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の下ラップ定盤を示す平面図、第２図伸１
．（ｂｌは本発明の一実施例に係る下ラッラツブ定盤を
示す平面図である。　。 〕−７，７ノ′・・・定盤本体、１２，１２′、１２″
・清、１３・・・砥粒供給孔。 出願人代理人　弁理士　鈴　江　武　彦第３図 第４図 １ １Figure 1 is a plan view showing the conventional lower lap surface plate, Figure 2
．． (bl is a plan view showing a lower rack surface plate according to an embodiment of the present invention.) -7, 7'... Surface plate main body, 12, 12', 12''
- Clear, 13...Abrasive grain supply hole. Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 4 1 1

Claims (1)

【特許請求の範囲】[Claims] 定盤本体の表面に放射状の溝を設けたことを特徴とする
ラップ定盤。A lap surface plate characterized by having radial grooves on the surface of the surface plate body.