JPS5859238U

JPS5859238U - Analog to digital converter

Info

Publication number: JPS5859238U
Application number: JP15320181U
Authority: JP
Inventors: 美昭田中; 稲見　衛; 大槻　善樹
Original assignee: 日本ビクター株式会社
Priority date: 1981-10-15
Filing date: 1981-10-15
Publication date: 1983-04-21

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

一第１図は本考案になるアナログ・デジタル変換器の第
１実施例の回路図、第２図Ａ−Ｅは第１図示の回路の各
部の信号波形図、第３図はコンデンサの放電時間と平均
値レベルの関係を示す図、第４図は放電時定数と基準電
圧の関係を示す図、第５図は本考案の第２実施例の回路
図、第６図Ａ〜Ｄは第５図示の回路の各部の信号波形図
である。１、　２．　２’、　　５．　７・・・・・・入力端子
、３・・・・・・コンピュータ、４．　６．　９・・・
・・・オペアンプ、８・・・・・・出力端子、１０・・
・・・・基準電圧発生器、Ｃ□〜Ｃ１・・・・・・コン
デンサ、Ｄ１〜Ｄ６・・・・・・ダイオード、Ｑ１〜Ｑ
５・・・・・、ＦＥＴ、　Ｒ１〜Ｒ□４・・・・・・、
抵抗、ＶＲ・・・・・・可変抵抗。Fig. 1 is a circuit diagram of the first embodiment of the analog-to-digital converter according to the present invention, Fig. 2 A to E are signal waveform diagrams of various parts of the circuit shown in Fig. 1, and Fig. 3 is the discharge time of the capacitor. 4 is a diagram showing the relationship between the discharge time constant and the reference voltage, FIG. 5 is a circuit diagram of the second embodiment of the present invention, and FIGS. FIG. 3 is a signal waveform diagram of each part of the illustrated circuit. 1, 2. 2', 5. 7...Input terminal, 3...Computer, 4. 6. 9...
...Operational amplifier, 8...Output terminal, 10...
...Reference voltage generator, C□~C1...Capacitor, D1~D6...Diode, Q1~Q
5..., FET, R1~R□4......,
Resistance, VR...Variable resistance.

Claims

【実用新案登録請求の範囲】[Scope of utility model registration request]

（１）被測定交流信号を整流し、該整流した信号をコン
デンサ及び抵抗により平滑して該コンデンサを該整流し
た信号の平均電圧まで充電し、該コンデンサの両端電圧
を基準電圧と比較しつつ該コンデンサを指数関数的に放
電させ、該放電の開始時より該コンデンサの両端電圧が
該基準電圧となるまでの時間を計数して該整流した信号
の平均電圧の対数のデジタル値を得るよう構成したアナ
ログ・デジタル変換器。(1) Rectify the AC signal to be measured, smooth the rectified signal with a capacitor and resistor, charge the capacitor to the average voltage of the rectified signal, and compare the voltage across the capacitor with the reference voltage. The capacitor is discharged exponentially, and the time from the start of the discharge until the voltage across the capacitor reaches the reference voltage is counted to obtain a digital value of the logarithm of the average voltage of the rectified signal. Analog to digital converter.

（２）該コンデンサを指数関数的に放電させる時定数と
該基準電圧とを共に切換えるよう構成した実用新案登録
請求の範囲第１項記載のアナログ・デジタル変換器。、(2) The analog-to-digital converter according to claim 1, which is configured to switch both the reference voltage and the time constant for exponentially discharging the capacitor. ,

（３）該被測定交流信号の整流は演算増幅器を用いて行
なわれ該コンデンサの電圧が該演算増幅器〜に帰還しないよう構成した実用新案登録請求の範囲第１
項又は第２項記載のアナログ・デジタル変換器。(3) The AC signal to be measured is rectified using an operational amplifier, and the voltage of the capacitor is configured so as not to be fed back to the operational amplifier.
The analog-to-digital converter according to item 1 or 2.