JPS5856437A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5856437A
JPS5856437A JP15520381A JP15520381A JPS5856437A JP S5856437 A JPS5856437 A JP S5856437A JP 15520381 A JP15520381 A JP 15520381A JP 15520381 A JP15520381 A JP 15520381A JP S5856437 A JPS5856437 A JP S5856437A
Authority
JP
Japan
Prior art keywords
film
layer
oxidation
silicon nitride
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15520381A
Other languages
Japanese (ja)
Inventor
Yoshitaka Sasaki
芳高 佐々木
Minoru Taguchi
実 田口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15520381A priority Critical patent/JPS5856437A/en
Publication of JPS5856437A publication Critical patent/JPS5856437A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain a highly integrated semiconductor device by suppressing the production of a bird beak or bird head at the thermally oxidizing time, thereby forming a ultrafine element isolating layer having small pattern conversion difference. CONSTITUTION:When a silicon nitrided film 113' is allowed to remain by reactive etching in a self-aligning manner on the inside surface of grooves 110,..., the first silicon nitrided film 104 is not, since a polycrystalline silicon film 105 and an annular oxidized film 108,... become etching masks, entirely etched. The films 105, 108,... are removed, thereby allowing to remain the film 104 having a thickness on an n type epitaxial layer 103 at the initial accumulation time. Accordingly, an npn type bipolar integrated circuit in which the pattern conversion difference suppressed with a bird beak, bird head due to thermal oxidation is reduced, and an element isolating layer 116 being substantially the same level as an n type silicon epitaxial layer 103 is provided can be obtained.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関し、特に素子分離領
域の形成工程を改良した半導体装置の製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which the process for forming element isolation regions is improved.

半導体集積回路は容量の増大、機能の多様化によシ増々
大規模化する傾向にあシ、これに伴なって素子の微細化
は３μｍ、２μｍついにはすシミクロンの寸法にすると
とが要求されている。Semiconductor integrated circuits tend to become larger and larger due to increased capacity and diversification of functions, and along with this, there is a demand for miniaturization of elements down to 3 μm, 2 μm, and finally to the symicron size. ing.

ところで、上述の微細化に不可欠な技術として素子間を
誘電体に゛よシ分離する技術があシ、その一つとして従
来から選択酸化技術が行なわれている。しかして２、選
択酸化技術にょるｎｐｎパイ／−２里集積回路の製造す
る方法を第１図（、）〜（、）を参照して以下に説明す
る。By the way, as a technique essential to the above-mentioned miniaturization, there is a technique of separating elements using a dielectric material, and one of these techniques has been a selective oxidation technique. 2. A method of manufacturing an npn pi/-2 li integrated circuit using selective oxidation technology will be described below with reference to FIGS.

（１）　　ｔず、ｐ型シリコン基板１の主面にｎ＋埋込
み層２・・・を選択的に形成し、エピタキシャル法によ
［ｎ型エピタキシャル半導体層３を成長させた後、エピ
タキシャル半導体層３表面に熱酸化によシ下地。酸化膜
４を成長させ、更にシリコン窒化膜５を増稠する。つづ
いて、これら膜５．４の素子分離領域の形成予定部に開
孔窓６を写真蝕刻法によシ選択的に形成する（第１図（
ａ）図示）１、 （２）　　次いで、シリコン窒化膜５及び下地酸化膜４
をマスクとして露出した！Ｉｍエピタキシャル半導体層
３を選択的にエッチｙダ除去して溝部７を形成した後、
同シリコン窒化膜５及び下地酸化膜４をマスクとしてゾ
ロンをイオン注入し溝部１底部のｎ型エピタ中シャル半
導体層３付近に？ロンイオ、ン注入層８を形成した（第
１図（ｂ）図示）。(1) First, an n+ buried layer 2 is selectively formed on the main surface of a p-type silicon substrate 1, and then an n-type epitaxial semiconductor layer 3 is grown by an epitaxial method. Thermal oxidation is applied to the surface. An oxide film 4 is grown, and a silicon nitride film 5 is further thickened. Subsequently, opening windows 6 are selectively formed in the portions of these films 5.4 where the element isolation regions are to be formed by photolithography (see FIG.
a) As shown) 1, (2) Next, silicon nitride film 5 and base oxide film 4
exposed as a mask! After selectively etching and removing the Im epitaxial semiconductor layer 3 to form the groove portion 7,
Using the same silicon nitride film 5 and base oxide film 4 as a mask, zolon is ion-implanted into the n-type epitaxial semiconductor layer 3 at the bottom of the trench 1. A ion-implanted layer 8 was formed (as shown in FIG. 1(b)).

（３）次いで、シリコン鼠化膜５を耐酸化性マスクとし
て高温ウェット雰囲気中で熱酸化処理し、溝部１部分を
選択酸化して酸化膜分離層９を形成した。この時、第１
図（ｃ）に示す如＜、Ｓロンイオン注入層８が拡散して
同分離層９底部にｒ型反転防止層１０が形成された。つ
づいて、シリコン窒化膜５及び下地酸化膜４を除去した
後、図示しな−が常法に従って酸化膜分離層９で分離さ
れた島状の１屋工ピタキシヤル半導体層３にｐ型のベー
ス領域を形成し、更に同ペース領域内に？型工ず、夕領
域、エピタキシャル層３に？型コレクタ取出し領域を形
成してｎｐｎバイポーラ集積回路を製造する。(3) Next, thermal oxidation treatment was performed in a high temperature wet atmosphere using the silicon dot oxide film 5 as an oxidation-resistant mask, and the groove portion 1 portion was selectively oxidized to form the oxide film separation layer 9. At this time, the first
As shown in Figure (c), the Sron ion-implanted layer 8 was diffused to form an r-type inversion prevention layer 10 at the bottom of the isolation layer 9. Subsequently, after removing the silicon nitride film 5 and the underlying oxide film 4, a p-type base region (not shown) is formed on the island-shaped pitaxial semiconductor layer 3 separated by an oxide film separation layer 9 in accordance with a conventional method. Formed and further within the same pace area? Mold work, evening region, epitaxial layer 3? A mold collector extraction region is formed to manufacture an npn bipolar integrated circuit.

しかしながら、上述した選択酸化法にあっては、高温酸
化を長時間行なう必要から、シリコン窒化膜６下に設け
られた窒化膜に起因するオキシナイトライドの生成防止
を目的とする下地酸化Ｍ４を介して横方向に酸化が進行
する、ｉわゆるサイド酸化が起こシ、第１図（Ｃ）に示
す如くバードビーク１１やバードヘッド１２を生じる。However, in the above-mentioned selective oxidation method, since it is necessary to carry out high-temperature oxidation for a long time, the base oxidation M4 is performed for the purpose of preventing the formation of oxynitride caused by the nitride film provided under the silicon nitride film 6. As a result, oxidation progresses in the lateral direction, so-called side oxidation, resulting in bird's beaks 11 and bird's heads 12 as shown in FIG. 1(C).

バードビーク１１の発生は島状の素子領域の縮小化につ
ながるばかシか、同素子領域のパターン変換誤差が大き
く、なった〕、写真蝕刻法による開口窓のノ々ターン精
度の悪化、微細な開口窓の形成困難等を一招いたシする
。前記・櫂−ドヘッドの発生は、ｎ型工ｆタキシャル半
導体層３表面の１段差となシ、配線の断切れにつながる
欠点がある。また、溝部１の側面が深さ方向と分の２倍
の幅となシ、１前述のパードーーりに加えて更に集積度
低下を招く。更に素子特性にも著し埴悪影響を及ぼす。The occurrence of bird beak 11 is due to the reduction of the island-shaped element area, or the pattern conversion error in the element area becomes large], the deterioration of the no-turn accuracy of the aperture window by photolithography, and the fine aperture. This may lead to difficulties in forming the window. The occurrence of the paddle head is caused by a one-step difference in the surface of the n-type taxial semiconductor layer 3, which has the drawback of leading to disconnection of the wiring. Moreover, if the side surface of the groove part 1 is twice as wide as the width in the depth direction, in addition to the above-mentioned parity, the degree of integration is further reduced. Furthermore, it has a significant negative effect on device characteristics.

例えば、シリコン雪化ｗＸ５を耐酸化性マスクとして高
温酸素雰囲気中で熱酸化処理すると、シリ″：１ｙ窒化
膜５とエピタキシャル半導体層Ｓ等とのストレ不発生、
熱酸化中でのｎ型エピタキシャル半導体層３等への熱歪
による０−８−Ｆ　（０ｘｉｄａｔｉｏｎ　Ｉｎｄｕｅ
＠ｄＳｔａｅｋｌｎｇ　Ｆａｕｌｔｓ　）等の結晶欠陥
が分離層９．周囲のｎ型エピタキシャル半導体層３等に
発生し、素子特性を著しく劣化させる。For example, when thermal oxidation treatment is performed in a high-temperature oxygen atmosphere using silicon snow plating wX5 as an oxidation-resistant mask, no stress occurs between the silicon '':1y nitride film 5 and the epitaxial semiconductor layer S, etc.
0-8-F due to thermal strain on the n-type epitaxial semiconductor layer 3 etc. during thermal oxidation.
Crystal defects such as @dStaeklng Faults) occur in the separation layer 9. This occurs in the surrounding n-type epitaxial semiconductor layer 3, etc., and significantly deteriorates the device characteristics.

そこで、上記問題を改善する方法として、たとえばＩＢ
Ｍ　Ｔ＠ｅｈｎｉｃａｌ　Ｄｉｓｃｌｏｓｕｒ＠Ｂｕｌ
ｌｅｔｉｎ　Ｍｏ１．２２　Ａ７　、Ｄｅｃ＠ｄ＊ｒ　
１９．７９７が提案されている。この方法を第２図＜＆
）〜（ｄ）　を参照して説明する。Therefore, as a way to improve the above problem, for example, IB
M T@ehnical Disclosure@Bul
letin Mo1.22 A7, Dec@d*r
19.797 has been proposed. This method is shown in Figure 2.
) to (d).

まずｐ型シリコン基板１にｎ＋！込み層２ｔ−形成後、
その上Ｋｎ型エピタキシャル半導体層３を成長させ、表
面に約１００Ｘ程度の下地酸化ａ４を形成する。その後
約１０００１程度の第１シ、リコン窒化膜５ｔ−堆積後
、所望のシリコン窒化膜と下地酸化膜′を開口し、表面
に露出したｍＷエピタキシャル半導体層を工オチンクス
ルことによって、溝部１と、シリコン窒化膜５のひさ、
し構造管形成する〔第２図（ａ）図示〕。次に熱酸化処
理を施し、該溝部１周囲に酸化膜１３を約１００Ｘ程度
形成する。しかる後、再度全体に第２シリコン窒化膜１
４を堆積させた後、前記第１シリコン窒化膜５のひさし
をマスクにしてリアクティゾイオンエッチングによって
溝部７底部の第２シリコン窒化膜１４を自己整合的に除
去する、〔第２図（ｂ）図示〕、このように溝部７の側
壁に自己整合的に窒化膜を形成した後、必要に応じてＣ
型不純物イオンを溝部７底部の半導体基板１に打ちこむ
、続いて熱酸化処理を施すことによって溝部１には酸化
膜分離層９′が形成されると共に、ｐ１反転防止層１σ
が上記酸化熱工程によって形成される〔第２図（Ｃ）図
示す〕、その後第１シリコン窒化膜５、第２シリコン窒
化膜１４ならび下地酸化膜４を工。First, n+! on the p-type silicon substrate 1! After forming the embedding layer 2t,
Thereon, a Kn type epitaxial semiconductor layer 3 is grown, and a base oxide a4 of about 100X is formed on the surface. Thereafter, after depositing a first silicon nitride film 5t of about 10,000 ml, a desired silicon nitride film and base oxide film' are opened, and the mW epitaxial semiconductor layer exposed on the surface is etched to form a trench 1 and a silicon nitride film 5t. The roof of the nitride film 5,
Then, a structural tube is formed (as shown in FIG. 2(a)). Next, a thermal oxidation process is performed to form an oxide film 13 of about 100X around the groove 1. After that, a second silicon nitride film 1 is applied over the entire surface again.
4, the second silicon nitride film 14 at the bottom of the trench 7 is removed in a self-aligned manner by reactive ion etching using the eaves of the first silicon nitride film 5 as a mask [FIG. ) As shown], after forming the nitride film in a self-aligned manner on the sidewalls of the trench 7, C.
By implanting type impurity ions into the semiconductor substrate 1 at the bottom of the trench 7 and then performing thermal oxidation treatment, an oxide film separation layer 9' is formed in the trench 1, and a p1 inversion prevention layer 1σ is formed.
is formed by the above-mentioned oxidation thermal process [as shown in FIG. 2(C)], and then the first silicon nitride film 5, the second silicon nitride film 14, and the base oxide film 4 are formed.

チング除去する（第２図（ｄ）図示）。Remove the tingling (as shown in FIG. 2(d)).

しかして、上記方法では、溝部７の側面にＲＩＫによっ
て耐酸化性絶縁膜である第２シリコン窒化膜１４を自己
整合的に形成することにより、前記溝部７の横方向への
酸化の拡シを少なくできる。つまυ酸化剤は溝部７の底
部の窒化膜開口部から浸入し、溝部２の底部に厚い酸化
膜を形成するとともに、第２シリコン窒化膜１４の酸化
膜１３に沿って酸化剤が浸入するためそこに形成される
酸化膜が、前記第２シリコン窒化腺１４ｙｆｒ押し上げ
、ちょうど溝部１の表面まで酸化膜分離層ｑが形成され
る。このため、ｎ型エピタキシャル半導体層３表面とほ
ぼ平坦で、バード・ピークの小さい酸化膜分離層９′が
形成できる。しかし、かかる方法においては、第２図ｃ
ｂ＞において、シリコン窒化膜１４を溝部１の側面にＲ
，１，１，で自己整合的に形成する際、半導体層３表面
のシリコン窒化膜５も同時にエツチングされてなくなっ
てしまうか、あるいは極薄く残る場合がある。このシリ
コン窒化膜３は、溝部７へ選択的に形成する酸化膜分離
層９′のマスク材であり、膜厚が大きければバード・ピ
ークの小さい酸化膜分離層が形成できる。その反面、前
記シリコン窒化膜５の膜厚を大きくすると、該シリコン
窒化膜５の下のｎ型エピタキシャル半導体層３に結晶欠
陥が起シやずいという相対する現象が生じる。友とえば
分離層の深さがｌ＃１程度の場合、シリコン窒化膜５は
約１０００Ｘ、下地酸化膜４は１００Ｋの膜厚にするこ
とが良いとされている。以上のことから第２図（ｂ）に
おけるシリコン窒化膜５＃−ｉ、溝部７の側面にシリコ
ン窒化膜１４を形成する際、ある−足の膜厚を保たなけ
ればガらない。However, in the above method, the second silicon nitride film 14, which is an oxidation-resistant insulating film, is formed on the side surface of the trench 7 in a self-aligned manner by RIK, thereby preventing the oxidation from spreading in the lateral direction of the trench 7. You can do less. The oxidizing agent intrudes from the nitride film opening at the bottom of the groove 7 and forms a thick oxide film at the bottom of the groove 2, and at the same time, the oxidizing agent infiltrates along the oxide film 13 of the second silicon nitride film 14. The oxide film formed there pushes up the second silicon nitride gland 14yfr, and an oxide film separation layer q is formed just up to the surface of the groove portion 1. Therefore, it is possible to form an oxide film separation layer 9' that is substantially flat with the surface of the n-type epitaxial semiconductor layer 3 and has a small bird peak. However, in such a method, FIG.
b>, the silicon nitride film 14 is formed on the side surface of the trench 1 with R.
, 1, 1 in a self-aligned manner, the silicon nitride film 5 on the surface of the semiconductor layer 3 may also be etched away at the same time, or may remain extremely thin. This silicon nitride film 3 is a mask material for an oxide film separation layer 9' selectively formed in the groove portion 7, and if the film thickness is large, an oxide film separation layer with a small bird peak can be formed. On the other hand, when the thickness of the silicon nitride film 5 is increased, the opposite phenomenon occurs in that crystal defects occur in the n-type epitaxial semiconductor layer 3 under the silicon nitride film 5. For example, when the depth of the separation layer is about l#1, it is said that it is good to make the silicon nitride film 5 about 1000X thick and the base oxide film 4 about 100K thick. From the above, when forming the silicon nitride film 5#-i and the silicon nitride film 14 on the side surfaces of the groove portion 7 in FIG. 2(b), damage will occur unless the film thickness is maintained at a certain level.

しかし、現在のＲＩＥのエツチングレートは、５００１
〜１０００　Ｘ／ｌｉｎで、さらにウエノ１内のばらつ
きが大きくことから、エピタキシャル半導体層３上のシ
リコン窒化１１［ｆｆを均一膜厚で、かつある膜厚内（
例えば１０００Ｘ±１０％）にとどめることは量産的に
は難しい。However, the current RIE etching rate is 5001
~ 1000
For example, it is difficult for mass production to limit the value to 1000X±10%).

本発明は上記問題点を解消するためになされたもので、
パーｒ・ピークを抑制してノターン変換差の小さい高集
積度化が可能な素子分離層を有する半導体装置の製造方
法を提供しようとするものである。The present invention was made to solve the above problems, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device having an element isolation layer that suppresses the Par-r peak and allows for high integration with small no-turn conversion differences.

すなわち、本発明は一導電型の半導体層もしくは半導体
基板上に、第１の耐酸化性絶縁膜、非単結晶半導体膜及
び第２の耐酸化性絶縁膜を順次形成する工程と、第２の
耐酸化性絶縁膜と非単結″６半導体膜を少なくとも１箇
所以上開口する工程と、この開口部内側面に露出する非
単結晶半導体膜部分を選択的に熱酸化して酸化膜を形成
する工程と、開口部内側面に形成された酸化膜をマスク
として該開口部から露出する第１の耐酸化性絶縁膜をエ
ツチングして前記三層膜に開口窓全形成する工程と、前
記第２の耐酸化性絶縁膜をマスクとして開口窓から露出
する半導体層もしくは半導体基板をエツチングして溝部
を形成すると共に、該溝部の開口に前記三層膜をひさし
状に延出する工程と、この溝部を含む全面に第３の耐酸
化性絶縁膜を形成する工程と、前記第２の耐酸化性絶縁
膜又は前記開口窓の内側面の一部に形成された酸化膜を
マスクとして前記溝部の底部一部の第３の絶縁膜をエツ
チングして該溝部の底部一部の半導体層もしくは半導体
基板を露出させる工程と、熱酸化処理を施して前記溝部
を酸化体で埋設することによシ、素子分離層を形成する
工程とを具備し次ことを特徴とするものである。That is, the present invention includes a step of sequentially forming a first oxidation-resistant insulating film, a non-single crystal semiconductor film, and a second oxidation-resistant insulating film on a semiconductor layer or semiconductor substrate of one conductivity type; A step of opening an oxidation-resistant insulating film and a non-single-crystal semiconductor film at least at one location, and a step of selectively thermally oxidizing a portion of the non-single-crystal semiconductor film exposed on the inner surface of this opening to form an oxide film. etching the first oxidation-resistant insulating film exposed from the opening using the oxide film formed on the inner surface of the opening as a mask to form the entire opening window in the three-layer film; forming a groove by etching the semiconductor layer or semiconductor substrate exposed through the opening window using a chemical-containing insulating film as a mask, and extending the three-layer film in the shape of an eaves into the opening of the groove; forming a third oxidation-resistant insulating film on the entire surface; and forming a part of the bottom of the groove using the second oxidation-resistant insulating film or an oxide film formed on a part of the inner surface of the opening window as a mask. By etching the third insulating film to expose a part of the semiconductor layer or semiconductor substrate at the bottom of the trench, and by performing thermal oxidation treatment to fill the trench with an oxidant, the device isolation layer is removed. The method is characterized by the following features:

本発明における第１の耐酸化性絶縁膜は選択酸化時に半
導体層もしくは半導体基板が酸化されるのを防止すると
共に、バード・ピークの発生を抑制する役目をする。か
かる第１の耐酸化性絶縁膜としては、例えばシリコン窒
化膜、アルミナ膜等を挙げることができる。The first oxidation-resistant insulating film in the present invention serves to prevent the semiconductor layer or the semiconductor substrate from being oxidized during selective oxidation, and also serves to suppress the occurrence of bird peaks. Examples of the first oxidation-resistant insulating film include a silicon nitride film and an alumina film.

本発明における非単結晶半導体膜は第１の耐酸化性絶縁
膜の保護するために用いられる。また、半導体膜の開口
後の熱酸により該開口内側面に形成する酸化膜は、半導
体層もしくは半導体基板に溝部を形成する際、該非晶質
半導体膜が工、チングされるのを阻止するために用いら
れる。かかる非単結晶半導体膜としては、例えば多結晶
シリコン膜、メロン、燐、砒素等の不純物を含む多結晶
シリコン膜、非晶質シリコン膜、或いはタングステンシ
リサイｒ１モリブデンシリサイドなどの金属シリサイド
膜等を挙げることができる。The non-single crystal semiconductor film in the present invention is used to protect the first oxidation-resistant insulating film. Furthermore, an oxide film formed on the inner surface of the opening by hot acid after opening the semiconductor film is used to prevent the amorphous semiconductor film from being etched or etched when forming a groove in the semiconductor layer or semiconductor substrate. used for. Examples of such a non-single crystal semiconductor film include a polycrystalline silicon film, a polycrystalline silicon film containing impurities such as melon, phosphorus, and arsenic, an amorphous silicon film, or a metal silicide film such as tungsten silicide r1 molybdenum silicide. can be mentioned.

本発明における第２の耐酸化性絶縁膜は半導体層もしく
は半導体基板に溝部を形成する際のマスクとして作用す
ると共に、非単結晶半導体膜を保護する役目をする。The second oxidation-resistant insulating film in the present invention acts as a mask when forming a groove in a semiconductor layer or a semiconductor substrate, and also serves to protect the non-single crystal semiconductor film.

次に１本発明をｎｐｎバイプーラ集積回路の製造に適用
した例について第３図（１）〜伽）を参照して説明する
。Next, an example in which the present invention is applied to the manufacture of an npn bipolar integrated circuit will be described with reference to FIGS. 3(1) to 3).

実施例 〔１〕まず、ｐｍシリコン基板１０１の主面Ｋｎ＋埋込
み層２０２＠ｈ１０２鵞、１０２．−・・を選択的に形
成し、エピタキシャル成長法によりｎ型のシリ逼ンエビ
タキシャル層１０３を成長させた。つづいて、熱酸化処
理を施してエピタキシャル層１０３表面に例えば厚さ１
００Ｘの下地酸化膜（図示せず）を形成し、更にこの下
地酸化膜上にＣＶＤ法にょシ例えば厚さ１ｏｏｏＸの第
１のシリコン窒化膜１０４、厚さ５００Ｘの多結晶シリ
コン膜１０５及び厚さ２０００〜２５００Ｘの第２のシ
リコン窒化膜１０６を順次堆積した後、第２のシリコン
窒化膜１０６の素子分離層形成予定部をフォトエツチン
グ技術によ〕選択的にエツチングして開口を形成しｆｃ
（第３図（ａ）図示）。Example [1] First, the main surface Kn+buried layer 202@h102 of the pm silicon substrate 101, 102. -... were selectively formed, and an n-type silicon epitaxial layer 103 was grown by an epitaxial growth method. Subsequently, thermal oxidation treatment is applied to the surface of the epitaxial layer 103 to a thickness of, for example, 1.
A base oxide film (not shown) with a thickness of 00X is formed, and then a first silicon nitride film 104 with a thickness of 100X, a polycrystalline silicon film 105 with a thickness of 500X, and a polycrystalline silicon film 105 with a thickness of After sequentially depositing the second silicon nitride film 106 with a thickness of 2000 to 2500X, the portion of the second silicon nitride film 106 where the element isolation layer is to be formed is selectively etched using a photoetching technique to form an opening.
(Illustrated in FIG. 3(a)).

（ｉｉ）次いで、第２のシリコン窒化膜１０ｇをマスク
として開口から露出する多結晶シリコン膜１０５部分を
選択的にエツチング除去して開口部１０７を形成した後
、熱酸化処理した。この時、開口部１０７・・・の内側
面に露出する多結晶シリコン膜１０５部分が酸化されて
例えば幅１５００Ｘの環状の酸化膜１０８・・・が形成
された（第３図伽）図示）、つづいて、第２のシリコン
窒化Ｍ１０６及び酸化膜１０８・・・をマスクとして第
１のシリコン窒化１１１１０４及び下地酸化膜を選択的
に工、チングして前記四層膜に開孔窓１０９・・・を形
成したーこのエツチングに際して第２のシリコン窒化膜
１０６は第１−のシリコン窒化膜１０４の膜厚相当分（
１００ＯＸ程度）エツチングされる。ひきつづき、第２
のシリコン窒化膜１０６及び酸化膜１０８・・・をマス
クとして開孔窓１０Ｙから露出するｎ型シリコンエピタ
キシャル層１０３を選択エツチングして溝部１１０・・
・と、前記四層膜の庇部１１１を形成した（第３図（ｅ
）図示）。(ii) Next, using the second silicon nitride film 10g as a mask, the portion of the polycrystalline silicon film 105 exposed from the opening was selectively etched away to form an opening 107, followed by thermal oxidation treatment. At this time, the portion of the polycrystalline silicon film 105 exposed on the inner surface of the opening 107 is oxidized, and a ring-shaped oxide film 108 having a width of 1500X, for example, is formed (as shown in FIG. 3). Next, using the second silicon nitride M106 and oxide film 108 as a mask, the first silicon nitride 111104 and base oxide film are selectively etched to open windows 109 in the four-layer film. During this etching, the second silicon nitride film 106 has a thickness equivalent to that of the first silicon nitride film 104 (
100OX) is etched. Continuing, Part 2
The n-type silicon epitaxial layer 103 exposed from the opening window 10Y is selectively etched using the silicon nitride film 106 and oxide film 108 .
・The eaves portion 111 of the four-layer film was formed (see FIG. 3(e)
).

（ｉｉｉ）次いで、熱酸化処理を施して溝部１１０・・
・内側面に・例えば厚さ１００−、ｌの下地酸化膜（図
示せず）を形成した後、庇部１１１をマスクとして溝部
１１０・・・の底部にｐＷ不純物、例えばメロンをイオ
ン注入してｐ型反転防止層１１２・・・を形成した。つ
づ−て、溝部１１０・・・を含む全面に減圧ＣｖＤ法如
よｐ例えば厚さ３００＾のシリコン窒化膜を堆積した（
第３図（ｄ）図示）この時、溝部１１０・・・内側面の
下地酸化膜及び第２のシリコン窒化膜１０６上等に均一
厚の第３のシリコン窒化膜１１３が堆積された。(iii) Next, thermal oxidation treatment is performed to form the groove 110...
After forming a base oxide film (not shown) with a thickness of, for example, 100 mm on the inner surface, pW impurities such as melon are ion-implanted into the bottoms of the trenches 110 using the eaves 111 as a mask. A p-type anti-inversion layer 112... was formed. Next, a silicon nitride film having a thickness of, for example, 300^ is deposited on the entire surface including the grooves 110 by low pressure CvD method (
At this time, a third silicon nitride film 113 having a uniform thickness was deposited on the base oxide film and the second silicon nitride film 106 on the inner surface of the trench 110 (as shown in FIG. 3(d)).

Ｏ■〕次いで、庇部１１１をマスクにして溝部１１０・
・・底部の第３のシリコン窒化膜１１３及び下地酸化膜
をリアクティプイオンエ、チングして溝部１１０・・・
の内側面化シリコン窒化膜１１３′を残存させると共和
開孔１１４・・・を形成した。この工、チングに際して
オーバーエツチングすることにより、第２のシリコン窒
化膜Ｉθ６が工、チング除去されるが、その下の第１の
シリコン窒化膜１０４は多結晶シリコ７１１１０５及び
酸化膜１０８・・・で覆われているため、膜減りは防止
される（第３図（・）図示）、つづいて、多結晶シリコ
ン膜１０５及び酸化膜１０１１・・・を順次工、チング
除去した（８３図（ｆ）図示ン。O■] Next, using the eaves part 111 as a mask, the groove part 110 and
...The third silicon nitride film 113 at the bottom and the base oxide film are etched with reactive ion etching to form the trench 110...
When the inner surface-formed silicon nitride film 113' remained, common openings 114 were formed. By over-etching during this etching, the second silicon nitride film Iθ6 is etched and removed, but the first silicon nitride film 104 underneath it is made up of polycrystalline silicon 711105 and oxide film 108... Since the polycrystalline silicon film 105 and the oxide film 1011 are covered, film reduction is prevented (as shown in Fig. 3(-)).Next, the polycrystalline silicon film 105 and the oxide film 1011... are sequentially etched and removed (Fig. 83(f)). Illustrated.

〔■〕次いで、熱酸化処理を施し九、この時、酸化剤は
溝部１１０・・・底部の残存シリコン窒化膜１１３′の
開孔１１４・・・がら侵入し、溝部１１０、　　・・・
底部に厚い酸化膜を形成すると共に、溝部１１０・・・
内側面の下地酸化膜（図示せず）に沿って侵入し、形成
される酸化膜によって残存シリコン窒化膜１１３′が上
方に押し上げら九、溝部１１０・・−の表面まで酸化体
１１５・・・が形成さｎる（第３図（Ｘ）図示）、つづ
いて、ｎ型シリコンエピタキシャル層１０３上の第１の
シリコン窒化膜１０４．酸化体１１５・・・上の残存シ
リコン窒化膜１１３′をエツチング除去し、更にエピタ
キシャル層１０３上の下地酸化膜をエツチング除去して
酸化体１１５・・・で埋設され穴溝部１１０・・・から
なる素子分離層１１６・・・が形成された（第３図（ト
））図示）、その後、図示しないが常法に従って素子分
離層１１６・・・で分離された島状のｎ型シリコンエピ
タキシャル層１０３＊・１０３冨＊　１０Ｊ　１・・・
ＫＰ型のベース領域を形成し、更に同ベース領域内にｔ
型エミッタ領域、エピタキシャル層１０３１．１０３３
＋　１０３　Ｂ・・・にｎ　型コレクタ取出し領域を形
成してｎｐｎバイポーラ集積回路を製造した。[■] Next, a thermal oxidation treatment is performed.9 At this time, the oxidizing agent penetrates through the openings 114 of the remaining silicon nitride film 113' at the bottom of the grooves 110,...
While forming a thick oxide film on the bottom, the groove portion 110...
The remaining silicon nitride film 113' invades along the base oxide film (not shown) on the inner surface, and the formed oxide film pushes the remaining silicon nitride film 113' upward until it reaches the surface of the groove 110. is formed (as shown in FIG. 3(X)), and then a first silicon nitride film 104. is formed on the n-type silicon epitaxial layer 103. The remaining silicon nitride film 113' on the oxidant 115 is etched away, and the base oxide film on the epitaxial layer 103 is further etched away to form a hole groove portion 110 filled with the oxide 115. The element isolation layers 116... are formed (as shown in FIG. 3(G)), and then, although not shown, the island-shaped n-type silicon epitaxial layer 103 is separated by the element isolation layers 116 in accordance with a conventional method. *・103 Tomi* 10J 1...
A KP type base region is formed, and t is further formed in the base region.
Type emitter region, epitaxial layer 1031.1033
An n-type collector extraction region was formed at +103 B... to manufacture an npn bipolar integrated circuit.

しかして、本発明方法によれば第３図０）に示す如く溝
部１１０・・・内側面にシリコン窒化膜１１３’ｆｆリ
アクテイブイオンエツチングにより自己整合的に残存さ
せる際、多結晶シリコン膜１０５及び環状の酸化膜１０
ｇ−・・がエツチングマスクとなるため、第１のシリコ
ン窒化Ｍ１０４は全く工、チングされない、ちなみに、
同一条件でのりアクティブイオンエツチングの工、チン
グレートはシリコン窒化物よシも多結晶シリコンの方が
４〜６倍遅い、このため、多結晶シリコン膜１０５及び
酸化膜１０　Ｂ　−・を除去することによってｎ型シリ
コンエピタキシャル層１０３上に初期堆積時の膜厚を有
する第１のシリコン窒化膜１０４を残存できる。従って
、熱酸化処理によってバードビーク、バードへ、ドが抑
制されたノ９ターン変換差が小さく、かつｎ型シリコン
エピタキシャル層１．　ＯＪｌとほぼ同レベルの平坦な
素子分離層１１６を備えたｎｐｎバイポーラ集積回路金
得ることができる。According to the method of the present invention, as shown in FIG. 30), when the silicon nitride film 113'ff is left in a self-aligned manner on the inner surface of the groove 110 by reactive ion etching, the polycrystalline silicon film 105 and Annular oxide film 10
Since g-... serves as an etching mask, the first silicon nitride M104 is not etched or etched at all.
The active ion etching rate under the same conditions is 4 to 6 times slower for polycrystalline silicon than for silicon nitride. Therefore, the polycrystalline silicon film 105 and the oxide film 10B-. should be removed. This allows the first silicon nitride film 104 to remain on the n-type silicon epitaxial layer 103, having the same thickness as when it was initially deposited. Therefore, the thermal oxidation treatment suppresses bird's beak, bird's, and 9 turn conversion differences, and the n-type silicon epitaxial layer 1. It is possible to obtain an npn bipolar integrated circuit with a flat device isolation layer 116 that is approximately on the same level as OJl.

なお本発明方法は上記実施例の如（ｎｐｎバイポーラ集
積回路の製造のみならず、ＩＬ、ＥＣＬなどの他のパイ
ポート集積回路、ＭＯ８集積回路の製造等にも同様に適
用できる。The method of the present invention can be applied not only to the manufacture of npn bipolar integrated circuits as in the above embodiment, but also to the manufacture of other pie port integrated circuits such as IL and ECL, MO8 integrated circuits, etc.

以上詳述した如（、本発明によれは熱酸化時のバードビ
ークやバードへ、ト９の生成を抑制して一９ターン変換
差の小さい微細か素子分離層を形成でき、ひいては高集
積度の半導体装置を製造できる等顕著な効果を有する。As described in detail above, according to the present invention, it is possible to suppress the formation of bird beaks, birds, and gates during thermal oxidation, form a fine element isolation layer with a small 19-turn conversion difference, and further improve the integration of highly integrated devices. It has remarkable effects such as being able to manufacture semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）〜＜ｃ）は従来法によるｎｐｎバイポーラ
集積回路の製造における酸化膜分離層の形成工程を示す
断面図、第２図（ａ）〜（ｄ）は従来の改良された方法
によるｎｐｎバイポーラ集積回路の製造における酸化膜
分離層の形成工程を示す断面図、第３図（＆）〜（ｈ）
は本発明の実施例でのｎｐｎバイポーラ集積回路の製造
における素子分離層の形成工程を示す断面図である。 １０１・・・ｐ型シリコン基板、１０２＊、１０２鵞。 Ｊ　０２．−ｎ　　埋込み層、ＪＯＪｅ１０３１　Ｈ１
０３鵞＊１０３ｓ・・・讐ＷシＩＪ：ｙンエビタキシャ
ル層、１０４，１０６．１１３−−シリコン窒化膜、１
０８・・・酸化膜、１１ｏ・・・溝部、１１１−庇部、
１１２・・・ｐ＋型反転防止層５ｌｌＪＩ’・・・残存
シリコン窒化膜、１１１−・酸化体、１１６・・・素子
分離層。Figures 1 (a) to <c) are cross-sectional views showing the process of forming an oxide film separation layer in the manufacture of an NPN bipolar integrated circuit using a conventional method, and Figures 2 (a) to (d) are cross-sectional views showing a conventional improved method. 3 (&) to (h) are cross-sectional views showing the formation process of an oxide film separation layer in the manufacture of an npn bipolar integrated circuit by
FIG. 2 is a cross-sectional view showing a step of forming an element isolation layer in manufacturing an NPN bipolar integrated circuit according to an embodiment of the present invention. 101...p-type silicon substrate, 102*, 102 goose. J02. -n buried layer, JOJe1031 H1
03鵞*103s・・・enWshiIJ:ynebitaxial layer, 104,106.113--Silicon nitride film, 1
08... Oxide film, 11o... Groove portion, 111-Eave portion,
112...p+ type inversion prevention layer 5llJI'...residual silicon nitride film, 111--oxidant, 116... element isolation layer.

Claims (2)

【特許請求の範囲】[Claims] （１）−導電型の半導体層もしくは半導体基板上に、第
１の耐酸化性絶縁膜、非単結晶半導体膜及び第２の耐酸
化性絶縁膜を順次形成する工程と、第２の耐酸化性絶縁
膜と非単結晶半導体膜を少なくとも１箇所以上開口する
工程と、この開口部内側面に露出する非単結晶半導体膜
部分を選択的に熱酸化して酸化膜を形成する工程と、開
口部内側面に形成された酸化膜をマスクとして核間口部
から露出する第１の耐酸化性絶縁膜をエツチングして前
記三層膜に開口窓を形成する工程と、前記第２の耐酸化
性絶縁膜をマスクとして開口窓から露出する半導体層も
しくは半導体基板をエツチングして溝部を形成すると共
に、該溝部の開口に前記三層膜をひさし状に延出する工
程と、この溝部を含む全面に第３の耐酸化性絶縁膜を形
成する工程と、前記第２の耐酸化性絶縁膜又は前記開口
窓の内側面の一部に形成された酸化膜をマスクとして前
記溝部の底部一部の第３の絶縁膜をエツチングして該溝
部の底部一部の半導体層もしくは半導体基板を露出させ
る工程と、熱酸化処理を施して前記溝部を酸化体で埋設
することにより素子分離層を形成する工程とを具備した
こ、、とを特徴とする半導体装置の製造方法。(1) - Step of sequentially forming a first oxidation-resistant insulating film, a non-single crystal semiconductor film, and a second oxidation-resistant insulating film on a conductive type semiconductor layer or semiconductor substrate; a step of forming an oxide film by selectively thermally oxidizing a portion of the non-single crystal semiconductor film exposed on the inner surface of the opening; forming an opening window in the three-layer film by etching the first oxidation-resistant insulating film exposed from the nuclear opening using the oxide film formed on the side surface as a mask; and the second oxidation-resistant insulating film. etching the semiconductor layer or semiconductor substrate exposed through the opening window using the etching mask as a mask to form a groove, and extending the three-layer film in the shape of an eave into the opening of the groove, and etching the third layer over the entire surface including the groove. forming a third oxidation-resistant insulating film on a part of the bottom of the groove using the second oxidation-resistant insulating film or the oxide film formed on a part of the inner surface of the opening window as a mask; The method includes a step of etching the insulating film to expose a portion of the semiconductor layer or semiconductor substrate at the bottom of the trench, and a step of performing thermal oxidation treatment to fill the trench with an oxidant to form an element isolation layer. A method for manufacturing a semiconductor device characterized by the following steps. （２）非単結晶半導体膜が多結晶シリコン膜、不純物ド
ーグ多結晶シリコン膜もしくは金属硅化物膜のうちのい
ずれかからなることを特徴とする特許請求の範囲第１項
記載の半導体装置の製造方法。(2) Manufacturing a semiconductor device according to claim 1, wherein the non-single crystal semiconductor film is made of any one of a polycrystalline silicon film, an impurity doped polycrystalline silicon film, or a metal silicide film. Method.
JP15520381A 1981-09-30 1981-09-30 Manufacture of semiconductor device Pending JPS5856437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15520381A JPS5856437A (en) 1981-09-30 1981-09-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15520381A JPS5856437A (en) 1981-09-30 1981-09-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5856437A true JPS5856437A (en) 1983-04-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP15520381A Pending JPS5856437A (en) 1981-09-30 1981-09-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5856437A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068202A (en) * 1988-12-15 1991-11-26 Sgs-Thomson Microelectronics S.R.L. Process for excavating trenches with a rounded bottom in a silicon substrate for making trench isolation structures
US5182227A (en) * 1986-04-25 1993-01-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182227A (en) * 1986-04-25 1993-01-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US5068202A (en) * 1988-12-15 1991-11-26 Sgs-Thomson Microelectronics S.R.L. Process for excavating trenches with a rounded bottom in a silicon substrate for making trench isolation structures

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