JPS5856437A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5856437A JPS5856437A JP15520381A JP15520381A JPS5856437A JP S5856437 A JPS5856437 A JP S5856437A JP 15520381 A JP15520381 A JP 15520381A JP 15520381 A JP15520381 A JP 15520381A JP S5856437 A JPS5856437 A JP S5856437A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- oxidation
- silicon nitride
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に素子分離領
域の形成工程を改良した半導体装置の製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which the process for forming element isolation regions is improved.
半導体集積回路は容量の増大、機能の多様化によシ増々
大規模化する傾向にあシ、これに伴なって素子の微細化
は3μm、2μmついにはすシミクロンの寸法にすると
とが要求されている。Semiconductor integrated circuits tend to become larger and larger due to increased capacity and diversification of functions, and along with this, there is a demand for miniaturization of elements down to 3 μm, 2 μm, and finally to the symicron size. ing.
ところで、上述の微細化に不可欠な技術として素子間を
誘電体に゛よシ分離する技術があシ、その一つとして従
来から選択酸化技術が行なわれている。しかして2、選
択酸化技術にょるnpnパイ/−2里集積回路の製造す
る方法を第1図(、)〜(、)を参照して以下に説明す
る。By the way, as a technique essential to the above-mentioned miniaturization, there is a technique of separating elements using a dielectric material, and one of these techniques has been a selective oxidation technique. 2. A method of manufacturing an npn pi/-2 li integrated circuit using selective oxidation technology will be described below with reference to FIGS.
(1) tず、p型シリコン基板1の主面にn+埋込
み層2・・・を選択的に形成し、エピタキシャル法によ
[n型エピタキシャル半導体層3を成長させた後、エピ
タキシャル半導体層3表面に熱酸化によシ下地。酸化膜
4を成長させ、更にシリコン窒化膜5を増稠する。つづ
いて、これら膜5.4の素子分離領域の形成予定部に開
孔窓6を写真蝕刻法によシ選択的に形成する(第1図(
a)図示)1、
(2) 次いで、シリコン窒化膜5及び下地酸化膜4
をマスクとして露出した!Imエピタキシャル半導体層
3を選択的にエッチyダ除去して溝部7を形成した後、
同シリコン窒化膜5及び下地酸化膜4をマスクとしてゾ
ロンをイオン注入し溝部1底部のn型エピタ中シャル半
導体層3付近に?ロンイオ、ン注入層8を形成した(第
1図(b)図示)。(1) First, an n+ buried layer 2 is selectively formed on the main surface of a p-type silicon substrate 1, and then an n-type epitaxial semiconductor layer 3 is grown by an epitaxial method. Thermal oxidation is applied to the surface. An oxide film 4 is grown, and a silicon nitride film 5 is further thickened. Subsequently, opening windows 6 are selectively formed in the portions of these films 5.4 where the element isolation regions are to be formed by photolithography (see FIG.
a) As shown) 1, (2) Next, silicon nitride film 5 and base oxide film 4
exposed as a mask! After selectively etching and removing the Im epitaxial semiconductor layer 3 to form the groove portion 7,
Using the same silicon nitride film 5 and base oxide film 4 as a mask, zolon is ion-implanted into the n-type epitaxial semiconductor layer 3 at the bottom of the trench 1. A ion-implanted layer 8 was formed (as shown in FIG. 1(b)).
(3)次いで、シリコン鼠化膜5を耐酸化性マスクとし
て高温ウェット雰囲気中で熱酸化処理し、溝部1部分を
選択酸化して酸化膜分離層9を形成した。この時、第1
図(c)に示す如<、Sロンイオン注入層8が拡散して
同分離層9底部にr型反転防止層10が形成された。つ
づいて、シリコン窒化膜5及び下地酸化膜4を除去した
後、図示しな−が常法に従って酸化膜分離層9で分離さ
れた島状の1屋工ピタキシヤル半導体層3にp型のベー
ス領域を形成し、更に同ペース領域内に?型工ず、夕領
域、エピタキシャル層3に?型コレクタ取出し領域を形
成してnpnバイポーラ集積回路を製造する。(3) Next, thermal oxidation treatment was performed in a high temperature wet atmosphere using the silicon dot oxide film 5 as an oxidation-resistant mask, and the groove portion 1 portion was selectively oxidized to form the oxide film separation layer 9. At this time, the first
As shown in Figure (c), the Sron ion-implanted layer 8 was diffused to form an r-type inversion prevention layer 10 at the bottom of the isolation layer 9. Subsequently, after removing the silicon nitride film 5 and the underlying oxide film 4, a p-type base region (not shown) is formed on the island-shaped pitaxial semiconductor layer 3 separated by an oxide film separation layer 9 in accordance with a conventional method. Formed and further within the same pace area? Mold work, evening region, epitaxial layer 3? A mold collector extraction region is formed to manufacture an npn bipolar integrated circuit.
しかしながら、上述した選択酸化法にあっては、高温酸
化を長時間行なう必要から、シリコン窒化膜6下に設け
られた窒化膜に起因するオキシナイトライドの生成防止
を目的とする下地酸化M4を介して横方向に酸化が進行
する、iわゆるサイド酸化が起こシ、第1図(C)に示
す如くバードビーク11やバードヘッド12を生じる。However, in the above-mentioned selective oxidation method, since it is necessary to carry out high-temperature oxidation for a long time, the base oxidation M4 is performed for the purpose of preventing the formation of oxynitride caused by the nitride film provided under the silicon nitride film 6. As a result, oxidation progresses in the lateral direction, so-called side oxidation, resulting in bird's beaks 11 and bird's heads 12 as shown in FIG. 1(C).
バードビーク11の発生は島状の素子領域の縮小化につ
ながるばかシか、同素子領域のパターン変換誤差が大き
く、なった〕、写真蝕刻法による開口窓のノ々ターン精
度の悪化、微細な開口窓の形成困難等を一招いたシする
。前記・櫂−ドヘッドの発生は、n型工fタキシャル半
導体層3表面の1段差となシ、配線の断切れにつながる
欠点がある。また、溝部1の側面が深さ方向と分の2倍
の幅となシ、1前述のパードーーりに加えて更に集積度
低下を招く。更に素子特性にも著し埴悪影響を及ぼす。The occurrence of bird beak 11 is due to the reduction of the island-shaped element area, or the pattern conversion error in the element area becomes large], the deterioration of the no-turn accuracy of the aperture window by photolithography, and the fine aperture. This may lead to difficulties in forming the window. The occurrence of the paddle head is caused by a one-step difference in the surface of the n-type taxial semiconductor layer 3, which has the drawback of leading to disconnection of the wiring. Moreover, if the side surface of the groove part 1 is twice as wide as the width in the depth direction, in addition to the above-mentioned parity, the degree of integration is further reduced. Furthermore, it has a significant negative effect on device characteristics.
例えば、シリコン雪化wX5を耐酸化性マスクとして高
温酸素雰囲気中で熱酸化処理すると、シリ″:1y窒化
膜5とエピタキシャル半導体層S等とのストレ不発生、
熱酸化中でのn型エピタキシャル半導体層3等への熱歪
による0−8−F (0xidation Indue
@dStaeklng Faults )等の結晶欠陥
が分離層9.周囲のn型エピタキシャル半導体層3等に
発生し、素子特性を著しく劣化させる。For example, when thermal oxidation treatment is performed in a high-temperature oxygen atmosphere using silicon snow plating wX5 as an oxidation-resistant mask, no stress occurs between the silicon '':1y nitride film 5 and the epitaxial semiconductor layer S, etc.
0-8-F due to thermal strain on the n-type epitaxial semiconductor layer 3 etc. during thermal oxidation.
Crystal defects such as @dStaeklng Faults) occur in the separation layer 9. This occurs in the surrounding n-type epitaxial semiconductor layer 3, etc., and significantly deteriorates the device characteristics.
そこで、上記問題を改善する方法として、たとえばIB
M T@ehnical Disclosur@Bul
letin Mo1.22 A7 、Dec@d*r
19.797が提案されている。この方法を第2図<&
)〜(d) を参照して説明する。Therefore, as a way to improve the above problem, for example, IB
M T@ehnical Disclosure@Bul
letin Mo1.22 A7, Dec@d*r
19.797 has been proposed. This method is shown in Figure 2.
) to (d).
まずp型シリコン基板1にn+!込み層2t−形成後、
その上Kn型エピタキシャル半導体層3を成長させ、表
面に約100X程度の下地酸化a4を形成する。その後
約10001程度の第1シ、リコン窒化膜5t−堆積後
、所望のシリコン窒化膜と下地酸化膜′を開口し、表面
に露出したmWエピタキシャル半導体層を工オチンクス
ルことによって、溝部1と、シリコン窒化膜5のひさ、
し構造管形成する〔第2図(a)図示〕。次に熱酸化処
理を施し、該溝部1周囲に酸化膜13を約100X程度
形成する。しかる後、再度全体に第2シリコン窒化膜1
4を堆積させた後、前記第1シリコン窒化膜5のひさし
をマスクにしてリアクティゾイオンエッチングによって
溝部7底部の第2シリコン窒化膜14を自己整合的に除
去する、〔第2図(b)図示〕、このように溝部7の側
壁に自己整合的に窒化膜を形成した後、必要に応じてC
型不純物イオンを溝部7底部の半導体基板1に打ちこむ
、続いて熱酸化処理を施すことによって溝部1には酸化
膜分離層9′が形成されると共に、p1反転防止層1σ
が上記酸化熱工程によって形成される〔第2図(C)図
示す〕、その後第1シリコン窒化膜5、第2シリコン窒
化膜14ならび下地酸化膜4を工。First, n+! on the p-type silicon substrate 1! After forming the embedding layer 2t,
Thereon, a Kn type epitaxial semiconductor layer 3 is grown, and a base oxide a4 of about 100X is formed on the surface. Thereafter, after depositing a first silicon nitride film 5t of about 10,000 ml, a desired silicon nitride film and base oxide film' are opened, and the mW epitaxial semiconductor layer exposed on the surface is etched to form a trench 1 and a silicon nitride film 5t. The roof of the nitride film 5,
Then, a structural tube is formed (as shown in FIG. 2(a)). Next, a thermal oxidation process is performed to form an oxide film 13 of about 100X around the groove 1. After that, a second silicon nitride film 1 is applied over the entire surface again.
4, the second silicon nitride film 14 at the bottom of the trench 7 is removed in a self-aligned manner by reactive ion etching using the eaves of the first silicon nitride film 5 as a mask [FIG. ) As shown], after forming the nitride film in a self-aligned manner on the sidewalls of the trench 7, C.
By implanting type impurity ions into the semiconductor substrate 1 at the bottom of the trench 7 and then performing thermal oxidation treatment, an oxide film separation layer 9' is formed in the trench 1, and a p1 inversion prevention layer 1σ is formed.
is formed by the above-mentioned oxidation thermal process [as shown in FIG. 2(C)], and then the first silicon nitride film 5, the second silicon nitride film 14, and the base oxide film 4 are formed.
チング除去する(第2図(d)図示)。Remove the tingling (as shown in FIG. 2(d)).
しかして、上記方法では、溝部7の側面にRIKによっ
て耐酸化性絶縁膜である第2シリコン窒化膜14を自己
整合的に形成することにより、前記溝部7の横方向への
酸化の拡シを少なくできる。つまυ酸化剤は溝部7の底
部の窒化膜開口部から浸入し、溝部2の底部に厚い酸化
膜を形成するとともに、第2シリコン窒化膜14の酸化
膜13に沿って酸化剤が浸入するためそこに形成される
酸化膜が、前記第2シリコン窒化腺14yfr押し上げ
、ちょうど溝部1の表面まで酸化膜分離層qが形成され
る。このため、n型エピタキシャル半導体層3表面とほ
ぼ平坦で、バード・ピークの小さい酸化膜分離層9′が
形成できる。しかし、かかる方法においては、第2図c
b>において、シリコン窒化膜14を溝部1の側面にR
,1,1,で自己整合的に形成する際、半導体層3表面
のシリコン窒化膜5も同時にエツチングされてなくなっ
てしまうか、あるいは極薄く残る場合がある。このシリ
コン窒化膜3は、溝部7へ選択的に形成する酸化膜分離
層9′のマスク材であり、膜厚が大きければバード・ピ
ークの小さい酸化膜分離層が形成できる。その反面、前
記シリコン窒化膜5の膜厚を大きくすると、該シリコン
窒化膜5の下のn型エピタキシャル半導体層3に結晶欠
陥が起シやずいという相対する現象が生じる。友とえば
分離層の深さがl#1程度の場合、シリコン窒化膜5は
約1000X、下地酸化膜4は100Kの膜厚にするこ
とが良いとされている。以上のことから第2図(b)に
おけるシリコン窒化膜5#−i、溝部7の側面にシリコ
ン窒化膜14を形成する際、ある−足の膜厚を保たなけ
ればガらない。However, in the above method, the second silicon nitride film 14, which is an oxidation-resistant insulating film, is formed on the side surface of the trench 7 in a self-aligned manner by RIK, thereby preventing the oxidation from spreading in the lateral direction of the trench 7. You can do less. The oxidizing agent intrudes from the nitride film opening at the bottom of the groove 7 and forms a thick oxide film at the bottom of the groove 2, and at the same time, the oxidizing agent infiltrates along the oxide film 13 of the second silicon nitride film 14. The oxide film formed there pushes up the second silicon nitride gland 14yfr, and an oxide film separation layer q is formed just up to the surface of the groove portion 1. Therefore, it is possible to form an oxide film separation layer 9' that is substantially flat with the surface of the n-type epitaxial semiconductor layer 3 and has a small bird peak. However, in such a method, FIG.
b>, the silicon nitride film 14 is formed on the side surface of the trench 1 with R.
, 1, 1 in a self-aligned manner, the silicon nitride film 5 on the surface of the semiconductor layer 3 may also be etched away at the same time, or may remain extremely thin. This silicon nitride film 3 is a mask material for an oxide film separation layer 9' selectively formed in the groove portion 7, and if the film thickness is large, an oxide film separation layer with a small bird peak can be formed. On the other hand, when the thickness of the silicon nitride film 5 is increased, the opposite phenomenon occurs in that crystal defects occur in the n-type epitaxial semiconductor layer 3 under the silicon nitride film 5. For example, when the depth of the separation layer is about l#1, it is said that it is good to make the silicon nitride film 5 about 1000X thick and the base oxide film 4 about 100K thick. From the above, when forming the silicon nitride film 5#-i and the silicon nitride film 14 on the side surfaces of the groove portion 7 in FIG. 2(b), damage will occur unless the film thickness is maintained at a certain level.
しかし、現在のRIEのエツチングレートは、5001
〜1000 X/linで、さらにウエノ1内のばらつ
きが大きくことから、エピタキシャル半導体層3上のシ
リコン窒化11[ffを均一膜厚で、かつある膜厚内(
例えば1000X±10%)にとどめることは量産的に
は難しい。However, the current RIE etching rate is 5001
~ 1000
For example, it is difficult for mass production to limit the value to 1000X±10%).
本発明は上記問題点を解消するためになされたもので、
パーr・ピークを抑制してノターン変換差の小さい高集
積度化が可能な素子分離層を有する半導体装置の製造方
法を提供しようとするものである。The present invention was made to solve the above problems, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device having an element isolation layer that suppresses the Par-r peak and allows for high integration with small no-turn conversion differences.
すなわち、本発明は一導電型の半導体層もしくは半導体
基板上に、第1の耐酸化性絶縁膜、非単結晶半導体膜及
び第2の耐酸化性絶縁膜を順次形成する工程と、第2の
耐酸化性絶縁膜と非単結″6半導体膜を少なくとも1箇
所以上開口する工程と、この開口部内側面に露出する非
単結晶半導体膜部分を選択的に熱酸化して酸化膜を形成
する工程と、開口部内側面に形成された酸化膜をマスク
として該開口部から露出する第1の耐酸化性絶縁膜をエ
ツチングして前記三層膜に開口窓全形成する工程と、前
記第2の耐酸化性絶縁膜をマスクとして開口窓から露出
する半導体層もしくは半導体基板をエツチングして溝部
を形成すると共に、該溝部の開口に前記三層膜をひさし
状に延出する工程と、この溝部を含む全面に第3の耐酸
化性絶縁膜を形成する工程と、前記第2の耐酸化性絶縁
膜又は前記開口窓の内側面の一部に形成された酸化膜を
マスクとして前記溝部の底部一部の第3の絶縁膜をエツ
チングして該溝部の底部一部の半導体層もしくは半導体
基板を露出させる工程と、熱酸化処理を施して前記溝部
を酸化体で埋設することによシ、素子分離層を形成する
工程とを具備し次ことを特徴とするものである。That is, the present invention includes a step of sequentially forming a first oxidation-resistant insulating film, a non-single crystal semiconductor film, and a second oxidation-resistant insulating film on a semiconductor layer or semiconductor substrate of one conductivity type; A step of opening an oxidation-resistant insulating film and a non-single-crystal semiconductor film at least at one location, and a step of selectively thermally oxidizing a portion of the non-single-crystal semiconductor film exposed on the inner surface of this opening to form an oxide film. etching the first oxidation-resistant insulating film exposed from the opening using the oxide film formed on the inner surface of the opening as a mask to form the entire opening window in the three-layer film; forming a groove by etching the semiconductor layer or semiconductor substrate exposed through the opening window using a chemical-containing insulating film as a mask, and extending the three-layer film in the shape of an eaves into the opening of the groove; forming a third oxidation-resistant insulating film on the entire surface; and forming a part of the bottom of the groove using the second oxidation-resistant insulating film or an oxide film formed on a part of the inner surface of the opening window as a mask. By etching the third insulating film to expose a part of the semiconductor layer or semiconductor substrate at the bottom of the trench, and by performing thermal oxidation treatment to fill the trench with an oxidant, the device isolation layer is removed. The method is characterized by the following features:
本発明における第1の耐酸化性絶縁膜は選択酸化時に半
導体層もしくは半導体基板が酸化されるのを防止すると
共に、バード・ピークの発生を抑制する役目をする。か
かる第1の耐酸化性絶縁膜としては、例えばシリコン窒
化膜、アルミナ膜等を挙げることができる。The first oxidation-resistant insulating film in the present invention serves to prevent the semiconductor layer or the semiconductor substrate from being oxidized during selective oxidation, and also serves to suppress the occurrence of bird peaks. Examples of the first oxidation-resistant insulating film include a silicon nitride film and an alumina film.
本発明における非単結晶半導体膜は第1の耐酸化性絶縁
膜の保護するために用いられる。また、半導体膜の開口
後の熱酸により該開口内側面に形成する酸化膜は、半導
体層もしくは半導体基板に溝部を形成する際、該非晶質
半導体膜が工、チングされるのを阻止するために用いら
れる。かかる非単結晶半導体膜としては、例えば多結晶
シリコン膜、メロン、燐、砒素等の不純物を含む多結晶
シリコン膜、非晶質シリコン膜、或いはタングステンシ
リサイr1モリブデンシリサイドなどの金属シリサイド
膜等を挙げることができる。The non-single crystal semiconductor film in the present invention is used to protect the first oxidation-resistant insulating film. Furthermore, an oxide film formed on the inner surface of the opening by hot acid after opening the semiconductor film is used to prevent the amorphous semiconductor film from being etched or etched when forming a groove in the semiconductor layer or semiconductor substrate. used for. Examples of such a non-single crystal semiconductor film include a polycrystalline silicon film, a polycrystalline silicon film containing impurities such as melon, phosphorus, and arsenic, an amorphous silicon film, or a metal silicide film such as tungsten silicide r1 molybdenum silicide. can be mentioned.
本発明における第2の耐酸化性絶縁膜は半導体層もしく
は半導体基板に溝部を形成する際のマスクとして作用す
ると共に、非単結晶半導体膜を保護する役目をする。The second oxidation-resistant insulating film in the present invention acts as a mask when forming a groove in a semiconductor layer or a semiconductor substrate, and also serves to protect the non-single crystal semiconductor film.
次に1本発明をnpnバイプーラ集積回路の製造に適用
した例について第3図(1)〜伽)を参照して説明する
。Next, an example in which the present invention is applied to the manufacture of an npn bipolar integrated circuit will be described with reference to FIGS. 3(1) to 3).
実施例
〔1〕まず、pmシリコン基板101の主面Kn+埋込
み層202@h102鵞、102.−・・を選択的に形
成し、エピタキシャル成長法によりn型のシリ逼ンエビ
タキシャル層103を成長させた。つづいて、熱酸化処
理を施してエピタキシャル層103表面に例えば厚さ1
00Xの下地酸化膜(図示せず)を形成し、更にこの下
地酸化膜上にCVD法にょシ例えば厚さ1oooXの第
1のシリコン窒化膜104、厚さ500Xの多結晶シリ
コン膜105及び厚さ2000〜2500Xの第2のシ
リコン窒化膜106を順次堆積した後、第2のシリコン
窒化膜106の素子分離層形成予定部をフォトエツチン
グ技術によ〕選択的にエツチングして開口を形成しfc
(第3図(a)図示)。Example [1] First, the main surface Kn+buried layer 202@h102 of the pm silicon substrate 101, 102. -... were selectively formed, and an n-type silicon epitaxial layer 103 was grown by an epitaxial growth method. Subsequently, thermal oxidation treatment is applied to the surface of the epitaxial layer 103 to a thickness of, for example, 1.
A base oxide film (not shown) with a thickness of 00X is formed, and then a first silicon nitride film 104 with a thickness of 100X, a polycrystalline silicon film 105 with a thickness of 500X, and a polycrystalline silicon film 105 with a thickness of After sequentially depositing the second silicon nitride film 106 with a thickness of 2000 to 2500X, the portion of the second silicon nitride film 106 where the element isolation layer is to be formed is selectively etched using a photoetching technique to form an opening.
(Illustrated in FIG. 3(a)).
(ii)次いで、第2のシリコン窒化膜10gをマスク
として開口から露出する多結晶シリコン膜105部分を
選択的にエツチング除去して開口部107を形成した後
、熱酸化処理した。この時、開口部107・・・の内側
面に露出する多結晶シリコン膜105部分が酸化されて
例えば幅1500Xの環状の酸化膜108・・・が形成
された(第3図伽)図示)、つづいて、第2のシリコン
窒化M106及び酸化膜108・・・をマスクとして第
1のシリコン窒化111104及び下地酸化膜を選択的
に工、チングして前記四層膜に開孔窓109・・・を形
成したーこのエツチングに際して第2のシリコン窒化膜
106は第1−のシリコン窒化膜104の膜厚相当分(
100OX程度)エツチングされる。ひきつづき、第2
のシリコン窒化膜106及び酸化膜108・・・をマス
クとして開孔窓10Yから露出するn型シリコンエピタ
キシャル層103を選択エツチングして溝部110・・
・と、前記四層膜の庇部111を形成した(第3図(e
)図示)。(ii) Next, using the second silicon nitride film 10g as a mask, the portion of the polycrystalline silicon film 105 exposed from the opening was selectively etched away to form an opening 107, followed by thermal oxidation treatment. At this time, the portion of the polycrystalline silicon film 105 exposed on the inner surface of the opening 107 is oxidized, and a ring-shaped oxide film 108 having a width of 1500X, for example, is formed (as shown in FIG. 3). Next, using the second silicon nitride M106 and oxide film 108 as a mask, the first silicon nitride 111104 and base oxide film are selectively etched to open windows 109 in the four-layer film. During this etching, the second silicon nitride film 106 has a thickness equivalent to that of the first silicon nitride film 104 (
100OX) is etched. Continuing, Part 2
The n-type silicon epitaxial layer 103 exposed from the opening window 10Y is selectively etched using the silicon nitride film 106 and oxide film 108 .
・The eaves portion 111 of the four-layer film was formed (see FIG. 3(e)
).
(iii)次いで、熱酸化処理を施して溝部110・・
・内側面に・例えば厚さ100−、lの下地酸化膜(図
示せず)を形成した後、庇部111をマスクとして溝部
110・・・の底部にpW不純物、例えばメロンをイオ
ン注入してp型反転防止層112・・・を形成した。つ
づ−て、溝部110・・・を含む全面に減圧CvD法如
よp例えば厚さ300^のシリコン窒化膜を堆積した(
第3図(d)図示)この時、溝部110・・・内側面の
下地酸化膜及び第2のシリコン窒化膜106上等に均一
厚の第3のシリコン窒化膜113が堆積された。(iii) Next, thermal oxidation treatment is performed to form the groove 110...
After forming a base oxide film (not shown) with a thickness of, for example, 100 mm on the inner surface, pW impurities such as melon are ion-implanted into the bottoms of the trenches 110 using the eaves 111 as a mask. A p-type anti-inversion layer 112... was formed. Next, a silicon nitride film having a thickness of, for example, 300^ is deposited on the entire surface including the grooves 110 by low pressure CvD method (
At this time, a third silicon nitride film 113 having a uniform thickness was deposited on the base oxide film and the second silicon nitride film 106 on the inner surface of the trench 110 (as shown in FIG. 3(d)).
O■〕次いで、庇部111をマスクにして溝部110・
・・底部の第3のシリコン窒化膜113及び下地酸化膜
をリアクティプイオンエ、チングして溝部110・・・
の内側面化シリコン窒化膜113′を残存させると共和
開孔114・・・を形成した。この工、チングに際して
オーバーエツチングすることにより、第2のシリコン窒
化膜Iθ6が工、チング除去されるが、その下の第1の
シリコン窒化膜104は多結晶シリコ711105及び
酸化膜108・・・で覆われているため、膜減りは防止
される(第3図(・)図示)、つづいて、多結晶シリコ
ン膜105及び酸化膜1011・・・を順次工、チング
除去した(83図(f)図示ン。O■] Next, using the eaves part 111 as a mask, the groove part 110 and
...The third silicon nitride film 113 at the bottom and the base oxide film are etched with reactive ion etching to form the trench 110...
When the inner surface-formed silicon nitride film 113' remained, common openings 114 were formed. By over-etching during this etching, the second silicon nitride film Iθ6 is etched and removed, but the first silicon nitride film 104 underneath it is made up of polycrystalline silicon 711105 and oxide film 108... Since the polycrystalline silicon film 105 and the oxide film 1011 are covered, film reduction is prevented (as shown in Fig. 3(-)).Next, the polycrystalline silicon film 105 and the oxide film 1011... are sequentially etched and removed (Fig. 83(f)). Illustrated.
〔■〕次いで、熱酸化処理を施し九、この時、酸化剤は
溝部110・・・底部の残存シリコン窒化膜113′の
開孔114・・・がら侵入し、溝部110、 ・・・
底部に厚い酸化膜を形成すると共に、溝部110・・・
内側面の下地酸化膜(図示せず)に沿って侵入し、形成
される酸化膜によって残存シリコン窒化膜113′が上
方に押し上げら九、溝部110・・−の表面まで酸化体
115・・・が形成さnる(第3図(X)図示)、つづ
いて、n型シリコンエピタキシャル層103上の第1の
シリコン窒化膜104.酸化体115・・・上の残存シ
リコン窒化膜113′をエツチング除去し、更にエピタ
キシャル層103上の下地酸化膜をエツチング除去して
酸化体115・・・で埋設され穴溝部110・・・から
なる素子分離層116・・・が形成された(第3図(ト
))図示)、その後、図示しないが常法に従って素子分
離層116・・・で分離された島状のn型シリコンエピ
タキシャル層103*・103冨* 10J 1・・・
KP型のベース領域を形成し、更に同ベース領域内にt
型エミッタ領域、エピタキシャル層1031.1033
+ 103 B・・・にn 型コレクタ取出し領域を形
成してnpnバイポーラ集積回路を製造した。[■] Next, a thermal oxidation treatment is performed.9 At this time, the oxidizing agent penetrates through the openings 114 of the remaining silicon nitride film 113' at the bottom of the grooves 110,...
While forming a thick oxide film on the bottom, the groove portion 110...
The remaining silicon nitride film 113' invades along the base oxide film (not shown) on the inner surface, and the formed oxide film pushes the remaining silicon nitride film 113' upward until it reaches the surface of the groove 110. is formed (as shown in FIG. 3(X)), and then a first silicon nitride film 104. is formed on the n-type silicon epitaxial layer 103. The remaining silicon nitride film 113' on the oxidant 115 is etched away, and the base oxide film on the epitaxial layer 103 is further etched away to form a hole groove portion 110 filled with the oxide 115. The element isolation layers 116... are formed (as shown in FIG. 3(G)), and then, although not shown, the island-shaped n-type silicon epitaxial layer 103 is separated by the element isolation layers 116 in accordance with a conventional method. *・103 Tomi* 10J 1...
A KP type base region is formed, and t is further formed in the base region.
Type emitter region, epitaxial layer 1031.1033
An n-type collector extraction region was formed at +103 B... to manufacture an npn bipolar integrated circuit.
しかして、本発明方法によれば第3図0)に示す如く溝
部110・・・内側面にシリコン窒化膜113’ffリ
アクテイブイオンエツチングにより自己整合的に残存さ
せる際、多結晶シリコン膜105及び環状の酸化膜10
g−・・がエツチングマスクとなるため、第1のシリコ
ン窒化M104は全く工、チングされない、ちなみに、
同一条件でのりアクティブイオンエツチングの工、チン
グレートはシリコン窒化物よシも多結晶シリコンの方が
4〜6倍遅い、このため、多結晶シリコン膜105及び
酸化膜10 B −・を除去することによってn型シリ
コンエピタキシャル層103上に初期堆積時の膜厚を有
する第1のシリコン窒化膜104を残存できる。従って
、熱酸化処理によってバードビーク、バードへ、ドが抑
制されたノ9ターン変換差が小さく、かつn型シリコン
エピタキシャル層1. OJlとほぼ同レベルの平坦な
素子分離層116を備えたnpnバイポーラ集積回路金
得ることができる。According to the method of the present invention, as shown in FIG. 30), when the silicon nitride film 113'ff is left in a self-aligned manner on the inner surface of the groove 110 by reactive ion etching, the polycrystalline silicon film 105 and Annular oxide film 10
Since g-... serves as an etching mask, the first silicon nitride M104 is not etched or etched at all.
The active ion etching rate under the same conditions is 4 to 6 times slower for polycrystalline silicon than for silicon nitride. Therefore, the polycrystalline silicon film 105 and the oxide film 10B-. should be removed. This allows the first silicon nitride film 104 to remain on the n-type silicon epitaxial layer 103, having the same thickness as when it was initially deposited. Therefore, the thermal oxidation treatment suppresses bird's beak, bird's, and 9 turn conversion differences, and the n-type silicon epitaxial layer 1. It is possible to obtain an npn bipolar integrated circuit with a flat device isolation layer 116 that is approximately on the same level as OJl.
なお本発明方法は上記実施例の如(npnバイポーラ集
積回路の製造のみならず、IL、ECLなどの他のパイ
ポート集積回路、MO8集積回路の製造等にも同様に適
用できる。The method of the present invention can be applied not only to the manufacture of npn bipolar integrated circuits as in the above embodiment, but also to the manufacture of other pie port integrated circuits such as IL and ECL, MO8 integrated circuits, etc.
以上詳述した如(、本発明によれは熱酸化時のバードビ
ークやバードへ、ト9の生成を抑制して一9ターン変換
差の小さい微細か素子分離層を形成でき、ひいては高集
積度の半導体装置を製造できる等顕著な効果を有する。As described in detail above, according to the present invention, it is possible to suppress the formation of bird beaks, birds, and gates during thermal oxidation, form a fine element isolation layer with a small 19-turn conversion difference, and further improve the integration of highly integrated devices. It has remarkable effects such as being able to manufacture semiconductor devices.
第1図(a)〜<c)は従来法によるnpnバイポーラ
集積回路の製造における酸化膜分離層の形成工程を示す
断面図、第2図(a)〜(d)は従来の改良された方法
によるnpnバイポーラ集積回路の製造における酸化膜
分離層の形成工程を示す断面図、第3図(&)〜(h)
は本発明の実施例でのnpnバイポーラ集積回路の製造
における素子分離層の形成工程を示す断面図である。
101・・・p型シリコン基板、102*、102鵞。
J 02.−n 埋込み層、JOJe1031 H1
03鵞*103s・・・讐WシIJ:yンエビタキシャ
ル層、104,106.113−−シリコン窒化膜、1
08・・・酸化膜、11o・・・溝部、111−庇部、
112・・・p+型反転防止層5llJI’・・・残存
シリコン窒化膜、111−・酸化体、116・・・素子
分離層。Figures 1 (a) to <c) are cross-sectional views showing the process of forming an oxide film separation layer in the manufacture of an NPN bipolar integrated circuit using a conventional method, and Figures 2 (a) to (d) are cross-sectional views showing a conventional improved method. 3 (&) to (h) are cross-sectional views showing the formation process of an oxide film separation layer in the manufacture of an npn bipolar integrated circuit by
FIG. 2 is a cross-sectional view showing a step of forming an element isolation layer in manufacturing an NPN bipolar integrated circuit according to an embodiment of the present invention. 101...p-type silicon substrate, 102*, 102 goose. J02. -n buried layer, JOJe1031 H1
03鵞*103s・・・enWshiIJ:ynebitaxial layer, 104,106.113--Silicon nitride film, 1
08... Oxide film, 11o... Groove portion, 111-Eave portion,
112...p+ type inversion prevention layer 5llJI'...residual silicon nitride film, 111--oxidant, 116... element isolation layer.
Claims (2)
1の耐酸化性絶縁膜、非単結晶半導体膜及び第2の耐酸
化性絶縁膜を順次形成する工程と、第2の耐酸化性絶縁
膜と非単結晶半導体膜を少なくとも1箇所以上開口する
工程と、この開口部内側面に露出する非単結晶半導体膜
部分を選択的に熱酸化して酸化膜を形成する工程と、開
口部内側面に形成された酸化膜をマスクとして核間口部
から露出する第1の耐酸化性絶縁膜をエツチングして前
記三層膜に開口窓を形成する工程と、前記第2の耐酸化
性絶縁膜をマスクとして開口窓から露出する半導体層も
しくは半導体基板をエツチングして溝部を形成すると共
に、該溝部の開口に前記三層膜をひさし状に延出する工
程と、この溝部を含む全面に第3の耐酸化性絶縁膜を形
成する工程と、前記第2の耐酸化性絶縁膜又は前記開口
窓の内側面の一部に形成された酸化膜をマスクとして前
記溝部の底部一部の第3の絶縁膜をエツチングして該溝
部の底部一部の半導体層もしくは半導体基板を露出させ
る工程と、熱酸化処理を施して前記溝部を酸化体で埋設
することにより素子分離層を形成する工程とを具備した
こ、、とを特徴とする半導体装置の製造方法。(1) - Step of sequentially forming a first oxidation-resistant insulating film, a non-single crystal semiconductor film, and a second oxidation-resistant insulating film on a conductive type semiconductor layer or semiconductor substrate; a step of forming an oxide film by selectively thermally oxidizing a portion of the non-single crystal semiconductor film exposed on the inner surface of the opening; forming an opening window in the three-layer film by etching the first oxidation-resistant insulating film exposed from the nuclear opening using the oxide film formed on the side surface as a mask; and the second oxidation-resistant insulating film. etching the semiconductor layer or semiconductor substrate exposed through the opening window using the etching mask as a mask to form a groove, and extending the three-layer film in the shape of an eave into the opening of the groove, and etching the third layer over the entire surface including the groove. forming a third oxidation-resistant insulating film on a part of the bottom of the groove using the second oxidation-resistant insulating film or the oxide film formed on a part of the inner surface of the opening window as a mask; The method includes a step of etching the insulating film to expose a portion of the semiconductor layer or semiconductor substrate at the bottom of the trench, and a step of performing thermal oxidation treatment to fill the trench with an oxidant to form an element isolation layer. A method for manufacturing a semiconductor device characterized by the following steps.
ーグ多結晶シリコン膜もしくは金属硅化物膜のうちのい
ずれかからなることを特徴とする特許請求の範囲第1項
記載の半導体装置の製造方法。(2) Manufacturing a semiconductor device according to claim 1, wherein the non-single crystal semiconductor film is made of any one of a polycrystalline silicon film, an impurity doped polycrystalline silicon film, or a metal silicide film. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15520381A JPS5856437A (en) | 1981-09-30 | 1981-09-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15520381A JPS5856437A (en) | 1981-09-30 | 1981-09-30 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5856437A true JPS5856437A (en) | 1983-04-04 |
Family
ID=15600748
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15520381A Pending JPS5856437A (en) | 1981-09-30 | 1981-09-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5856437A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5068202A (en) * | 1988-12-15 | 1991-11-26 | Sgs-Thomson Microelectronics S.R.L. | Process for excavating trenches with a rounded bottom in a silicon substrate for making trench isolation structures |
US5182227A (en) * | 1986-04-25 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
-
1981
- 1981-09-30 JP JP15520381A patent/JPS5856437A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5182227A (en) * | 1986-04-25 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
US5068202A (en) * | 1988-12-15 | 1991-11-26 | Sgs-Thomson Microelectronics S.R.L. | Process for excavating trenches with a rounded bottom in a silicon substrate for making trench isolation structures |
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