JPS585097U - Blow pattern generation circuit - Google Patents

Blow pattern generation circuit

Info

Publication number
JPS585097U
JPS585097U JP9612681U JP9612681U JPS585097U JP S585097 U JPS585097 U JP S585097U JP 9612681 U JP9612681 U JP 9612681U JP 9612681 U JP9612681 U JP 9612681U JP S585097 U JPS585097 U JP S585097U
Authority
JP
Japan
Prior art keywords
generation circuit
pattern generation
blow pattern
output
binary counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9612681U
Other languages
Japanese (ja)
Inventor
熊谷 耕治
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP9612681U priority Critical patent/JPS585097U/en
Publication of JPS585097U publication Critical patent/JPS585097U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は吹鳴パターンの波形図、第2図は従来例のブロ
ック図、第3図は本考案の実施例のブロック図である。    ・ 31・・・クロック発生回路、34・・・バイナリカウ
ンタ、35・・・リードオンメモリ。
FIG. 1 is a waveform diagram of a blowing pattern, FIG. 2 is a block diagram of a conventional example, and FIG. 3 is a block diagram of an embodiment of the present invention.・ 31... Clock generation circuit, 34... Binary counter, 35... Read-on memory.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] クロック発生回路と、このクロック発生回路が出力した
クロックで動作するバイナリカウンタと、このバイナリ
カウンタの出力をアドレスとして入力し、アドレスの所
定間隔に対応する出力を1′′、  “10′で繰り返
えすように書き込まれたメモリとからなる吹鳴パターン
発生回路。
A clock generation circuit, a binary counter that operates with the clock output from this clock generation circuit, and the output of this binary counter are input as addresses, and the output corresponding to a predetermined interval of the address is repeated at 1'' and “10”. A blowing pattern generation circuit consists of a memory that is written in a manner similar to the following.
JP9612681U 1981-06-30 1981-06-30 Blow pattern generation circuit Pending JPS585097U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9612681U JPS585097U (en) 1981-06-30 1981-06-30 Blow pattern generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9612681U JPS585097U (en) 1981-06-30 1981-06-30 Blow pattern generation circuit

Publications (1)

Publication Number Publication Date
JPS585097U true JPS585097U (en) 1983-01-13

Family

ID=29891007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9612681U Pending JPS585097U (en) 1981-06-30 1981-06-30 Blow pattern generation circuit

Country Status (1)

Country Link
JP (1) JPS585097U (en)

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