JPS584962A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS584962A JPS584962A JP9732182A JP9732182A JPS584962A JP S584962 A JPS584962 A JP S584962A JP 9732182 A JP9732182 A JP 9732182A JP 9732182 A JP9732182 A JP 9732182A JP S584962 A JPS584962 A JP S584962A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- nose
- wire
- strength
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims description 13
- 238000005219 brazing Methods 0.000 abstract description 12
- 239000000919 ceramic Substances 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 7
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005452 bending Methods 0.000 abstract description 2
- 238000000465 moulding Methods 0.000 abstract description 2
- 238000001465 metallisation Methods 0.000 description 3
- 235000014676 Phragmites communis Nutrition 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置特に超高周波帯デバイスに有効な
セラミ、りと金属リードとのロー付部の構造に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a brazed portion between a ceramic or metal lead and a metal lead, which is effective for semiconductor devices, particularly ultra-high frequency band devices.
稠密な導電パターンを有する電子回路や超高周波帯デバ
イスはその電気的特性上及びそれに伴う構造上、セラミ
ック本体と外部引出リードの如きセラミックに金属のロ
ー材でロー材するものに対して幾何学的に制限される。Electronic circuits and ultra-high frequency band devices that have dense conductive patterns are geometrically different from ceramic bodies and external leads, which are made of ceramic with a metal brazing material, due to their electrical characteristics and associated structures. limited to.
特に超高周波帯デバイス用容器や回路基板については浮
遊容量やインダクタンス等の寄生リアクタンス成分がそ
の電子デバイスの特性を阻害するものについては、前記
幾何学的制限が顕著である。従って所望のロー付強度を
得るに困難になる事が多い。The above-mentioned geometrical restrictions are particularly noticeable in containers and circuit boards for ultra-high frequency devices where parasitic reactance components such as stray capacitance and inductance impede the characteristics of the electronic device. Therefore, it is often difficult to obtain the desired brazing strength.
本発明の目的は電子回路の特性を損わず且つ。An object of the present invention is to avoid impairing the characteristics of electronic circuits.
機械的強度を十分満足せしめる様な金属リードのロー付
構造を提供することにある。The object of the present invention is to provide a brazed structure of metal leads that satisfies mechanical strength.
本発明は外部導出リードの先端部をはぼ垂直に折り曲げ
てメタライズ層に取）付けることを特徴とする。The present invention is characterized in that the tips of the external leads are bent almost vertically and attached to the metallized layer.
この構造によれば垂直方向に加わる外力に対してはその
接着強度は著しく強く、かつ水平方向に対してリードを
押すように作用する外力およびリードを引くように作用
する外力のいづれに勾しても同一の強度を有し、とくに
ロー材はリードの周辺全体にわたって均一にまわりこむ
ため、理想的な接着強＆が得られる。According to this structure, the adhesive strength is extremely strong against external forces applied in the vertical direction, and is strong against both external forces that act to push the reed in the horizontal direction and external forces that act to pull the reed. They also have the same strength, and in particular, the brazing material wraps around the entire lead evenly, so ideal adhesive strength can be obtained.
本発明の具体的な主旨を明らかにする為に、特願昭４８
−１０５７１５の第６図第７図を用いて詳説する。！１
図は特願昭４８−１０５７１５に於ける第７図を示した
ものであり、第２図は特願昭４８−１０５７１５ に於
ける第６図を示したものである。In order to clarify the specific gist of the present invention, Japanese Patent Application No. 48
This will be explained in detail using FIG. 6 and FIG. 7 of -105715. ! 1
The figure shows FIG. 7 in Japanese Patent Application No. 105715/1972, and FIG. 2 shows FIG. 6 in Japanese Patent Application No. 105715/1972.
同図の構成を具体的に説明すると、金属スタッド６の凹
溝内に補助スタ、ドアを貫通させる孔を有する絶縁基′
板１１を取りつけ、この基板１１の底面にメタライズ層
１１’を被着形成し、このメタライズ層１１’を例えば
ロー材によりて金属スタ。To explain the configuration of the figure in detail, an insulating base plate having an auxiliary stud and a hole for passing the door in the groove of the metal stud 6.
A plate 11 is attached, a metallized layer 11' is formed on the bottom surface of the substrate 11, and this metallized layer 11' is formed into a metal star by using, for example, brazing material.
ドロの上に固着する。絶縁体１１の上面にメタライズ層
２“、２″を設け、このメタライズ層ｉ、１には半導体
素子３のｉＩＣ極とを結ぶ金属細線４′、４“と外部引
出リードｌＯがとククけられる。更に基板１１の上面と
は枠体１２が取りつけられ、この枠体１２にはメタライ
ズ層１２’が設けられている。こ体１１のメタライズ２
“、２＃以外に補助スタ、ドアに金属細線４で接続され
ている。It sticks to the mud. Metalized layers 2", 2" are provided on the upper surface of the insulator 11, and thin metal wires 4', 4" connecting with the iIC pole of the semiconductor element 3 and external lead lO are formed in the metalized layers i, 1. Further, a frame 12 is attached to the upper surface of the substrate 11, and a metallized layer 12' is provided on this frame 12.
In addition to ", 2#, the auxiliary star is connected to the door with a thin metal wire 4.
この構造は容器の入出力間の容量は極めて小さく且つ容
器の入出力電極は所望された特性インピーダンスをもつ
ストリップラインが構成され、且つ接地インダクタンス
が小さくなる様にしである事に特徴をもつものであるが
、容器の入出力電極間の距離が長いと、インダクタンス
が増大し且つ電極の構成体である絶縁体１１と外部回路
を接続する外部外出リードｌＯが空気に囲まれている為
に急激なインピーダンスを変化する等の欠点を有する。This structure is characterized in that the capacitance between the input and output of the container is extremely small, the input and output electrodes of the container are configured as strip lines with a desired characteristic impedance, and the grounding inductance is small. However, if the distance between the input and output electrodes of the container is long, the inductance will increase, and the external lead lO connecting the insulator 11, which is the structure of the electrode, and the external circuit will be surrounded by air, so it will suddenly increase. It has drawbacks such as changing impedance.
従って外部引出リード１０＜よる損失を少くし且つ入出
力電極のインダクタンスを出来る限り小さくする為には
入出力各々の電極の外部回路布の距離を出来る限シ小さ
くする事が望ましい。Therefore, in order to reduce the loss caused by the external lead 10 and to minimize the inductance of the input and output electrodes, it is desirable to minimize the distance between the external circuit traces of each input and output electrode.
然しながら入出力各々の電極の外部回路布の距離を短か
くすると絶縁基板１１と外部引出リード１０との接続強
度が極めて小さくなる。例えば所望接タライズ２“、２
＃の少くとも日−付する部分は１．４闘巾で長さがｌ〜
１，２″必喪である。即ちリード巾の２倍〜２．５倍の
面積が必要である。勿論リード巾が広い場合には（リー
ド巾） ＋ ０．２〜０．４“× （長さ）＝（リード
巾）×２なるロー付寸法を有するメタライズ面積があれ
ばよいのであるが、超高周波デバイスの小形化から出さ
れた実用的寸法からみると之よルはるかに大きなロー付
巾、長さが必要になる。即ち、所望の特性インピーダン
スを保有しインダクタンスが小さく且つ高信頼度のもの
が必要であるが１例えば現在の小形容器で熱的機械的衡
機に強い容器の設計し製造するに於すて。However, if the distance between the external circuit cloths of the input and output electrodes is shortened, the connection strength between the insulating substrate 11 and the external lead 10 becomes extremely small. For example, the desired tangentization 2", 2
At least the date part of # is 1.4 width and length l~
1,2" is required. In other words, an area of 2 to 2.5 times the lead width is required. Of course, if the lead width is wide, (lead width) + 0.2 to 0.4" x ( It would be sufficient to have a metallized area with a brazing dimension of (length) = (lead width) x 2, but considering the practical dimensions resulting from the miniaturization of ultra-high frequency devices, this is a much larger brazing area. Width and length are required. That is, it is necessary to have a desired characteristic impedance, low inductance, and high reliability. For example, in designing and manufacturing current small containers that are resistant to thermal and mechanical balance.
気密性を考慮した場合の絶縁基板１１と枠体１２との接
合中は０．４ ”であり半導体素子３と絶縁基体１１を
接続する金属細線４′、４“のボンゲイング部の所要長
さは０．３“である。即ち、外部引出リードｌＯのロー
付面積が大部分を占める事になる。The required length of the bonding portion of the thin metal wires 4' and 4'' connecting the semiconductor element 3 and the insulating base 11 is 0.4'' during bonding between the insulating substrate 11 and the frame 12 when airtightness is considered. 0.3". In other words, the brazed area of the external lead lO occupies most of the area.
従って、基体１１のメタライズ巾はロー付部と所の３５
〜４０％にしか過ぎなくなり、之による半導体素子３か
ら外部引出リードｌｏ迄の損失祉極めて太きｂ事が分る
。勿論、絶縁基板１１の厚さを厚くしメタライズ巾を大
きくすればよいが装置自体が大型化するので実装上望ま
しくない。この改善の為にロー付部の巾を小さく長さを
短かくする必然性が発生する。その改善手段としては第
３図に示す如くロー付部の外部引出リードを細くする等
の手段をこうしればよいのであるが（賞このリードの先
端は角を落すか丸める事が望ましい）。Therefore, the metallization width of the base body 11 is 35 mm between the brazed portion and the location.
It can be seen that the loss from the semiconductor element 3 to the external lead lo is extremely large. Of course, it would be possible to increase the thickness of the insulating substrate 11 and increase the metallization width, but this would increase the size of the device itself, which is not desirable in terms of mounting. To improve this, it becomes necessary to reduce the width and length of the brazed portion. As a means to improve this, it is possible to make the external lead of the brazing part thinner as shown in FIG. 3 (it is preferable that the tip of this lead be rounded or rounded).
ベリリア上２建、り等の様にセラミックの強度が弱いも
のは基板１１に対して９０”の方向すなわち垂直方向の
強度が弱い結果が得られている。その実測値を第５図に
示す、即ち、同図中Ａ、Ｂは垂直方向の引張９強度を示
し、に、Ｂ／は水平方向の引張）強度を示す。Ａ 、
Ａ／はメタライズパターン巾とリード巾が同じでストリ
ップラインとして望ましい値を持つ友もの、Ｂ、Ｂ／は
第３図の構造のものをそれぞれ測定したものである。It has been found that ceramics with weak strength, such as Bereria Kamiken, Ri, etc., have weak strength in the 90" direction, that is, the vertical direction, with respect to the substrate 11. The measured values are shown in Fig. 5. That is, in the figure, A and B indicate the tensile strength in the vertical direction, and B/ indicates the tensile strength in the horizontal direction.
A/ is the value measured for a friend whose metallization pattern width and lead width are the same and has a desirable value as a strip line, and B and B/ are those measured for the structure shown in FIG. 3, respectively.
次に本発明の一実施例によれば、第４図に示す如く、絶
縁基板１１上面にメタライズされ喪金属配線層２＃を有
し、その配線層２′ｖ−リード線１０の先端がほぼ垂直
Ｉ／ｃｍてられ、ロー材２４でその周囲が接着されてい
る。リード線１０はロー接後配線層２を対して平行に外
部へ取り出されている。According to an embodiment of the present invention, as shown in FIG. It is vertically I/cm and its periphery is bonded with brazing material 24. The lead wire 10 is taken out to the outside parallel to the wiring layer 2 after soldering.
崗１１’は絶縁基板１１の裏面配線層である。The layer 11' is a wiring layer on the back surface of the insulating substrate 11.
かかる実施例の接合強度を＃！５図のＣ，Ｃ’に示す、
Ｃは垂直方向の接合強度 Ｑｌは水平方向の接合強度で
ある。このように垂直方向の接合強度は従来例に比して
圧倒的に強く、水平方向も遜色のないものである。之は
特にセラ電、り基板２１の周端に欠陥をもつものに極め
て有効であり、４ＩＫグリーンシート法に基くセラミッ
クの密度が不均一なもの又は成形による欠陥の発生の多
いものに有効である。しかも、実質的に垂直に曲げて取
シ付けているので、水平方向に対する応力緩衝の自由度
も大きく、リードを水平方向に押しても引いても同一な
強度が得られるように工夫されている。The bonding strength of such an example is #! Shown in C and C' in Figure 5,
C is the joint strength in the vertical direction, and Ql is the joint strength in the horizontal direction. As described above, the bonding strength in the vertical direction is overwhelmingly stronger than that of the conventional example, and the bonding strength in the horizontal direction is also comparable. This is particularly effective for ceramics that have defects on the peripheral edge of the substrate 21, and is effective for ceramics based on the 4IK green sheet method with uneven density or where many defects occur due to molding. . Moreover, since the lead is bent substantially vertically and attached, there is a large degree of freedom in absorbing stress in the horizontal direction, and the lead is devised so that the same strength can be obtained whether the lead is pushed or pulled in the horizontal direction.
次にリード２０の先端形状に関していうと、第６図（ａ
ｌに示す如く、リード２０′の巾を一様にするかもしく
け先端で広げるとロー材１４が基板２１の周辺部にたま
ってしまう。従ってかかるリード２０′よりも第６図（
ｂ）に示す如くリード２０“の先端を暫次細くしてロー
材２４がリード２０“の両側にまわシ込むようＫした９
、又は基板の内側に多くたまる様にしたものの方が接合
強度は大きくなり。Next, regarding the shape of the tip of the lead 20, see FIG.
As shown in FIG. 1, if the width of the lead 20' is made uniform but widened at the tip of the wire, the brazing material 14 will accumulate around the periphery of the substrate 21. Therefore, rather than such a lead 20', as shown in FIG.
As shown in b), the tip of the lead 20" was tapered so that the brazing material 24 was wrapped around both sides of the lead 20"9.
Or, the bonding strength will be greater if more of it accumulates inside the board.
より一層効果的である事が分った。その接合強度を第７
図に示す、同図軸のｇ 、 ｖ、ｔは第６９葎）のも示
したもので、第６図（ｂ）の方がより有効であることが
わかる。さらに第８図の如くのり−ド２０“の最先端部
を狭い同−巾として、これと連続する部分をテーパー状
に広げるようにし、最先端部をメタライズ層と平行にし
て、テーパ部分を垂直に折シ曲げるようにしてロー付け
するともつと効果が出る事が分った。It turned out to be even more effective. The joint strength is the seventh
The g, v, and t on the axes shown in the figure are also shown for the 69th axle), and it can be seen that Fig. 6(b) is more effective. Furthermore, as shown in Fig. 8, the leading edge of the glued 20'' is made narrow and the same width, and the continuous part is widened in a tapered shape.The leading edge is parallel to the metallized layer and the tapered part is vertical. I found that brazing it by bending it to the side was more effective.
以上で明らかな様に超高周波帯デバイスの如く限られた
ロー付面積を要求されたものＫついて前記の程々の佛造
が極めて望ましい事が分る。As is clear from the above, the above-mentioned moderate structure is extremely desirable for devices that require a limited soldering area, such as ultra-high frequency band devices.
同本構造については１本要旨にかなう種々の電子回路部
品について広く応用される事は言う迄もない。It goes without saying that the same structure can be widely applied to various electronic circuit components that meet the purpose of this invention.
第１図は従来の半導体容器の断面図、第２図はその構成
図、第３図は従来のリード取付部の平面図、第４図は本
発明の一実施例の平面図、第５図は従来および本発明の
リードの取付強度を示すグラフである。
第６図（ＩＩ） 、 （ｂ）は本発明の他の実施例を示
す部分斜視図、第７図はその接合強度を示すグラフであ
る。第８図は本発明の更に他の実施例によるリードの平
面図である。
２・・・・・・メタライズ層、３・・・・・・半導体素
子、４・・・・・・金属細線、６・・・・・・金属スタ
ッド、７・・・・・・補助スタッド、 １０，２０．
２０’、２０’、２０’・・・・・・外部引出リード、
１１．２１・・・・・・絶縁基板、 １１’、２１′−
・・・・・メタ＄／図
第３日
第４５２１
Ｄ−イ寸禾ｆ↑と度数分布
第 左 目
第７図FIG. 1 is a sectional view of a conventional semiconductor container, FIG. 2 is a configuration diagram thereof, FIG. 3 is a plan view of a conventional lead attachment part, FIG. 4 is a plan view of an embodiment of the present invention, and FIG. 5 is a graph showing the attachment strength of the conventional lead and the lead of the present invention. FIGS. 6(II) and (b) are partial perspective views showing another embodiment of the present invention, and FIG. 7 is a graph showing the bonding strength thereof. FIG. 8 is a plan view of a lead according to still another embodiment of the present invention. 2...metalized layer, 3...semiconductor element, 4...metal thin wire, 6...metal stud, 7...auxiliary stud, 10,20.
20', 20', 20'...external drawer lead,
11.21...Insulating substrate, 11', 21'-
・・・・・・Meta$/Figure 3rd day 4521 D-I dimension f↑ and frequency distribution Left eye Figure 7
Claims (1)
を有するメタライズ配線層と、前記絶縁基板に取〕付け
られた電子回路部品と、前記メタライズ配線層の前記リ
ード取シ付は部に取り付けられた外部導出用金属リード
とを有し、前記外部導出用金属リードの先端は前記メタ
ライズ配線層のリード取り付は部に対してほぼ垂直に曲
けられて取）付けられていることを特徴とする半導体装
置。an insulating substrate, a metallized wiring layer having a 'J-do mounting section on the periphery of the insulating substrate, an electronic circuit component attached to the insulating substrate, and the lead attachment part of the metallized wiring layer. has a metal lead for leading out to the outside attached to the part, and the tip of the metal lead for leading out to the outside is bent and attached almost perpendicularly to the part for lead attachment of the metallized wiring layer. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9732182A JPS584962A (en) | 1982-06-07 | 1982-06-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9732182A JPS584962A (en) | 1982-06-07 | 1982-06-07 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11719477A Division JPS5391578A (en) | 1977-09-28 | 1977-09-28 | Container for electronic part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS584962A true JPS584962A (en) | 1983-01-12 |
Family
ID=14189212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9732182A Pending JPS584962A (en) | 1982-06-07 | 1982-06-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS584962A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62197701A (en) * | 1986-02-25 | 1987-09-01 | Tokyo Seimitsu Co Ltd | Measuring device for 3-dimensional shape |
| JPS63238417A (en) * | 1987-03-27 | 1988-10-04 | Okuma Mach Works Ltd | Three-dimensional measuring method in digitizer |
-
1982
- 1982-06-07 JP JP9732182A patent/JPS584962A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62197701A (en) * | 1986-02-25 | 1987-09-01 | Tokyo Seimitsu Co Ltd | Measuring device for 3-dimensional shape |
| JPS63238417A (en) * | 1987-03-27 | 1988-10-04 | Okuma Mach Works Ltd | Three-dimensional measuring method in digitizer |
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