JPS5847928U - Reference clock signal generation circuit for data processing equipment - Google Patents
Reference clock signal generation circuit for data processing equipmentInfo
- Publication number
- JPS5847928U JPS5847928U JP14040381U JP14040381U JPS5847928U JP S5847928 U JPS5847928 U JP S5847928U JP 14040381 U JP14040381 U JP 14040381U JP 14040381 U JP14040381 U JP 14040381U JP S5847928 U JPS5847928 U JP S5847928U
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- reference clock
- data processing
- frequency
- signal generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の全体ブロック図、第2図は本考案の実
施例の1つで、発振回路の部分を詳細化−したブロック
図、第3図は本考案の他の実施例で、発振回路の部分を
詳細化したブロック図である。
100・・・レジスタ、200・・・発振回路、300
・・・クロックトライバ回路、210・・・基準発振器
、220・・・分周器(可変)、23−0・・・位相比
較器、240・・・分周器(固定)、250・・・低域
通過フィルタ、260・・・電圧制御発振器。Fig. 1 is an overall block diagram of the present invention, Fig. 2 is an embodiment of the present invention, and a detailed block diagram of the oscillation circuit, and Fig. 3 is another embodiment of the invention. FIG. 2 is a detailed block diagram of an oscillation circuit. 100...Register, 200...Oscillation circuit, 300
...Clock driver circuit, 210... Reference oscillator, 220... Frequency divider (variable), 23-0... Phase comparator, 240... Frequency divider (fixed), 250... -Low pass filter, 260...voltage controlled oscillator.
Claims (1)
るクロック信号発生装置において、データ処理装置から
値を書きこむことのできるレジスタと、 このレジスタの出力値により分周比の変わる分周器と、
入力電圧によって発振周波数の変わる電圧制御発振器と
、基準となる周波数を発振する基準発振器とを系内に持
ち、前記基準発振器の発振周波数f。と電圧制御発振器
の発振周波数Fとの間に F=(m/n)・f (但しm、 nは整数) の関係を持ち、前記分周器の分周比により、上式中のm
、 nのいずれかが変化する位相同期系から構成され
る発振回路からなり、 前記発振回路の出力すなわち基準クロック信号として前
記電圧制御発振器の出力を使用し、前記データ処理装置
から前記レジスタへの値の書き込みにより、前記基準ク
ロック信号の出力を中断することなく、その周波数を変
化させることを特徴とするデータ処理装置の基準クロッ
ク信号発生回路。[Claims for Utility Model Registration] A clock signal generation device that generates a reference clock signal to be supplied to a data processing device includes a register into which a value can be written from the data processing device, and a frequency division ratio based on the output value of this register. A frequency divider that changes
The system includes a voltage controlled oscillator whose oscillation frequency changes depending on the input voltage and a reference oscillator that oscillates at a reference frequency, and the oscillation frequency f of the reference oscillator. The relationship between F and the oscillation frequency F of the voltage controlled oscillator is F=(m/n)・f (where m and n are integers), and depending on the frequency division ratio of the frequency divider, m in the above equation
, an oscillation circuit constituted by a phase synchronized system in which either of n changes, and the output of the voltage controlled oscillator is used as the output of the oscillation circuit, that is, the reference clock signal, and the value from the data processing device to the register is 1. A reference clock signal generation circuit for a data processing device, characterized in that the frequency of the reference clock signal is changed by writing of the reference clock signal without interrupting output of the reference clock signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14040381U JPS5847928U (en) | 1981-09-24 | 1981-09-24 | Reference clock signal generation circuit for data processing equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14040381U JPS5847928U (en) | 1981-09-24 | 1981-09-24 | Reference clock signal generation circuit for data processing equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5847928U true JPS5847928U (en) | 1983-03-31 |
Family
ID=29933565
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14040381U Pending JPS5847928U (en) | 1981-09-24 | 1981-09-24 | Reference clock signal generation circuit for data processing equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5847928U (en) |
-
1981
- 1981-09-24 JP JP14040381U patent/JPS5847928U/en active Pending
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