JPS5847597Y2 - memory device - Google Patents
memory deviceInfo
- Publication number
- JPS5847597Y2 JPS5847597Y2 JP1977105911U JP10591177U JPS5847597Y2 JP S5847597 Y2 JPS5847597 Y2 JP S5847597Y2 JP 1977105911 U JP1977105911 U JP 1977105911U JP 10591177 U JP10591177 U JP 10591177U JP S5847597 Y2 JPS5847597 Y2 JP S5847597Y2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- voltage
- battery
- power
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Stand-By Power Supply Arrangements (AREA)
Description
【考案の詳細な説明】
本案は停電時にメモリーを電池出力によって作動させ、
停電回復時に電池の正常動作をチェックする事によって
メモリーの内容の良否を判定するメモリー装置に関する
。[Detailed explanation of the invention] This invention operates the memory using battery output during a power outage.
The present invention relates to a memory device that determines whether the contents of the memory are good or not by checking the normal operation of the battery when the power is restored.
一般に揮発性メモリーを使用する場合に、常時メモリー
に電力を供給しなければならないので、通常のメモリー
電源としては二次電池が併用されているが、それでも長
時間の停電の際には電池電圧の低下が生じ、メモリー内
容が破壊される事となる。Generally, when using volatile memory, it is necessary to constantly supply power to the memory, so a secondary battery is also used as a normal memory power source, but even then, the battery voltage will drop during a long power outage. This will cause the memory contents to be destroyed.
本案は上記の点に鑑みて停電回復時に電池電圧をチェッ
クし、メモリー内容の良否を判定するメモリー装置を提
供するものである。In view of the above points, the present invention provides a memory device that checks the battery voltage upon recovery from a power outage and determines whether the memory contents are good or bad.
第１図は本案の実施例の回路図で、第２図は第１図の動
作波形図である。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is an operation waveform diagram of FIG. 1.
図に於いて１はＣ−ＭＯＳで構成された揮発性のメモリ
ーで、通常は商用電源からの直流電圧ｖａが抵抗Ｒ１ダ
イオードＤＩ 、Ｄ２を介して供給され、停電時には電
池２の電圧ｖｂが抵抗Ｒ２ダイオードＤ１を介して供給
されるので、記憶内容が常時保護される。In the figure, 1 is a volatile memory composed of C-MOS, and normally DC voltage va from the commercial power supply is supplied through resistors R1 and diodes DI and D2, and in the event of a power outage, the voltage vb of battery 2 is supplied to the resistor. Since it is supplied via the R2 diode D1, the stored contents are always protected.
Ｃ−ＭＯＳのメモリーは消費電力が非常に少ないので停
電時でも充分メモリー１は作動するが、長時間停電した
場合はメモリー１内容が破壊される惧れがある。Since C-MOS memory consumes very little power, the memory 1 can operate satisfactorily even during a power outage, but there is a risk that the contents of the memory 1 will be destroyed if the power goes out for a long time.
３は電池２の電圧検出する回路で、ツェナーダイオード
ＺＤとトランジスタＴｒと抵抗Ｒ３，Ｒ４，Ｒ５とから
構成され、電池２の電圧ｖｂが一定電圧以下になるとツ
ェナーダイオードＺＤが不導通になり、トランジスタＴ
ｒがオフになってトランジスタＴ。3 is a circuit for detecting the voltage of the battery 2, which is composed of a Zener diode ZD, a transistor Tr, and resistors R3, R4, and R5. When the voltage vb of the battery 2 falls below a certain voltage, the Zener diode ZD becomes non-conductive, and the transistor T
r is turned off and transistor T.
の出力電圧Ｖ。The output voltage V.
が電池２の電圧ｖｂと同一になる。４は単安定マルチ回
路で、電源電圧Ｖａが停電から回復すると単一信号を発
生し、ツアーゲートＮＲにてトランジスタＴ の出力電
圧Ｖ。becomes the same as the voltage vb of battery 2. 4 is a monostable multi-circuit that generates a single signal when the power supply voltage Va recovers from a power outage, and the output voltage V of the transistor T at the tour gate NR.
との条件が取られる。The condition is taken.
第２図を用いて停電中に電池２の電圧ｖｂが規定電圧よ
り低下した場合について説明する。A case where the voltage vb of the battery 2 drops below the specified voltage during a power outage will be explained using FIG. 2.
電源電圧Ｖａが回復すると抵抗Ｒ１，Ｒ２を介して電池
２に充電々流が流れるが、電池２の電圧ｖｂはすぐには
正常な電圧に回復しない。When the power supply voltage Va recovers, a charging current flows to the battery 2 via the resistors R1 and R2, but the voltage vb of the battery 2 does not immediately recover to a normal voltage.
電源電圧Ｖａが回復すると単安定マルチ回路４から出力
Ｖｄが発生し、電池２の電圧ｖｂが規定電圧以下のため
検出回路３のトランジスタＴｒがオフし、出力電圧Ｖ。When the power supply voltage Va recovers, an output Vd is generated from the monostable multicircuit 4, and since the voltage vb of the battery 2 is below the specified voltage, the transistor Tr of the detection circuit 3 is turned off, and the output voltage V.
は電池２の電圧ｖｂと同一になる。このためノアーゲー
）ＮＲに於いては二人力が負であるため正の出力が発生
する。becomes the same as the voltage vb of battery 2. For this reason, in Noah Game) NR, since the two-person force is negative, a positive output is generated.
つまり、電源電圧Ｖａの回復時に電池２が規定電圧以下
である事が検出される。That is, when the power supply voltage Va is restored, it is detected that the voltage of the battery 2 is below the specified voltage.
その後電池２の電圧が規定電圧になるとトランジスタＴ
がオンし、出力電圧Ｖ。After that, when the voltage of battery 2 reaches the specified voltage, transistor T
turns on and the output voltage V.
が正になる。becomes positive.
さらに上記ツアーゲートＮＲの正の出力によって特殊記
号の印字又はブザーによる警報ざらにフリップフロップ
等を用いた記憶を行なって表示する事によってメモリー
１内容が破壊されている事を使用者に知らせる。Further, the user is informed that the contents of the memory 1 have been destroyed by printing a special symbol in response to the positive output of the tour gate NR or by memorizing and displaying the memory using a flip-flop or the like in response to a warning from a buzzer.
また上記のツアーゲートＮＲの出力はメモリー１の内容
が不良である事を示すものであるので、メモリー１を使
用する制御回路にイニシャルクリヤー信号として与えて
メモリー１の不良時に自動的にクリアー動作を行なわせ
る事もできる。Furthermore, since the output of the tour gate NR mentioned above indicates that the contents of memory 1 are defective, it is given as an initial clear signal to the control circuit that uses memory 1, so that it automatically performs a clear operation when memory 1 is defective. You can also make them do it.
以上の如く、本案は通常は商用電源からの電力によって
作動する揮発性メモリーを停電時に電池で保護するメモ
リー装置に於いて、電池の正常動作を検出する回路と、
該回路の出力を停電回復時にチェックする手段とを設け
、停電回復時にメモリー内容の良否を判定するもので、
停電が伺回発生しても電池電圧が正常であればメモリー
内容を良とし、停電時に電池電圧が規定電圧以下に低下
した場合は停電回復時にメモリーの不良を確実に通報す
る事ができ、不揮発性メモリーの不良を容易に知る事が
できる。As described above, the present invention provides a circuit for detecting normal operation of a battery in a memory device in which a volatile memory that normally operates using power from a commercial power source is protected by a battery during a power outage.
means for checking the output of the circuit when the power is restored, and determining whether the memory contents are good or bad when the power is restored;
Even if a power outage occurs repeatedly, if the battery voltage is normal, the memory contents are assumed to be good. If the battery voltage drops below the specified voltage during a power outage, it is possible to reliably report a memory defect when the power is restored, and it is non-volatile. You can easily find out if your sexual memory is defective.
第１図は本案の実施例を示す回路図、第２図は第１図の
動作を説明する波形図である。
図に於いて１は不揮発性メモリー、２は電池、３は電圧
検出回路、４は単安定マルチ回路である。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram explaining the operation of FIG. 1. In the figure, 1 is a non-volatile memory, 2 is a battery, 3 is a voltage detection circuit, and 4 is a monostable multi-circuit.
Claims (1)
リーを停電時に電池で保護するメモリー装置に於いて、
電池の正常動作を検出する回路と、該回路の出力を停電
回復時にチェックする手段とを設け、停電回復時にメモ
リー内容の良否を判定する事を特徴とするメモリー装置
。In memory devices, volatile memory, which is normally powered by commercial power, is protected by batteries during power outages.
A memory device comprising a circuit for detecting normal operation of a battery and a means for checking the output of the circuit upon recovery from a power outage, and determining whether the memory contents are good or bad at the time of recovery from a power outage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1977105911U JPS5847597Y2 (en) | 1977-08-05 | 1977-08-05 | memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1977105911U JPS5847597Y2 (en) | 1977-08-05 | 1977-08-05 | memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5433032U JPS5433032U (en) | 1979-03-03 |
| JPS5847597Y2 true JPS5847597Y2 (en) | 1983-10-29 |
Family
ID=29048606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1977105911U Expired JPS5847597Y2 (en) | 1977-08-05 | 1977-08-05 | memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5847597Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5185602A (en) * | 1975-01-25 | 1976-07-27 | Torio Kk |
-
1977
- 1977-08-05 JP JP1977105911U patent/JPS5847597Y2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5185602A (en) * | 1975-01-25 | 1976-07-27 | Torio Kk |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5433032U (en) | 1979-03-03 |
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