JPS5846167B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5846167B2 JPS5846167B2 JP54171024A JP17102479A JPS5846167B2 JP S5846167 B2 JPS5846167 B2 JP S5846167B2 JP 54171024 A JP54171024 A JP 54171024A JP 17102479 A JP17102479 A JP 17102479A JP S5846167 B2 JPS5846167 B2 JP S5846167B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor substrate
- metal layer
- substrate
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に高い放熱性
を要求される半導体素子への電極形成法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming electrodes on a semiconductor element that requires high heat dissipation.
高出力トランジスタ等大電力を扱う半導体素子にあって
は、その二次降伏を防止するために、その動作時半導体
基板のＰＮ接合部において発生する熱をすみやかに放散
させることが要求される。Semiconductor elements that handle large amounts of power, such as high-output transistors, are required to quickly dissipate heat generated at the PN junction of the semiconductor substrate during operation in order to prevent secondary breakdown.
このため前記高出力トランジスタ例えばバイポーラパワ
ートランジスタにあっては、コレクタを構成する半導体
基板背面を削り、薄くし、更に該基板背面全面にコレク
タ電極として銅、銀等の熱伝導性の優れた金属層を配設
することが提案されている。For this reason, in the case of the above-mentioned high-output transistors, such as bipolar power transistors, the back surface of the semiconductor substrate constituting the collector is shaved to make it thinner, and a metal layer with excellent thermal conductivity such as copper or silver is layered on the entire back surface of the substrate as the collector electrode. It is proposed that the
しかしながら、前記熱伝導性の優れた金属層は、半導体
基板との密着性が低く後工程において剥離し易く、また
コレクタを構成する半導体基板部分は一般に不純物濃度
が低いため良好な抵抗性（オーミック）接触が得られな
いという問題が存在する。However, the metal layer with excellent thermal conductivity has poor adhesion with the semiconductor substrate and is easily peeled off in subsequent processes, and the semiconductor substrate portion that constitutes the collector generally has a low impurity concentration and therefore has good resistance (ohmic). There is a problem of not being able to get in touch.
本発明は、このような大電力を扱う半導体素子に密着性
良く且つ良好な抵抗性接触をもって熱伝導性の優れた電
極を形成することができる方法を提供しようとするもの
である。The present invention aims to provide a method for forming an electrode with good adhesion, good resistance contact, and excellent thermal conductivity on a semiconductor element that handles such a large amount of power.
このため、本発明によれば、素子が形成された半導体基
板の背（裏）面に、前記半導体基板と密着性の良い第１
の金属層を形成する工程と、前記第１の金属層上に前記
半導体基板と共晶反応を生じる第２の金属層を形成する
工程と、前記第２の金属層上に熱伝導性の優れた第３の
金属層を形成する工程と、熱処理し、前記第１の金属層
を通して前記半導体基板と前記第２の金属層との共晶化
反応を行なう工程とを有することを特徴とする半導体装
置の製造方法が提供される。Therefore, according to the present invention, a first layer having good adhesion to the semiconductor substrate is provided on the back (back) surface of the semiconductor substrate on which elements are formed.
forming a second metal layer on the first metal layer that causes a eutectic reaction with the semiconductor substrate; and forming a second metal layer on the second metal layer having excellent thermal conductivity. a step of forming a third metal layer, and a step of heat-treating and performing a eutectic reaction between the semiconductor substrate and the second metal layer through the first metal layer. A method of manufacturing a device is provided.
次に本発明を実施例をもって詳細に説明しよう。Next, the present invention will be explained in detail using examples.
第１図〜第４図は本発明にかかる半導体装置の製造方法
を示す。1 to 4 show a method of manufacturing a semiconductor device according to the present invention.
本発明によれば、まず第１図に示すように、例えばＮ型
を有するシリコン（Ｓｉ）基板１１に、周知の方法によ
り硼素［Ｆ］）等の不純物を導入してＰ型ベース領域１
２が形成され、更に該ベース領域１２内に燐１（Ｐ）等
の不純物を導入してＮ型エミッタ領域１３が形成され、
更に該ベース領域１２及び工□ツタ領域１゛３からアル
ミニウム（Ａ１）等からなる電極１４及び１５が該シリ
コン基板１１の表面を覆う二酸化シリコン（ＳＩＯ２）
等からなる絶縁皮膜１６上に導出されてなる半導体基板
（ウェハー）を準備する。According to the present invention, first, as shown in FIG. 1, an impurity such as boron [F] is introduced into a silicon (Si) substrate 11 having an N type by a well-known method to form a P type base region 1.
2 is formed, and further an impurity such as phosphorus 1 (P) is introduced into the base region 12 to form an N-type emitter region 13,
Furthermore, electrodes 14 and 15 made of aluminum (A1) or the like are formed from silicon dioxide (SIO2) covering the surface of the silicon substrate 11 from the base region 12 and the ivy region 1-3.
A semiconductor substrate (wafer) is prepared by being drawn out on an insulating film 16 made of the following.
そして該半導体基板をワックス１７によりガラス基板１
８に固着し、周知の化学的及び機械的研磨によりシリコ
ン基板１１の背面を研磨し、その厚さを３０（μｍ〕以
下とする。Then, the semiconductor substrate is attached to the glass substrate 1 by wax 17.
8, and the back surface of the silicon substrate 11 is polished by well-known chemical and mechanical polishing to a thickness of 30 (μm) or less.
かかる状態を第２図に示す。Such a state is shown in FIG.
本発明によれば、次いで該シリコン基板１１の背面に厚
さ５００（４）程のニクロム（Ｎｉ−Ｃｒ、Ｎｉ８０％
、Ｃｒ ２０１％＝ｌ）層１９を被着形成する。According to the present invention, the back surface of the silicon substrate 11 is then coated with nichrome (Ni-Cr, 80% Ni) having a thickness of about 500 (4).
, Cr 201%=l) layer 19 is deposited.
該ニクロム層１９はシリコンとの密着性が良好である。The nichrome layer 19 has good adhesion to silicon.
該ニクロム層１９は周知の蒸着法によって形成すること
ができる。The nichrome layer 19 can be formed by a well-known vapor deposition method.
そして該ニクロム層１９を覆って厚さ２０００＋ＡＩ程
の金−アンチモン（ＡｕＳｂ、Ｓｂ０．５層％ｌ）層２
０を被着形成する。Then, covering the nichrome layer 19, a gold-antimony (AuSb, Sb0.5 layer %l) layer 2 having a thickness of about 2000 + AI
0 is deposited and formed.
該金アンチモン層２０も蒸着法によって形成することが
できる。The gold-antimony layer 20 can also be formed by a vapor deposition method.
かかる状態を第３図に示す。Such a state is shown in FIG.
次いで前記金−アンチモン層２０土に選択的にフォト・
レジスト層２１を形成し、該フォトレジスト層２１をマ
スクとして銅（Ｃｕ）あるいは銀（Ａｇ）層２２を厚さ
５０〜６０〔μｍ〕にめっきする。Then, selective photo-coating was applied to the gold-antimony layer 20 soil.
A resist layer 21 is formed, and a copper (Cu) or silver (Ag) layer 22 is plated to a thickness of 50 to 60 [μm] using the photoresist layer 21 as a mask.
そして更に該銅あるいは銀層２２上に金（Ａｕ７層を厚
さ５〜６〔μｍ〕にめっきする。Further, gold (Au7 layer) is plated on the copper or silver layer 22 to a thickness of 5 to 6 [μm].
この状態を第４図に示す。This state is shown in FIG.
しかる後前記フォト・レジスト層２１を除去し、更にワ
ックス１１を除去して半導体基板をガラス基板１８と分
離する。Thereafter, the photoresist layer 21 is removed, and the wax 11 is further removed to separate the semiconductor substrate from the glass substrate 18.
そして該半導体基板を加熱炉中に配置して、３７０（’
ＣＴｈ上に加熱し、前記ニクロム層１９を通してシリコ
ン基板１１と金−アンチモン層２０との共晶合金化処理
を行う。Then, the semiconductor substrate is placed in a heating furnace, and
CTh is heated to perform eutectic alloying treatment between the silicon substrate 11 and the gold-antimony layer 20 through the nichrome layer 19.
この共晶化処理により良好な抵抗性接触が形成される。This eutecticization process forms a good resistive contact.
以上のような本発明によれば、金−アンチモン層とシリ
コン基板との共晶により低抵抗をもって抵抗性接触が形
成されるとともに、銅あるいは銀等の熱伝導性の優れた
金属はニクロム層及び金−アンチモン層を介して形成さ
れるため高い密着性をもってシリコン基板上に配設され
る。According to the present invention as described above, a resistive contact is formed with low resistance by the eutectic of the gold-antimony layer and the silicon substrate, and a metal with excellent thermal conductivity such as copper or silver is used as the nichrome layer and the silicon substrate. Since it is formed through a gold-antimony layer, it can be disposed on a silicon substrate with high adhesion.
したがって、かかる構造を有する半導体装置は、十分に
大きな電力を扱うことが可能となる。Therefore, a semiconductor device having such a structure can handle sufficiently large power.
前記実施例に示した方法を適用してコレクタ電極を構成
したトランジスタは、コレクタとベース間に順方向電流
を８００ （ｍＡ）流すのに要する電圧Ｖが１．２〜１
．４［Ｖ］であって、従来２．０〜２．２ ［Ｖ］必要
としていたのに比較して抵抗性接触部の抵抗が低くされ
たことは明らかである。In the transistor whose collector electrode was constructed by applying the method shown in the above embodiment, the voltage V required to flow a forward current of 800 (mA) between the collector and the base was 1.2 to 1.
．． It is clear that the resistance of the resistive contact portion has been lowered by 4 [V] compared to the conventionally required 2.0 to 2.2 [V].
なお、前記共晶化処理は、当該半導体基板を分割して個
々のトランジスタチップとし、該トランジスタチップを
金属ステム等に固着する際の熱処理をもって実施しても
よい。Note that the eutectic treatment may be performed by dividing the semiconductor substrate into individual transistor chips and performing heat treatment when fixing the transistor chips to a metal stem or the like.
また、本発明は前記実施例に限られず、他の半導体素子
に適用し得ることはもちろんである。Furthermore, the present invention is not limited to the above-mentioned embodiments, and can of course be applied to other semiconductor devices.
第１図乃至第４図は、本発明にかかる半導体装置の製造
工程を示す断面図である。
第１図は半導体基板に素子を形成した状態を示し、第２
図は該半導体基板をガラス基板に固着した状態を示し、
第３図及び第４図は該半導体基板の背面に金属層を形成
した状態を示す。
図において、１１・・・・・・シリコン基板、１９・・
・・・・ニクロム層、２０・・・・・・金−アンチモン
層、２２・・・・・・熱伝導性の優れた金属。1 to 4 are cross-sectional views showing the manufacturing process of a semiconductor device according to the present invention. FIG. 1 shows a state in which elements are formed on a semiconductor substrate, and the second
The figure shows the semiconductor substrate fixed to a glass substrate,
3 and 4 show a state in which a metal layer is formed on the back surface of the semiconductor substrate. In the figure, 11... silicon substrate, 19...
... Nichrome layer, 20 ... Gold-antimony layer, 22 ... Metal with excellent thermal conductivity.
Claims (1)
基板と密着性の良い第１の金属層を形成する工程と、前
記第１の金属層上に前記半導体基板と共晶反応を生じる
第２の金属層を形成する工程と、前記第２の金属層上ｌ
こ熱伝導性の優れた第３の金属層を形成する工程と、熱
処理し、前記第１の金属層を通して前記半導体基板と前
記第２の金属層との共晶化反応を行う工程とを有するこ
とを特徴とする半導体装置の製造方法。1. A step of forming a first metal layer having good adhesion to the semiconductor substrate on the back surface of the semiconductor substrate on which an element is formed, and a second step of causing a eutectic reaction with the semiconductor substrate on the first metal layer. forming a metal layer on the second metal layer;
The method includes a step of forming a third metal layer having excellent thermal conductivity, and a step of performing a heat treatment to cause a eutectic reaction between the semiconductor substrate and the second metal layer through the first metal layer. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54171024A JPS5846167B2 (en) | 1979-12-28 | 1979-12-28 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54171024A JPS5846167B2 (en) | 1979-12-28 | 1979-12-28 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5694736A JPS5694736A (en) | 1981-07-31 |
| JPS5846167B2 true JPS5846167B2 (en) | 1983-10-14 |
Family
ID=15915668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54171024A Expired JPS5846167B2 (en) | 1979-12-28 | 1979-12-28 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5846167B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6069802U (en) * | 1983-10-13 | 1985-05-17 | 笠井 琴雄 | variable pressure regulator |
| JPH07133889A (en) * | 1993-11-10 | 1995-05-23 | Kato Spring Seisakusho:Kk | Contraflow prevention connector |
| US10107241B2 (en) | 2014-06-16 | 2018-10-23 | Denso Corporation | Valve device and high-pressure pump using the same |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102006046789A1 (en) * | 2006-10-02 | 2008-04-03 | Infineon Technologies Ag | Electronic component e.g. isolated gate bipolar transistor, has layer region that is electrically conductively arranged at thinned wafers, where layer thickness of layer region is larger than specific micrometers |
| CN102522326B (en) * | 2011-12-14 | 2014-09-24 | 杭州立昂微电子股份有限公司 | Production method of semiconductor discrete device back side metal suitable for screen printing |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4855664A (en) * | 1971-11-12 | 1973-08-04 | ||
| JPS5023173A (en) * | 1973-06-28 | 1975-03-12 |
-
1979
- 1979-12-28 JP JP54171024A patent/JPS5846167B2/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4855664A (en) * | 1971-11-12 | 1973-08-04 | ||
| JPS5023173A (en) * | 1973-06-28 | 1975-03-12 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6069802U (en) * | 1983-10-13 | 1985-05-17 | 笠井 琴雄 | variable pressure regulator |
| JPH07133889A (en) * | 1993-11-10 | 1995-05-23 | Kato Spring Seisakusho:Kk | Contraflow prevention connector |
| US10107241B2 (en) | 2014-06-16 | 2018-10-23 | Denso Corporation | Valve device and high-pressure pump using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5694736A (en) | 1981-07-31 |
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