JPS5843684B2 - Genten Shingo Kenshiyutsuhouhou - Google Patents
Genten Shingo KenshiyutsuhouhouInfo
- Publication number
- JPS5843684B2 JPS5843684B2 JP13773875A JP13773875A JPS5843684B2 JP S5843684 B2 JPS5843684 B2 JP S5843684B2 JP 13773875 A JP13773875 A JP 13773875A JP 13773875 A JP13773875 A JP 13773875A JP S5843684 B2 JPS5843684 B2 JP S5843684B2
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- origin
- signal
- signals
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
- Length Measuring Devices With Unspecified Measuring Means (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
Description
【発明の詳細な説明】
本発明は、長さや角度の増分方式の測定装置における原
点を一時的に求める原点信号検出方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an origin signal detection method for temporarily determining the origin in an incremental length or angle measuring device.
増分方式のエンコーダからの出力信号は９０゜の位相差
をもって現われる（第１図ａの信号Ａ。The output signals from the incremental encoder appear with a phase difference of 90° (signal A in FIG. 1a).
Ｂ）。B).
この信号Ａ、Ｂの矩形波出力は第１図す。Ｃに示す通り
である。The rectangular wave outputs of the signals A and B are shown in FIG. As shown in C.
順方向に計数した際のパルス及び逆方向計数のパルスを
それぞれ第１図ｄ。The pulses when counting in the forward direction and the pulses when counting in the backward direction are shown in FIG. 1d, respectively.
ｅに示す。Shown in e.
−１，０、＋１・・・・・・等は任意のＰ点で零リセッ
トしたときのカウンターの表示である。-1, 0, +1, etc. are the counter displays when the counter is reset to zero at any P point.
このディジタル増分方式では、任意の位置でゼロリセッ
トが出来る。This digital incremental method allows zero reset at any position.
しかし、ディジタルエラーが避けられない；原点が決っ
ていないために精度測定の基準がない、あるいは精度よ
く原点に復帰させることができない、等の欠点がある。However, digital errors are unavoidable; since the origin is not determined, there is no standard for accuracy measurement, or it is not possible to accurately return to the origin.
すなわち、第１図の任意のＰ点でゼロリセットしたとす
ると、順方向に計数する場合を考えると第１図ｄのＰ、
Ｑ間か１デイジツト分の長さより短かいにもかかわらず
Ｑ点を過ぎると「＋１」とカウンターに表示してしまう
。That is, if we reset to zero at an arbitrary point P in Figure 1, then when counting in the forward direction, P in Figure 1 d,
Even though the length is shorter than the Q interval or one digit, when the Q point is passed, "+1" is displayed on the counter.
逆方向に計数する場合についても同様に、このディジタ
ルエラーが発生する。This digital error also occurs when counting in the opposite direction.
また、上記のような信号を出力する増分方式エンコーダ
の再現性の測定を行う場合、正確に原点に復帰させよう
とすると、Ｐ点を測定の基準として検出する装置（例え
は、電子マイクロメータやリミットスイッチあるいは第
１図のような原点信号を発生させるためにエンコーダの
スケール上の１個所のみから信号を出力するための信号
系）を別に用意しなければならない。In addition, when measuring the repeatability of an incremental encoder that outputs a signal like the one above, if you want to accurately return to the origin, it is necessary to use a device that detects point P as a measurement reference (for example, an electronic micrometer or A limit switch or a signal system (signal system for outputting a signal from only one point on the scale of the encoder) must be separately prepared in order to generate the origin signal as shown in FIG.
また、累積精度を測定する場合でも、ｎディジット（ｎ
は整数）だけの精度を他の測長装置で測定しようとする
と１＋ｎ“のカウンターの表示を示す範囲は１デイジツ
トたけあるので、正確にｎディジットの精度測定が行な
えないことになる。Also, even when measuring cumulative accuracy, n digits (n
If an attempt is made to measure the precision of only n digits with another length measuring device, the range in which the counter displays 1+n'' is 1 digit long, so it will not be possible to accurately measure the precision of n digits.
本発明は、以上のような従来の増分方式のエンコーダに
避けられない欠点を解決する原点信号検出方法の提供を
目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide an origin signal detection method that solves the above-mentioned drawbacks of conventional incremental encoders.
以下に、０°、９００の正弦波２信号を出力する増分方
式のエンコーダを例にとって本発明による原点信号検出
回路の実施例を説明する。An embodiment of the origin signal detection circuit according to the present invention will be described below, taking as an example an incremental encoder that outputs two 0° and 900 sine wave signals.
第２図では、Ｏ０相信号と９０°相信号をそれぞれ抵抗
２，３を通して入れこの両抵抗の接続点に加算増幅器１
と抵抗４とを並列接続する。In Figure 2, the O0 phase signal and the 90° phase signal are passed through resistors 2 and 3, respectively, and a summing amplifier 1 is connected to the connection point between these two resistors.
and resistor 4 are connected in parallel.
これによりベクトル台底した信号例えば４５° （又は
２２５° ）の正弦波信号を出力する。This outputs a signal with a vector base, for example, a 45° (or 225°) sine wave signal.
第３図では、０°相信号と９０°相信号をそれぞれバッ
ファアンプ５，６を通して入れ、この両バッファアンプ
の出力信号を直列接続した抵抗７゜８に入力して両抵抗
の接続点からベクトル合成した信号例えば４５°の正弦
波信号をとり出している。In Figure 3, the 0° phase signal and the 90° phase signal are input through buffer amplifiers 5 and 6, respectively, and the output signals of both buffer amplifiers are input to a resistor 7°8 connected in series, and a vector is generated from the connection point of both resistors. A synthesized signal, for example a 45° sine wave signal, is extracted.
第４図において、ａは、００９０° ４５゜の正弦波信
号を、ｂはＯ０信号の矩形波、Ｃは４５°の矩形波、ｄ
は９０°の矩形波、ｅは周知の方法によって計数した９
０°矩形波のカフントパルス列、ｆは周知の方法によっ
て計数した４５゜矩形波の合成位相パルス列（図には理
解を容易にするため矩形波の立下り点でパルスを発生さ
せているが立上り点でも同様な作動が可能なことは容易
に理解できる。In Figure 4, a is a 0090° 45° sine wave signal, b is a rectangular wave of the O0 signal, C is a 45° rectangular wave, and d
is a 90° square wave, and e is 9 calculated by a well-known method.
Cafund pulse train of 0° square wave, f is composite phase pulse train of 45° square wave counted by a well-known method (in the figure, a pulse is generated at the falling point of the square wave for ease of understanding, but the pulse is generated at the falling point of the rectangular wave, but the rising It is easy to understand that a similar operation is also possible at points.
）ｇはカウンター表示状態″０“を検出したゼロ信号、
ｈは原点パルスを示す。) g is the zero signal that detected the counter display state "0",
h indicates the origin pulse.
原点パルスｈはパルス列ｆとカウンタのＯ状態を示す信
号ｇとの論理積として得られているものである。The origin pulse h is obtained as the logical product of the pulse train f and the signal g indicating the O state of the counter.
本発明では原点パルスｈをエンコーダ装置の基準原点と
する。In the present invention, the origin pulse h is used as the reference origin of the encoder device.
以上に本発明の詳細な説明する。The present invention will now be described in detail.
エンコーダ装置のカウンターはパルス列ｅを計数するも
のであるが操作者によりゼロリセットされうる。The counter of the encoder device counts the pulse train e and can be reset to zero by the operator.
今、エンコーダがｐ点に対応する位置にあるとき、カウ
ンターがリセットされたとする。Suppose now that the counter is reset when the encoder is at a position corresponding to point p.
この位置からエンコーダを第４図の右方向に動かしてい
ってパルス列ｅの最初に来るパルスの立上り（パルスの
左エツジ）でカウンタはＯ状態でなくなる。As the encoder is moved to the right in FIG. 4 from this position, the counter is no longer in the O state at the rising edge of the first pulse (left edge of the pulse) of the pulse train e.
第４図の例ではカウンタが０状態でなくなる前にパルス
列ｆのパルスがないからこの間でパルス列ｆと信号ｇと
の論理積出力はなく、従ってエンコーダの右方向へ動か
すことにより原点パルスｈは生じない。In the example of Fig. 4, there is no pulse of the pulse train f before the counter goes to the 0 state, so there is no AND output of the pulse train f and the signal g during this time, and therefore, by moving the encoder to the right, the origin pulse h is generated. do not have.
この場合次に操作者はエンコーダを左方向へ動かす。In this case, the operator then moves the encoder to the left.
カウンタはパルス列のｐ点から左側の最初のパルスｅの
立上り（今度はパルスの右エツジ）でＯ状態でなくなる
。The counter ceases to be in the O state at the rising edge of the first pulse e to the left of point p in the pulse train (this time at the right edge of the pulse).
第４図の例ではカウンタが０状態でなくなる迄にパルス
ｆがあるから原点パルスｈが生ずる。In the example shown in FIG. 4, since there is a pulse f until the counter is no longer in the 0 state, an origin pulse h is generated.
操作者は原点パルスｈの生じた位置を測定基準とする。The operator uses the position where the origin pulse h occurs as a measurement reference.
測定用パルスとしてパルス列ｆを用いれば、パルス列ｆ
の生ずる位置は原点パルスの生ずる位置から１デイジツ
ト毎にあるから前述のディジットエラーが生じない。If the pulse train f is used as the measurement pulse, the pulse train f
Since the positions where the digits are generated are one digit apart from the position where the origin pulse is generated, the above-mentioned digit error does not occur.
計測用パルスをパルス列ｅ又は分解能を上ゆるためＯｏ
と９０°の立上りと立下りにおけるパルス列を用い原点
パルス位置を測定基準としても誤差を防ぐことはできる
。Set the measurement pulse to pulse train e or Oo to increase the resolution.
Errors can also be prevented by using a pulse train at the rise and fall of 90° and using the origin pulse position as a measurement standard.
例数ならば原点パルス位置とそれらの計測用パルス列の
位置の関係は予じめ分かつているから、後にこれを補償
することができるからである。This is because, in the case of examples, the relationship between the origin pulse position and the positions of these measurement pulse trains is known in advance, and this can be compensated for later.
以上の如く構成した本発明によれば、エンコーダ装置の
カウンターをゼロリセットした後、原点パルスの出る位
置を測定基準とすれば、他に原点を定める装置がなくと
も正確に原点が決定される。According to the present invention configured as described above, after the counter of the encoder device is reset to zero, if the position where the origin pulse appears is used as the measurement standard, the origin can be accurately determined even without any other device for determining the origin.
このため工作機械等において加工中に原点へ戻す必要の
ある時はカウンタの０表示までもどしてこの原点パルス
の発生する位置を得れば正確に再現性をチェックするこ
とができる。Therefore, when it is necessary to return to the origin during machining in a machine tool or the like, reproducibility can be accurately checked by returning the counter to 0 and obtaining the position where this origin pulse is generated.
特に、本発明はディジタル秤や液面測定装置などのよう
に容易に原点を変える必要があり、かつ精度の検定が重
要な装置においては本装置による原点を使用すれば有効
である。In particular, the present invention is effective if the origin provided by this device is used in devices such as digital scales and liquid level measuring devices in which the origin needs to be easily changed and accuracy verification is important.
第１図は増分方式エンコーダの信号の説明図、第２図は
本発明の装置に使用する位相合成回路の説明図、第３図
は本発明の装置に使用する別の位相合成回路の説明図、
第４図は原点信号波形図である。
（主要部分の符号の説明つ
１・・・・・・増幅器、２，３，４・・・・・・抵抗、
５，６・・・・・・バッファアンプ、７，８・・・・・
・抵抗。Fig. 1 is an explanatory diagram of signals of an incremental encoder, Fig. 2 is an explanatory diagram of a phase synthesis circuit used in the device of the present invention, and Fig. 3 is an explanatory diagram of another phase synthesis circuit used in the device of the present invention. ,
FIG. 4 is an origin signal waveform diagram. (Explanation of symbols of main parts 1...Amplifier, 2, 3, 4...Resistance,
5, 6...Buffer amplifier, 7, 8...
·resistance.
Claims (1)
つの位相差の異る信号を出力し、該２信号を受けて可逆
計数し、前記２信号を位相合成し、該位相合成された信
号をパルス化し、該パルス列と前記計数のゼロ状態との
論理積をとり、該論理積により得られた単一パルスを測
定基準の原点信号とする原点信号検出方法。1. From incremental length and angle encoder measuring devices to 2.
output two signals with different phase differences, receive the two signals and perform reversible counting, phase synthesize the two signals, pulse the phase synthesized signal, and logic between the pulse train and the zero state of the count. An origin signal detection method in which a product is calculated and a single pulse obtained by the logical product is used as a measurement reference origin signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13773875A JPS5843684B2 (en) | 1975-11-18 | 1975-11-18 | Genten Shingo Kenshiyutsuhouhou |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13773875A JPS5843684B2 (en) | 1975-11-18 | 1975-11-18 | Genten Shingo Kenshiyutsuhouhou |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5262046A JPS5262046A (en) | 1977-05-23 |
| JPS5843684B2 true JPS5843684B2 (en) | 1983-09-28 |
Family
ID=15205665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13773875A Expired JPS5843684B2 (en) | 1975-11-18 | 1975-11-18 | Genten Shingo Kenshiyutsuhouhou |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5843684B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0238613Y2 (en) * | 1984-12-24 | 1990-10-17 |
-
1975
- 1975-11-18 JP JP13773875A patent/JPS5843684B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5262046A (en) | 1977-05-23 |
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