JPS5842247A - Case for semiconductor - Google Patents

Case for semiconductor

Info

Publication number
JPS5842247A
JPS5842247A JP56140763A JP14076381A JPS5842247A JP S5842247 A JPS5842247 A JP S5842247A JP 56140763 A JP56140763 A JP 56140763A JP 14076381 A JP14076381 A JP 14076381A JP S5842247 A JPS5842247 A JP S5842247A
Authority
JP
Japan
Prior art keywords
inner leads
layer
envelope
semiconductor
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56140763A
Other languages
Japanese (ja)
Inventor
Masaru Katagiri
優 片桐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56140763A priority Critical patent/JPS5842247A/en
Publication of JPS5842247A publication Critical patent/JPS5842247A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive the high integration of inner leads and the improvement of packing density by a method wherein a plurality of inner lead layers are provided in stepped shape and the surfaces and reverse sides of the inner leads are alternately arranged so that each step may not overlap. CONSTITUTION:In the main bodies 22, 23, of a two-layer case, the opening 32 of the main body 23 of an upper-layer case is formed bigger than that 33 of the main body 22 of a lower-layer case. A plurality of inner leads 34 are metaled on themain body 22 of the lower-layer case so that the inner leads 34 may surround around an element fixing section 31. In the same way, a plurality of inner leads 35 are metaled on the main body 23 of the upper-layer case so that the inner leads 35 may surround around the opening 32. Where, the upper- layer inner leads 35 and the lower-layer inner leads 34 are alternately arranged so that the surfaces of the lower-layer inner leads 34 and the reverse sides of the upper-layer inner leads 34 may not overlap.

Description

【発明の詳細な説明】 この発明は例えばＬＳＩ（大規模集積回路）チップを収
容するための半導体外囲器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor envelope for accommodating, for example, an LSI (large scale integrated circuit) chip.

従来、この種の半導体外囲器は例えば第１図の分解斜視
図に示すような方法で製造されている。すなわち、素子
固着部（ベッド）１１及びグランドツイン１２′ｔ−メ
タライズした絶縁基板１上に、上記素子固着部１１に対
応し九開口１３を形成すると共に複数のインナーリード
１４゜１４・・・をメタライズした外囲器本体２を接着
し、さらにこの外囲器本体２上に、上記素子固着部１１
に対応し九−口１５を形成すると共にグランドライン１
６をメタライズした上板３、及び上記素子固着部１１１
１Ｃ対応し九開口１７を形成したシェル載置台４を順次
接着し、さらにインナーリード１４，１４・・・にアウ
ターリード１Ｂ。Conventionally, this type of semiconductor envelope has been manufactured, for example, by a method as shown in the exploded perspective view of FIG. That is, on the element fixing part (bed) 11 and the ground twin 12't-metallized insulating substrate 1, nine openings 13 are formed corresponding to the element fixing part 11, and a plurality of inner leads 14, 14... The metallized envelope body 2 is adhered, and the element fixing portion 11 is further placed on the envelope body 2.
corresponding to the ground line 1 and forming a nine-mouth 15.
6 and the above-mentioned element fixing part 111.
Shell mounting bases 4 with nine openings 17 corresponding to 1C are adhered one after another, and outer leads 1B are attached to inner leads 14, 14, . . . .

１ａ・・・をメタライズして接続固定すると第２図に示
すような半導体外囲量が得られる。第３図は外１ｉｉｓ
本体２における素子固着部１１の周辺部を拡大して示す
平面図、第４図は上記半導体外ｓａ＋の素子固着部１ノ
にＬＳＩチツチン９を固着し、その内部端子とインナー
リード１４を一ンデインダワイヤ２０で接続した場合の
構造を示す一部断爾図である。When 1a... are metalized and connected and fixed, a semiconductor envelope as shown in FIG. 2 is obtained. Figure 3 is outside 1iis
FIG. 4 is an enlarged plan view showing the periphery of the element fixing part 11 in the main body 2, and FIG. 20 is a partially cutaway diagram showing the structure when connected at 20. FIG.

とζろで、最近のＬＳＩの多機能、高集積化に伴い、端
子（−ン）数が増加した場合、それを組み込む丸めの半
導体外囲器も当然同数の端子を必要とする。この丸め、
従来構造の半導体外囲器では、その外形寸法を大きくせ
ざるを得なかった。すなわち、従来構造では、ＬＳＩチ
ッチンｇの内部端子を外部に引き出すためのインナーリ
ード１４，１４・・・は素子固着部１１０周Ｈに単一層
で形成されてお夛、第３図に示すインナーリード１４，
１４・・・の幅Ｗ、及び間隔Ｗ、を狭くしない＠シ、端
子数が増えれば必然的に外囲器寸法も大きくなってしま
う。一方、インナーリード１４，１４・・・の幅Ｗ、及
び間隔Ｗ、を狭くすることはがンデイングの作業性及び
信頼性上好ましくなく、従来構造で社どうしても外形寸
法の大きな本のとなってしまう。従って、このような半
導体外囲器に組み込まれ九ＬＳＩをが−ド等に実値する
場合、従来構造では実装密度が上がらないという欠点を
有していた。If the number of terminals increases as LSIs become more multifunctional and highly integrated, the rounded semiconductor envelope that incorporates them will naturally require the same number of terminals. This rounding,
In a semiconductor envelope having a conventional structure, the external dimensions have to be increased. That is, in the conventional structure, the inner leads 14, 14, . 14,
If the width W and the interval W of 14 are not narrowed, as the number of terminals increases, the size of the envelope will inevitably increase. On the other hand, narrowing the width W and the interval W of the inner leads 14, 14, etc. is not preferable in terms of the workability and reliability of soldering, and the conventional structure inevitably results in a book with large external dimensions. . Therefore, when a nine LSI integrated into such a semiconductor package is used as a board, the conventional structure has the disadvantage that the packaging density cannot be increased.

この発明は上記実情に僑みてなされたもので、ドの高集
積化を図ることが可能で、外形寸法を大幅に縮小するこ
とができ、実装密度を向上させることのできる半導体外
囲器を提供することＫある。This invention was made in view of the above-mentioned circumstances, and provides a semiconductor envelope that can achieve high integration, significantly reduce external dimensions, and improve packaging density. There's K things to do.

以下、図面を参照してこの発明の一実施例を説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第５図線従来構造と同様に素子固着部３１及びグランド
ラインがメタライズされた絶縁基板２１上に２層の外囲
器本体２２．２３が接着され、さらに外囲器本体２３上
に上板２４が接着された状態の半導体外囲器の一部を示
す斜視図である。２層の外囲器本体２１．２３のうち上
層の外！！ｉＳ本体２Ｓの開口５ｚｌｄ下層の外囲器本
体２２の橢口ＳＳより大きく形成されている。そして、
下層の外囲器本体２２には素子固着５ｅｘ（ｖａ口ＳＳ
）の周囲を取り囲むように複数のインナーリード３４，
３４・・・がメタライズされ、同様に上層の外囲器本体
２３にも開口ｊ２の周囲を城に囲むように複数のインナ
ーリードｓｓ　、ｓｓ・・・がメタライズされている。Figure 5: Similar to the conventional structure, two layers of the envelope body 22 and 23 are bonded onto the insulating substrate 21 on which the element fixing portion 31 and the ground line are metallized, and the upper plate 24 is further bonded onto the envelope body 23. FIG. 2 is a perspective view showing a part of the semiconductor envelope in a state where the semiconductor envelope is bonded to the semiconductor envelope. The outside of the upper layer of the two-layer envelope body 21.23! ! The opening 5zld of the iS main body 2S is formed larger than the opening SS of the lower envelope main body 22. and,
The lower envelope body 22 has an element fixed 5ex (VA port SS).
) a plurality of inner leads 34,
34... are metalized, and similarly, a plurality of inner leads ss, ss... are metalized on the upper envelope main body 23 so as to surround the opening j2.

ここで、上層のインナーリード３５，３５・・・は、そ
れぞれ下層のインナーリード３４，３イ・・・と幅Ｗ１
部及び間隔Ｗｔ部が上下で重なることのないように下層
のインナーリード３４，３４・・・と交互に配置されて
いる。なお、ｓｅ、３６・・・はインナーリード３４，
３４・・・、３５．３５・・・に接続するように溶接さ
れたアウターリードである。第６図は素子固着部３１に
ＬＳＩチップ２５を固着し、その内部端子と、上層のイ
ンナーリードｊ５及び下層のインナーリード３４とをそ
れぞれがンデイングワイヤ２６．２７で接続し良状態を
示す断面図である。Here, the inner leads 35, 35... of the upper layer have a width W1 of the inner leads 34, 3i... of the lower layer, respectively.
The inner leads 34, 34, . . . are arranged alternately so that the upper and lower inner leads 34, 34, . . . In addition, se, 36... are inner leads 34,
These are outer leads welded to connect to 34..., 35, 35.... FIG. 6 is a cross section showing a good state in which the LSI chip 25 is fixed to the element fixing part 31, and its internal terminals are connected to the upper layer inner lead j5 and the lower layer inner lead 34 with connecting wires 26 and 27, respectively. It is a diagram.

すなわち、この半導体外囲器においては、インナーリー
ドが、従来単一層で形成されていたのに対し、２層構造
で、それらが階段状に形成され、かつ上下で菫なり合う
ととのないように交互に配置されているため、従来必要
としていたインナーリードの間隔部の領域を有効に利用
することができる。従って、多ビン構造の半導体外囲器
の場合のインナーリードの高集積化會図ることが可能と
なシ、外形寸法を大幅に縮小すみことができ、実装密度
を向上させることができる。In other words, in this semiconductor envelope, whereas the inner leads were conventionally formed in a single layer, they have a two-layer structure in which they are formed in a step-like manner, and they overlap at the top and bottom to avoid the possibility of Since the inner leads are arranged alternately, the space between the inner leads, which was conventionally required, can be effectively utilized. Therefore, in the case of a multi-bin structure semiconductor envelope, it is possible to achieve high integration of inner leads, the external dimensions can be significantly reduced, and the packaging density can be improved.

第７図は上記半導体外囲器をマイボンシステムに適用し
たものである。すなわち、マイコン’／ｆｉテムにおい
ては、ＣＰ　Ｕ　（ＣｅｎｔｒａｌＰｒｏｔｅｓｔｉｎ
ｇ　　Ｕｎ口）４１０半導体外囲器４２上にソケット４
Ｓを接続し、このソケット４３にメモリ４４を組み込む
方法が利用されている、が、例えばｃｐυ４１からメモ
リ４４への接続端子を上層のインナーリード、ＣＰＵ４
１から外部への引出し端子を下層のインナーリードとい
うように上下に分けて使用することで、従来よシ容易に
半導体外囲器４２の設計を行うことができ、かつ外形寸
法の縮小を図り実装密度を向上させることができる。FIG. 7 shows the above semiconductor envelope applied to the Mibon system. That is, in the microcontroller/fitem, CPU (CentralProtestin
g Un port) 410 Socket 4 on semiconductor envelope 42
For example, the connection terminal from cpυ41 to memory 44 is connected to the inner lead of the upper layer, and the memory 44 is installed in this socket 43.
By using the lead-out terminals from 1 to the outside as upper and lower inner leads on the lower layer, the semiconductor envelope 42 can be designed more easily than in the past, and the external dimensions can be reduced and mounted. Density can be improved.

尚、上記実施例においては、インナーリーＰ３４．１４
・・・、ａｓ、ｓｓ・・・を２層構造として説明し九が
、これに限定するものではなく、３層以上０構造として
さらに集積度を向上させることもできることは勿論であ
る。In the above embodiment, innerly P34.14
. . , as, ss, . . . are described as having a two-layer structure, but the present invention is not limited to this, and it goes without saying that the degree of integration can be further improved by forming a structure with three or more layers.

以上のようにこの発明によれば、複数層のインナーリー
ドを階段状に設け、かつ各段のインナーリードが重なシ
合うことのないように上下交互に配置する構成としたの
で、インナーリードの高集積化を図ることが可能で、外
形寸法を大幅に縮小することができ、実装密度を向上さ
せることができる。As described above, according to the present invention, a plurality of layers of inner leads are provided in a step-like manner, and the inner leads of each stage are arranged vertically and alternately so that they do not overlap. High integration can be achieved, external dimensions can be significantly reduced, and packaging density can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体外囲器の構造を示す分解斜視図、
第２図は上記外囲器の全体斜視図、第３図は上記外囲器
の一部を示す平面図、第４図は上記外囲器にＬＳＩチッ
プを組み込んだ状態を示す一部断面図、第５図はこの発
明の一実施例に係る半導体外囲器の一部を示す斜視図、
第６図は上記外囲器にＬＳＩチップを組み込んだ状態を
示す一部断面図、第７図は上記外囲器にＣＰＵ及びメモ
リを組み込んだ状態を示す斜視図である。 ２１・・・絶縁基板、２２．２３・・・外囲器本体、２
５・・・Ｌ８Ｉチッグ、３１・・・素子固着部、３４゜
３５・・・インナーリード。 出願人代理人　弁理士　鈴　江　武　彦ＪＲ１図 ７ 第３図　　　　第４図 ４ 第５図FIG. 1 is an exploded perspective view showing the structure of a conventional semiconductor envelope;
FIG. 2 is an overall perspective view of the envelope, FIG. 3 is a plan view of a portion of the envelope, and FIG. 4 is a partial sectional view showing the LSI chip assembled in the envelope. , FIG. 5 is a perspective view showing a part of a semiconductor envelope according to an embodiment of the present invention,
FIG. 6 is a partial cross-sectional view showing a state in which an LSI chip is assembled into the above-mentioned envelope, and FIG. 7 is a perspective view showing a state in which a CPU and a memory are built into the above-mentioned envelope. 21... Insulating substrate, 22.23... Envelope body, 2
5... L8I tip, 31... Element fixing part, 34° 35... Inner lead. Applicant's agent Patent attorney Takehiko Suzue JR1 Figure 7 Figure 3 Figure 4 Figure 4 Figure 5

Claims (2)

【特許請求の範囲】[Claims] （１）半導体素子が収容される半導体外囲器において、
前記半導体素子が固着される導電性の素子固着部と、こ
の素子固着部の周囲をＩＲに囲むように検数層設けられ
九複数のインナーリードとを具備したことを特徴とする
半導体外囲器。(1) In a semiconductor envelope in which a semiconductor element is housed,
A semiconductor envelope comprising: a conductive element fixing part to which the semiconductor element is fixed; and a plurality of nine inner leads provided with a counting layer so as to surround the element fixing part with an IR. . （２）　　前記複数層のインナーリードが階段状に形成
され、かつ各段のインナーリードはその上下段のインナ
ーリードと重なり合うことのないように交互に配置され
た特許請求の範囲第１項記載の半導体外囲器。(2) The plurality of layers of inner leads are formed in a step-like manner, and the inner leads of each stage are alternately arranged so as not to overlap with the inner leads of the upper and lower stages thereof. Semiconductor envelope.
JP56140763A 1981-09-07 1981-09-07 Case for semiconductor Pending JPS5842247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56140763A JPS5842247A (en) 1981-09-07 1981-09-07 Case for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56140763A JPS5842247A (en) 1981-09-07 1981-09-07 Case for semiconductor

Publications (1)

Publication Number Publication Date
JPS5842247A true JPS5842247A (en) 1983-03-11

Family

ID=15276170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56140763A Pending JPS5842247A (en) 1981-09-07 1981-09-07 Case for semiconductor

Country Status (1)

Country Link
JP (1) JPS5842247A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5016085A (en) * 1988-03-04 1991-05-14 Hughes Aircraft Company Hermetic package for integrated circuit chips
US5117275A (en) * 1990-10-24 1992-05-26 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5229328A (en) * 1990-10-24 1993-07-20 International Business Machines Corporation Method for bonding dielectric mounted conductors to semiconductor chip contact pads
US5233221A (en) * 1990-10-24 1993-08-03 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5016085A (en) * 1988-03-04 1991-05-14 Hughes Aircraft Company Hermetic package for integrated circuit chips
US5117275A (en) * 1990-10-24 1992-05-26 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5229328A (en) * 1990-10-24 1993-07-20 International Business Machines Corporation Method for bonding dielectric mounted conductors to semiconductor chip contact pads
US5233221A (en) * 1990-10-24 1993-08-03 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology

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