JPH0199248A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0199248A
JPH0199248A JP62258632A JP25863287A JPH0199248A JP H0199248 A JPH0199248 A JP H0199248A JP 62258632 A JP62258632 A JP 62258632A JP 25863287 A JP25863287 A JP 25863287A JP H0199248 A JPH0199248 A JP H0199248A
Authority
JP
Japan
Prior art keywords
semiconductor element
spacer
semiconductor
semiconductor device
semiconductor elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62258632A
Other languages
Japanese (ja)
Inventor
Ryuichi Kosugi
小杉　龍一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62258632A priority Critical patent/JPH0199248A/en
Publication of JPH0199248A publication Critical patent/JPH0199248A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To enhance maximum memory capacity and to enhance a mounting density by superposing a semiconductor element and a spacer made of an insulation material in a laminar state in a package. CONSTITUTION:A semiconductor element 1 and a space 2 made of an insulation material are superposed in a laminar state in a package. Resin 6 seals the element 1, the spacer 2, the inner terminal of an external lead 4 and fine metal wirings 5. Thus, maximum memory capacity is enhanced, and its mounting density is raised.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置に関し、そのパッケージ内部の
半導体素子と絶縁材料よりなるスペーサーを層状に重ね
た構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and relates to a structure in which a semiconductor element inside a package and a spacer made of an insulating material are stacked in layers.

〔従来の技術〕[Conventional technology]

第２図は従来のダイナミック・ランダム・アクセス・メ
モリー（以下Ｄ−ＲＡＭと称する）の側断面図である。FIG. 2 is a side sectional view of a conventional dynamic random access memory (hereinafter referred to as D-RAM).

図において（１）は内部に回路が構成された半導体素子
、（４）は外部導出導体、（６）は半導体素子（１）と
外部導出導体（４）を電気的に接続する金属細線、（６
）は前記（１）〜（５）の部品を包囲する樹脂（７）は
半導体素子（１）をのせるグイバットである。In the figure, (1) is a semiconductor element with a circuit configured inside, (4) is an external lead-out conductor, (6) is a thin metal wire that electrically connects the semiconductor element (1) and the external lead-out conductor (4), ( 6
), the resin (7) surrounding the parts (1) to (5) above is a guibat on which the semiconductor element (1) is placed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の半導体装置は以上のように半導体素子（１）をグ
イバット（７）の−主面、また両面にしか取り付けるこ
とができないため、例えば記憶容量または機能が限られ
、実装密度が低いという問題があった。As described above, in conventional semiconductor devices, the semiconductor element (1) can only be attached to the -main surface or both sides of the Guibat (7), which leads to problems such as limited storage capacity or functionality and low packaging density. there were.

この発明は、ヒ記のような問題点を解消するためになさ
れたもので、半導体装置導体の最大記憶容態または機能
などを高めた半導体装置を得ることを目的としている。This invention has been made to solve the problems mentioned above, and aims to provide a semiconductor device in which the maximum storage capacity or function of a semiconductor device conductor is improved.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、複数の半導体素子に設け
られ絶縁材料よりなるスペーサーと、前記半導体素子に
設けられた複数の電極を相互に接続する接続部材とを設
けたものである。A semiconductor device according to the present invention is provided with a spacer made of an insulating material and provided on a plurality of semiconductor elements, and a connecting member that interconnects a plurality of electrodes provided on the semiconductor elements.

〔作用〕[Effect]

この発明における半導体装置は、絶縁材料よりなるスペ
ーサーにより複数の半導体素子を接続することができる
。In the semiconductor device according to the present invention, a plurality of semiconductor elements can be connected by a spacer made of an insulating material.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第１図において（１）は半導体素子、（２）は絶縁材料
で作られたスペーサー、（３）は半導体素子（１）を接
続する接続部材、（４）は外部導出導体、（５）は半導
体素子（１）と外部導出導体（４）を電気的に接続する
金属細線、（６）は半導体系子（１）、スペーサー（２
）、外部導出導体（４）の内部端子、および金属細線（
５）を封止する樹脂である。また素子には複数の電油が
あり、これらは接続部材で相互に電気的に接続されてい
る。In Figure 1, (1) is a semiconductor element, (2) is a spacer made of an insulating material, (3) is a connecting member that connects the semiconductor element (1), (4) is an external conductor, and (5) is a A thin metal wire electrically connects the semiconductor element (1) and the external conductor (4), (6) is the semiconductor element (1) and the spacer (2).
), the internal terminal of the external conductor (4), and the thin metal wire (
5) is a resin for sealing. Further, the element includes a plurality of electro-oils, which are electrically connected to each other by a connecting member.

なお、上記実施例では、半導体素子が３１ｉ１に重なっ
ており、また＠１畠のような金属細線の配線になってい
るまたスペーサを図のような形状になっているが、この
発明が適用される半導体装置の内部構造は揮々の配置、
形状を取り得ろもので、上記実施例に限られるものでは
ない。また、第１図はデュアル・インラインパッケージ
型のＤ−ＲＡＭについてであるが、これに限られるもの
ではない。In the above embodiment, the semiconductor element overlaps 31i1, and the wiring is made of thin metal wires like @1Hata, and the spacer has the shape as shown in the figure, but this invention is not applied. The internal structure of a semiconductor device is
It can take any shape, and is not limited to the above embodiment. Further, although FIG. 1 shows a dual inline package type D-RAM, the present invention is not limited to this.

〔発明の効果〕〔Effect of the invention〕

以ヒのようにこの発明によれば、パッケージ内部で半導
体素子と絶縁材料よりなるスペーサーを層状に重ねるよ
うに構成したので、最大記憶容置または機能などが高ま
り、実装密度が高まるという効果かある。As described above, according to this invention, the semiconductor element and the spacer made of an insulating material are layered inside the package, which has the effect of increasing the maximum storage capacity or function and increasing the packaging density. .

４、　図面の［１１）単な説明 第１図はこの発明の一実施例によるＤ−ＲＡＭ半導体装
置を示す側断面図、第２図は従来のＤ−ＲＡＭ半導体装
置を示す側断面図である。4. [11] Simple explanation of the drawings FIG. 1 is a side sectional view showing a D-RAM semiconductor device according to an embodiment of the present invention, and FIG. 2 is a side sectional view showing a conventional D-RAM semiconductor device. .

図中（１）半導体素子、（２）はスペーサー、（３）は
接続部材、（４）は外部導出導体、（５）は全島細線、
（６）は樹脂である。In the figure, (1) is a semiconductor element, (2) is a spacer, (3) is a connecting member, (4) is an external conductor, (5) is a whole island thin wire,
(6) is a resin.

なお、図中同一符号は同−又は相当部分を示す。Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 　複数の半導体素子と、この複数の半導体素子間に設け
られ絶縁材料よりなるスペーサーと、前記半導体素子に
設けられた複数の電極を相互に接続する接続部材、前記
半導体素子と金属細線により、その内部端子が接続され
る複数の外部導出導体と、前記半導体素子、スペーサー
、接続部材、金属細線および外部導出導体の内部端子を
包囲する樹脂とを備えた半導体装置。A plurality of semiconductor elements, a spacer made of an insulating material provided between the plurality of semiconductor elements, a connecting member for interconnecting a plurality of electrodes provided on the semiconductor elements, and a plurality of semiconductor elements and thin metal wires, A semiconductor device comprising a plurality of external lead-out conductors to which terminals are connected, and a resin surrounding the semiconductor element, a spacer, a connecting member, a thin metal wire, and an internal terminal of the external lead-out conductor.
JP62258632A 1987-10-13 1987-10-13 Semiconductor device Pending JPH0199248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62258632A JPH0199248A (en) 1987-10-13 1987-10-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62258632A JPH0199248A (en) 1987-10-13 1987-10-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0199248A true JPH0199248A (en) 1989-04-18

Family

ID=17322968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62258632A Pending JPH0199248A (en) 1987-10-13 1987-10-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0199248A (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5295045A (en) * 1990-11-14 1994-03-15 Hitachi, Ltd. Plastic-molded-type semiconductor device and producing method therefor
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6759737B2 (en) 2000-03-25 2004-07-06 Amkor Technology, Inc. Semiconductor package including stacked chips with aligned input/output pads
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
USRE40112E1 (en) * 1999-05-20 2008-02-26 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5295045A (en) * 1990-11-14 1994-03-15 Hitachi, Ltd. Plastic-molded-type semiconductor device and producing method therefor
USRE40112E1 (en) * 1999-05-20 2008-02-26 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6762078B2 (en) 1999-05-20 2004-07-13 Amkor Technology, Inc. Semiconductor package having semiconductor chip within central aperture of substrate
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6803254B2 (en) 1999-12-20 2004-10-12 Amkor Technology, Inc. Wire bonding method for a semiconductor package
US6759737B2 (en) 2000-03-25 2004-07-06 Amkor Technology, Inc. Semiconductor package including stacked chips with aligned input/output pads
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6650019B2 (en) 2000-07-20 2003-11-18 Amkor Technology, Inc. Method of making a semiconductor package including stacked semiconductor dies
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US6919631B1 (en) 2001-12-07 2005-07-19 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor

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