JPS5837989B2 - field effect semiconductor device - Google Patents
field effect semiconductor deviceInfo
- Publication number
- JPS5837989B2 JPS5837989B2 JP55018294A JP1829480A JPS5837989B2 JP S5837989 B2 JPS5837989 B2 JP S5837989B2 JP 55018294 A JP55018294 A JP 55018294A JP 1829480 A JP1829480 A JP 1829480A JP S5837989 B2 JPS5837989 B2 JP S5837989B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- field effect
- diffusion layer
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
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- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は金属一絶縁膜一半導体構造を有する絶縁ゲート
型電界効果半導体装置、いわゆるＭＩＳ型電界効果半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect semiconductor device having a metal-insulating film-semiconductor structure, a so-called MIS field effect semiconductor device.
一般にＭＩＳ型電界効果半導体装置に於ける素子間絶縁
は、一方の素子の一拡散層と隣接する素子の一拡散層と
を各々ソース、ドレインとし、両拡散層間に存在するフ
ィールド絶縁膜上の配線導体をゲートする寄生ＭＩＳ型
電界効果素子の閾電圧ＶＴＦを同半導体装置の使用最高
電圧以上の値になるようにする事により保たれている。In general, inter-element insulation in MIS type field effect semiconductor devices uses one diffusion layer of one element and one diffusion layer of an adjacent element as the source and drain, respectively, and interconnects on the field insulating film between the two diffusion layers. This is maintained by setting the threshold voltage VTF of the parasitic MIS type field effect element that gates the conductor to a value higher than the maximum voltage used in the semiconductor device.
特にデプレツション型の半導体装置では半導体基板電位
をソース電位に対し、特定電位に設定することにより、
すなわち基板バイアスを印加することにより、エンハン
スメン′ト型として使用される。In particular, in depression type semiconductor devices, by setting the semiconductor substrate potential to a specific potential with respect to the source potential,
That is, by applying a substrate bias, it is used as an enhancement type.
従ってこの様な場合、寄生ＭＩＳ型電界効果素子の閾電
圧も基板電位を考慮に入れて設計される事になる。Therefore, in such a case, the threshold voltage of the parasitic MIS type field effect element is also designed taking the substrate potential into consideration.
しかし、素子間の絶縁に於いては、上記基板電位の効果
でＶＴＦが十分高く保持されているが、装置周辺から基
板裏面への絶縁については、基板電位の効果がなくなり
、Ｖ’ｌ’Ｆ は小さくなり、その結果、素子周辺部か
ら、基板裏面への漏洩電流が問題となる。However, in insulation between elements, VTF is maintained sufficiently high due to the effect of the substrate potential, but when it comes to insulation from the periphery of the device to the back surface of the substrate, the effect of the substrate potential disappears, and V'l'F becomes small, and as a result, leakage current from the periphery of the element to the back surface of the substrate becomes a problem.
すなわち、ＮチャンネルＭＩＳ型電界効果素子による高
速回路においては拡散層（ソース、ドレイン）一基板間
の容量を小とするために、Ｐ型基板に負電圧を印力日し
て使用する場合が多い。That is, in high-speed circuits using N-channel MIS type field effect elements, in order to reduce the capacitance between the diffusion layer (source, drain) and the substrate, a negative voltage is often applied to the P-type substrate. .
これによりデプレツション型の素子はエンハンスメント
型となり、使用するのであるが、この場合素子間のＶＴ
Ｆ もたとえばＩＯＶから３０Ｖに上昇するから、素子
間の寄生効果は問題なくなる。As a result, the depletion type element becomes an enhancement type and is used, but in this case, the VT between the elements
Since F2 also increases from IOV to 30V, for example, parasitic effects between elements are no longer a problem.
しかしながら素子周辺部から基板の側面を通って裏面に
いたる寄生素子のＶＴＦ はこの基板バイアスによる効
果は得られない。However, the effect of this substrate bias cannot be obtained on the VTF of the parasitic element extending from the periphery of the device through the side surface of the substrate to the back surface.
さらにこの寄生素子は、周辺部の不純物領域をドレイン
とし、これに接続する配線層およびこれより絶縁膜上に
漏洩した＋電荷をゲート電極とし、基板および裏面の金
属層をソースとするから、この等価回路はゲート電極と
ドレインとを接続し、基板とソースとが接続されること
となる。Furthermore, this parasitic element uses the impurity region in the periphery as a drain, the wiring layer connected to this and the + charge leaked from this onto the insulating film as a gate electrode, and the substrate and the metal layer on the back side as a source. The equivalent circuit connects the gate electrode and the drain, and the substrate and the source.
したがって、たとえばこの装置の使用電圧が＋１２Ｖで
基板電圧が−５■の場合、この側面の寄生ＭＩＳにおい
ては、基板に対して＋１７■のゲート電圧が印加された
こととなり、側面を流れる漏洩電流の問題は犬となる。Therefore, for example, if the working voltage of this device is +12V and the substrate voltage is -5■, in the parasitic MIS on this side, a gate voltage of +17■ is applied to the substrate, and the leakage current flowing through the side is The problem is the dog.
従来、この素子周辺部から基板裏面への漏洩電流を防止
する決定的な方法がなく、不十分ながら次の様な対策が
講じられてきた。Conventionally, there has been no definitive method for preventing this leakage current from the periphery of the element to the back surface of the substrate, and the following countermeasures have been taken, although they are insufficient.
すなわち、素子周辺部にガード・リング或いはチャンネ
ル・ストッパーとして基板と同導電型の不純物を拡散形
成し、基板電位効果がなくてもＶＴＦが十分高くなる様
に工夫されている。That is, an impurity having the same conductivity type as the substrate is diffused as a guard ring or a channel stopper around the device, so that the VTF can be made sufficiently high even without the substrate potential effect.
しかし、この基板と同導電型の不純物拡散は従来の製造
工程に追加される工程であり、製造歩留の低下の原因と
なる。However, this diffusion of impurities of the same conductivity type as the substrate is an additional process to the conventional manufacturing process, and causes a decrease in manufacturing yield.
又、ＶＴＦを高くする為に高濃度拡散が行われた場合に
は、製造上の欠陥とくに拡散マスクに生じたピンホール
から、素子部に点状に異常拡散される事があり、そこが
耐圧不良を起こし、これも製造歩留りの低下の原因とな
る。Additionally, when high-concentration diffusion is performed to increase the VTF, manufacturing defects, especially pinholes in the diffusion mask, may cause abnormal dots to be diffused into the element area, which may cause the breakdown voltage to decrease. This causes defects, which also causes a decrease in manufacturing yield.
本発明の目的は製造工程の追加なく、素子周辺部から基
板裏面へのチャンネル性漏洩電流を最小に押えることの
できるＭＩＳ型電界効果半導体装置を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an MIS type field effect semiconductor device that can minimize channel leakage current from the periphery of the device to the back surface of the substrate without adding any additional manufacturing steps.
本発明によれば、Ｐ型半導体基板の表面にＮチャンネル
絶縁ゲート型電界効果トランジスタを設け、該半導体基
板に基板バイアスを印加した半導体装置において、前記
トランジスタを包囲するようにＮ型の領域を前記表面に
設け、前記トランジスタのソースもしくはドレインから
前記半導体基板の裏面への漏洩電流を防止するように前
記領域の電位を制御することを特徴とする電界効果半導
体装置が得られる。According to the present invention, in a semiconductor device in which an N-channel insulated gate field effect transistor is provided on the surface of a P-type semiconductor substrate and a substrate bias is applied to the semiconductor substrate, an N-type region is formed so as to surround the transistor. There is obtained a field effect semiconductor device characterized in that it is provided on the front surface and the potential of the region is controlled so as to prevent leakage current from the source or drain of the transistor to the back surface of the semiconductor substrate.
すなわち、本発明によれば、素子周辺にソース、ドレイ
ンと同導電型の不純物拡散層を配置し、この拡散層を通
常Ｏ■に設定される基準電位に固定する。That is, according to the present invention, an impurity diffusion layer of the same conductivity type as the source and drain is arranged around the element, and this diffusion layer is fixed at a reference potential which is normally set to O2.
このようにＯ■に設定すれば、本発明の拡散層と周辺部
の素子の拡散層との間のＶＴＦは素子間の■ＴＦと同じ
ように例えば＋３０Ｖの高い値となる。If the voltage is set to O■ in this way, the VTF between the diffusion layer of the present invention and the diffusion layer of the peripheral element becomes a high value of, for example, +30V, like the TF between the elements.
又、このようにＯ■にすることにより、本発明の拡散層
に接続する電極から十電荷がにじみでても、裏面と本発
明の拡散層間の寄生ＭＩＳには実効的には基板電位の絶
対値分しか印加されないこととなるから、この寄生ＭＩ
ＳのＶＴＦはたかだかＩＯＶ程度あれば十分であること
となる。In addition, by setting O■ in this way, even if ten charges ooze out from the electrode connected to the diffusion layer of the present invention, the parasitic MIS between the back surface and the diffusion layer of the present invention is effectively affected by the absolute value of the substrate potential. This parasitic MI
It is sufficient that the VTF of S is at most about IOV.
この構造によれば、素子部最外穀から、基板裏面へのチ
ャンネル性漏洩電流は本発明の基準電位に固定された拡
散層により阻止される事になる。According to this structure, channel leakage current from the outermost portion of the element portion to the back surface of the substrate is blocked by the diffusion layer fixed to the reference potential of the present invention.
すなわち、本発明の拡散層と素子部最外穀の拡散層とで
形成される寄生ＭＩＳ型トランジスタは素子内部同様、
基板電位の効果を受け、すなわち基板バイアスの効果を
受け、十分高い閾電圧ＶＴＦが得られ、素子部最外穀か
ら、基板裏面への寄生ＭＩＳ型トランジスタ動作による
漏洩電流は防止される。That is, the parasitic MIS type transistor formed by the diffusion layer of the present invention and the outermost diffusion layer of the element part has the same characteristics as the inside of the element.
Under the effect of the substrate potential, that is, the effect of the substrate bias, a sufficiently high threshold voltage VTF is obtained, and leakage current due to parasitic MIS type transistor operation from the outermost part of the element portion to the back surface of the substrate is prevented.
又、本発明の拡散層と基板裏面とで構成される寄生ＭＩ
Ｓ型トランジスタは電極電位によるＶＴＦ増加の効果が
得られないが低い閾電圧でもエンハンスメント型となっ
ておれば、常に電気的絶縁が保持される事になる。Moreover, the parasitic MI composed of the diffusion layer of the present invention and the back surface of the substrate
Although the S-type transistor does not have the effect of increasing VTF due to the electrode potential, if it is an enhancement type transistor even at a low threshold voltage, electrical insulation is always maintained.
従って本発明の拡散層は素子部最外穀から基板電極又は
基板裏面への寄生ＭＩＳ型トランジスタ動作による漏洩
電流を阻止できるものである。Therefore, the diffusion layer of the present invention can prevent leakage current due to parasitic MIS type transistor operation from the outermost portion of the element portion to the substrate electrode or the back surface of the substrate.
次にこの発明による電界効果半導体装置の一実施例を図
面を参照して説明しよう。Next, an embodiment of a field effect semiconductor device according to the present invention will be described with reference to the drawings.
第１図は本発明のチャンネル・ストッパーを使用した半
導体装置の断面図でａ−ａ ’間が一半導体装置であり
、ｂ−ｂ’間が同装置の回路素子部６を示している。FIG. 1 is a cross-sectional view of a semiconductor device using the channel stopper of the present invention, where the line aa' shows one semiconductor device, and the line b-b' shows a circuit element section 6 of the same device.
本発明の半導体装置は第２図に於いて斜線部の回路素子
部６を囲む様にソース、ドレインと同導電型の不純物拡
散層２′を設ける構造でその製法は第１図の如く、従来
の製法に従ってＰ型シリコン基板１表面にＮ型のソース
、ドレイン２、ゲート３、金属配線４を形成していく過
程に於いて、ソース、ドレイン形成と同時にａｂ，ａ’
−ｂ’間に回路素子部６を囲む様にＮ＋拡散層２′を形
成し、この拡散層電位を基準電位例えばｏｖに設定して
なる半導体装置である。The semiconductor device of the present invention has a structure in which an impurity diffusion layer 2' of the same conductivity type as the source and drain is provided so as to surround the circuit element section 6 shown in the shaded area in FIG. 2, and its manufacturing method is as shown in FIG. In the process of forming an N-type source, drain 2, gate 3, and metal wiring 4 on the surface of a P-type silicon substrate 1 according to the manufacturing method described above, ab, a'
This is a semiconductor device in which an N+ diffusion layer 2' is formed between -b' so as to surround the circuit element section 6, and the potential of this diffusion layer is set to a reference potential, for example, ov.
そして図では基板１の電位を特定電位に設定することに
よりエンハンスメント型となっている。In the figure, the potential of the substrate 1 is set to a specific potential to provide an enhancement type.
斯る構成によれば、回路素子部最外穀拡散層２と本発明
のチャンネル・ストッパー拡散層２′とで構威される寄
生ＭＩＳ型電界効果トランジスタは回路素子部と同じ閾
電圧が得られ、回路素子部から、その周辺への漏洩電流
は阻止される事になる。According to such a configuration, the parasitic MIS field effect transistor composed of the outermost diffusion layer 2 of the circuit element part and the channel stopper diffusion layer 2' of the present invention can obtain the same threshold voltage as the circuit element part. , leakage current from the circuit element section to its surroundings is prevented.
更に本発明のチャンネル・ストッパーは上記チャンネル
・ストッパーとして使用されるだけでなく、基準電位配
線の一部として利用できる。Furthermore, the channel stopper of the present invention can be used not only as the channel stopper described above, but also as a part of the reference potential wiring.
従って本発明によれば漏洩電流の少い、高性能ＭＩＳ型
半導体装置を得る事ができるのである。Therefore, according to the present invention, a high performance MIS type semiconductor device with low leakage current can be obtained.
また以上では「拡散層」なる表現を用いたが、この層は
不純物拡散によって形成したもののほか、イオン打込な
どの他の方法で形成したものであってもよい。Although the expression "diffusion layer" is used above, this layer may be formed by impurity diffusion or by other methods such as ion implantation.
【図面の簡単な説明】
第１図は本発明を用いた半導体装置の断面図であり、第
２図はその平面図である。
図において、１はＰ型シリコン基板、２はＮ型ソース、
ドレイン、２′は素子部周辺に設けた拡散層、３はゲー
ト、４は金属配線、
２′の電極、６は素子部である。
５は拡散層BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a semiconductor device using the present invention, and FIG. 2 is a plan view thereof. In the figure, 1 is a P-type silicon substrate, 2 is an N-type source,
A drain, 2' is a diffusion layer provided around the element part, 3 is a gate, 4 is a metal wiring, 2' is an electrode, and 6 is an element part. 5 is the diffusion layer
Claims (1)
電型チャンネルの絶縁ゲート型電界効果トランジスタを
設け、該半導体基板に基板バイアスを印加した半導体装
置において、前記第１および第２のトランジスタを含む
前記一導電型半導体基板の表面部分を包囲しかつ前記第
１および第２のトランジスタ間には延在せずかつ基準電
位配線の一部として利用される逆導電型の領域を前記表
面に設け、前記トランジスタのソースもしくはドレイン
から前記半導体基板の裏面への漏洩電流を防止したこと
を特徴とする電界効果半導体装置。1. In a semiconductor device in which first and second insulated gate field effect transistors with opposite conductivity type channels are provided on the surface of a semiconductor substrate of one conductivity type, and a substrate bias is applied to the semiconductor substrate, the first and second transistors are a region of an opposite conductivity type that surrounds a surface portion of the one conductivity type semiconductor substrate including a conductivity type semiconductor substrate, does not extend between the first and second transistors, and is used as a part of a reference potential wiring; A field effect semiconductor device, characterized in that a leakage current from the source or drain of the transistor to the back surface of the semiconductor substrate is prevented.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55018294A JPS5837989B2 (en) | 1980-02-16 | 1980-02-16 | field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55018294A JPS5837989B2 (en) | 1980-02-16 | 1980-02-16 | field effect semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13909774A Division JPS5164881A (en) | 1974-12-03 | 1974-12-03 | DENKAIKOKAHANDOTAISOCHI |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55127052A JPS55127052A (en) | 1980-10-01 |
| JPS5837989B2 true JPS5837989B2 (en) | 1983-08-19 |
Family
ID=11967581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55018294A Expired JPS5837989B2 (en) | 1980-02-16 | 1980-02-16 | field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5837989B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6023290U (en) * | 1983-07-26 | 1985-02-18 | 株式会社荏原製作所 | drain pump |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2537161B2 (en) * | 1983-11-17 | 1996-09-25 | 株式会社東芝 | MOS semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS492437A (en) * | 1972-04-18 | 1974-01-10 |
-
1980
- 1980-02-16 JP JP55018294A patent/JPS5837989B2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS492437A (en) * | 1972-04-18 | 1974-01-10 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6023290U (en) * | 1983-07-26 | 1985-02-18 | 株式会社荏原製作所 | drain pump |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55127052A (en) | 1980-10-01 |
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