JPS5835953A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5835953A JPS5835953A JP13412381A JP13412381A JPS5835953A JP S5835953 A JPS5835953 A JP S5835953A JP 13412381 A JP13412381 A JP 13412381A JP 13412381 A JP13412381 A JP 13412381A JP S5835953 A JPS5835953 A JP S5835953A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- metal foil
- metal
- metallic foil
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置に係り、半導体装置を構成する半
導体ペレツトに可撓性の電極を取付けた改良された半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to an improved semiconductor device in which flexible electrodes are attached to semiconductor pellets constituting the semiconductor device.
半導体ペレツ。トは片側又は両面に金属板を取付けるの
が普通であり、これらの金属板は半導体ペレット上の金
属電極と大体同じ大きさである場合が多い。第１図は、
従来の電力用半導体装置の構造例を示す。（ｂ）は（ａ
）のＡ−Ａ′断面である。半導体ペレット１０５の両面
には、金属電極膜（図示せずンがもうけられており、こ
の金属電極膜の形状と大略同形の金属板が半導体ペレッ
ト１０５の両面にもうけられる。半導体ペレット１０５
の下面は、ペレット取付は板１０６に圧着あるいは接続
され、熱並びに電流を通じさせる。半導体ペレット１０
５の上面は、二つの半導体領域の電極とそれぞれほぼ同
形の形状と、リボン形部１０２゜１０３および平面部１
０１，１０４をもつ帯状の導体と接続される。導体の平
面部１０１，１０４は外部引出し部材と接続される。Semiconductor pellets. It is common for semiconductor pellets to have metal plates attached to one or both sides, and these metal plates are often approximately the same size as the metal electrodes on the semiconductor pellet. Figure 1 shows
An example of the structure of a conventional power semiconductor device is shown. (b) is (a
). A metal electrode film (not shown) is formed on both sides of the semiconductor pellet 105, and a metal plate having approximately the same shape as the metal electrode film is formed on both sides of the semiconductor pellet 105.Semiconductor pellet 105
The underside of the pellet mount is crimped or connected to plate 106 to conduct heat and electrical current. Semiconductor pellet 10
The upper surface of 5 has substantially the same shape as the electrodes of the two semiconductor regions, ribbon-shaped portions 102 and 103, and flat portion 1.
It is connected to a strip-shaped conductor having numbers 01 and 104. The flat portions 101 and 104 of the conductor are connected to an external lead-out member.
従来、上記の導体を、機械的な打ち抜き加工や切削加工
した場合には、上記のリボン形部、平面部を成型するこ
とができた。しかしこの方法は導体の成型や接続など半
導体装置の製造工程および部品数が増加する。Conventionally, when the above-mentioned conductor was mechanically punched or cut, it was possible to form the above-mentioned ribbon-shaped part and flat part. However, this method increases the number of semiconductor device manufacturing steps such as molding and connection of conductors and the number of components.
半導体装置に接続される導体を生産性良く半導体ペレッ
トの電極に接続する方法として、テープキャリヤ法があ
る。これは連続した絶縁性フィルム部材に導電性金属箔
を貼り合わせ、導電性金属箔を所望の形状に化学的にエ
ツチング加工して作られる。所望の形状に加工さ扛た導
電性金属箔の一部は、半導体ペレットの金属電極に接続
される。A tape carrier method is known as a method for connecting a conductor connected to a semiconductor device to an electrode of a semiconductor pellet with high productivity. This is made by bonding a conductive metal foil to a continuous insulating film member and chemically etching the conductive metal foil into a desired shape. A portion of the conductive metal foil processed into a desired shape is connected to the metal electrode of the semiconductor pellet.
テープキャリヤを構成する部材は、連続的にテープを供
給するため、薄い絶縁性フィルム部材と導電性金属箔を
用い、これらの部材は共に可撓性を有している。In order to continuously supply the tape, the members constituting the tape carrier include a thin insulating film member and a conductive metal foil, both of which have flexibility.
このような導電性金属箔の付着さｎたテープを使う場合
に生ずる問題は、導電性金属箔および絶縁性フィルム部
材ともに可撓性があるため、第１図に示した従来例のよ
うに導線を成型することが困難なことである。このため
、導電性金属箔と半導体ペレットの金属電極および導電
性金属箔を外部に引き出すための金属端子とが一体にな
った構造の半導体装置では、半導体ペレット内に形成さ
れた接合が半導体ペレットの外周部で露出している箇所
と導電性金属箔との間が近接していると、高電場が発生
して放電し、半導体装置としての機能が失なわれる恐れ
がある。The problem that arises when using such a tape with conductive metal foil attached is that both the conductive metal foil and the insulating film member are flexible, so if the conductor wire is It is difficult to mold. Therefore, in a semiconductor device with a structure in which a conductive metal foil, a metal electrode of a semiconductor pellet, and a metal terminal for drawing out the conductive metal foil to the outside are integrated, the bond formed inside the semiconductor pellet is If the exposed portion on the outer periphery and the conductive metal foil are close to each other, a high electric field may be generated and discharge may occur, leading to loss of functionality as a semiconductor device.
本発明の目的は、半導体ペレットと導電性金属箔との間
の放電を防止した、新規な構造の半導体装置を提供する
ことにある。An object of the present invention is to provide a semiconductor device with a novel structure that prevents discharge between a semiconductor pellet and a conductive metal foil.
本発明の他の目的は、信頼性の高い半導体装置を提供す
ることにある。Another object of the present invention is to provide a highly reliable semiconductor device.
本発明の特徴は、半導体基体の主表面に形成された電極
膜と接続された金属箔と、半導体基体に形成された接合
端部とを電気的に遠ざけるために、金属箔を接続した電
極端子の端子面を、半導体基体の電極面より高くした構
造にある。A feature of the present invention is that the electrode terminal to which the metal foil is connected is used to electrically distance the metal foil connected to the electrode film formed on the main surface of the semiconductor substrate from the bonding end formed on the semiconductor substrate. The terminal surface of the semiconductor substrate is higher than the electrode surface of the semiconductor substrate.
以下、本発明を実施例により詳細に説明する。Hereinafter, the present invention will be explained in detail with reference to Examples.
第２図に、ＧＴＯサイリスタを用いた本発明の実施例の
構造を示す。第２図（ｂ）は（ａ）のＡ −Ａ’断面、
（Ｃ）は（ａ）のＢ −Ｂ’断面である。図でサイリス
タ基体２００は、ｐエミッタ２０１、ｎベース２０２、
ｐベース２０３、ｎエミッタ２１６、ガラスパッシベー
ション２１５．ｎエミッタ２１６とオーミック接続する
カンード金属電極２０９、ｎエミッタ２１６の露出面と
同一表面に露出したｐベース２０３とオーミック接続す
る制御電極であるゲート金属電極２０８、ｐエミッタ２
０１にオーミック接続した他方の主電極であるアノード
電極２０４から成る。ゲート金属電極２０８、カンード
金属電極２０９、アノ山ド電極２０４は半田付けが可能
で、（１）ｎ型、ｐ型のシリコン基板と低抵抗のオーミ
ックコンタクトが可能であること、（２ンシリコン基板
と密着性が良いこと、（３ン抵抗率が小さいこと、（４
）外部配線とのボンディングが容易であること等の条件
を満す金属膜が用いられる。本発明ではｃｒ−Ｎｉ−Ａ
ｇ多層金属膜を、カンード金属電極２０９およびゲート
金属電極２０８については、リフトオフ法で選択的に、
アノード電極２０４については全面に形成した。FIG. 2 shows the structure of an embodiment of the present invention using a GTO thyristor. Figure 2 (b) is the A-A' cross section of (a),
(C) is a BB' cross section of (a). In the figure, the thyristor base 200 includes a p emitter 201, an n base 202,
P base 203, N emitter 216, glass passivation 215. A canned metal electrode 209 is ohmically connected to the n emitter 216, a gate metal electrode 208 is a control electrode that is ohmically connected to the p base 203 exposed on the same surface as the exposed surface of the n emitter 216, and the p emitter 2
The anode electrode 204 is the other main electrode and is ohmically connected to the anode electrode 204. The gate metal electrode 208, the canned metal electrode 209, and the anode metal electrode 204 can be soldered. Good adhesion, (3) low resistivity, (4)
) A metal film is used that satisfies conditions such as ease of bonding with external wiring. In the present invention, cr-Ni-A
g The multilayer metal film is selectively removed by a lift-off method for the canned metal electrode 209 and the gate metal electrode 208.
The anode electrode 204 was formed on the entire surface.
図で２１７は、キャリヤテープ２０５、導電性金属箔で
できたカソード電極金属箔２０６、ゲート電極金属箔２
０７からなる複合電極材である。In the figure, 217 is a carrier tape 205, a cathode electrode metal foil 206 made of conductive metal foil, and a gate electrode metal foil 2.
This is a composite electrode material made of 07.
カソード電極金属箔２０６は、ＧＴＯサイリスタのカン
ード金属電極２０９と、またゲート電極金属箔２０７は
ＧＴＯサイリスタのゲート金属電極２０８と半田層２１
４を介して接続され、一体化された。この複合電極材２
１７は有機絶縁テープ゛をベースとして、その表面に銅
箔などの導電性金属箔を接着剤を用い、あるいは熱圧着
法により貼り合わせたものである。キャリヤテープ２０
５は耐熱性に優れているボ４ノイミドフイルム、耐熱性
では劣るが安価なポリエステルフィルム、透明度は劣る
が耐熱性が優れているガラスエポキシ材等が使用でき、
る。接着剤としては、エポキシ系接着剤、イミド系接着
剤が使用できる。The cathode metal foil 206 connects the cando metal electrode 209 of the GTO thyristor, and the gate electrode metal foil 207 connects the gate metal electrode 208 of the GTO thyristor to the solder layer 21.
4 and integrated. This composite electrode material 2
No. 17 is based on an organic insulating tape, and a conductive metal foil such as copper foil is bonded to the surface of the tape using an adhesive or by thermocompression bonding. carrier tape 20
5 can be used such as a polyester film which has excellent heat resistance, a polyester film which has poor heat resistance but is inexpensive, and a glass epoxy material which has poor transparency but excellent heat resistance.
Ru. As the adhesive, an epoxy adhesive or an imide adhesive can be used.
本実施例ではポリイミドフィルムに銅箔をエポキシ系接
着剤で貼り合わせたものを使用した。銅箔、ポリイミド
フィルムの厚さは複合電極材の可撓性の点でそれぞれ１
０〜１００μＷ、２０〜４００μｍが望ましい。本発明
の実施例では、銅箔は３５μｍ、ポリイミドフィルムは
１２５μｍとした。ゲート電極金属箔２０７、カソード
電極金属箔２０６の形状は、複合電極材をホトレジスト
法およびレジスト印刷法により、銅箔をエツチングして
形成される。In this example, a polyimide film bonded to copper foil with an epoxy adhesive was used. The thickness of the copper foil and polyimide film is 1% each in terms of flexibility of the composite electrode material.
0 to 100 μW and 20 to 400 μm are desirable. In the example of the present invention, the copper foil was 35 μm thick, and the polyimide film was 125 μm thick. The shapes of the gate electrode metal foil 207 and the cathode electrode metal foil 206 are formed by etching the copper foil of the composite electrode material using a photoresist method and a resist printing method.
複合電極材２１７の一部であるカンード電極金属箔２０
６はカンード電極支持板２１０に、ゲート電極金属箔２
０７はゲート電極支持板２１１にそｎぞれ半田層２０６
と２０７で接続し、一体化した。カンード電極支持板２
１０、ゲート電極支持板２１１は、半田で接合される部
材であればよく、銅板、鋼板、クラツド板、あるいはこ
れらの材料の表面にニッケルなどをメッキした部材、あ
るいはアルミナなどのセラミックの表面に上記の金属材
料をメッキあるいは接合した板が用いられる。図に示す
ように、ＧＴＯサイリスタ基板２００、複合電極材２１
７、ゲート電極支持板２１１、カンード電極支持板２１
０の一体構造において、カンード・電極金属箔２０６お
よびゲート電極金属箔２０７の露出した面を、図上、ゲ
ート金属電極２０８の面よりも高くする。この構造によ
り、可撓性のある複合電極材は、ＧＴＯサイリスタ基板
２００に接触することなく、またＧＴＯサイリスク基板
２００のｎベース２０２とｐベース２０３間のｐｎ接合
の露出端部と近接しない。Canned electrode metal foil 20 that is part of composite electrode material 217
6 is a gate electrode metal foil 2 on a cando electrode support plate 210.
07 is a solder layer 206 on each gate electrode support plate 211.
It was connected with 207 and integrated. Cando electrode support plate 2
10. The gate electrode support plate 211 may be any member that can be joined by soldering, such as a copper plate, a steel plate, a clad plate, a member plated with nickel or the like on the surface of these materials, or a member plated with nickel or the like on the surface of a ceramic such as alumina. A plate plated or bonded with metal materials is used. As shown in the figure, a GTO thyristor substrate 200, a composite electrode material 21
7. Gate electrode support plate 211, cand electrode support plate 21
In the integrated structure of No. 0, the exposed surfaces of the cando/electrode metal foil 206 and the gate electrode metal foil 207 are made higher than the surface of the gate metal electrode 208 in the figure. With this structure, the flexible composite electrode material does not contact the GTO thyristor substrate 200 or come close to the exposed end of the pn junction between the n-base 202 and p-base 203 of the GTO thyristor substrate 200.
上記ＧＴＯサイリスタ基体２００、複合電極材２１７、
ゲート電極支持板２１１、カンード電極支持板２１０の
一体構造を製造する工程を以下に述べる。The above GTO thyristor base 200, composite electrode material 217,
The steps for manufacturing the integrated structure of the gate electrode support plate 211 and the cand electrode support plate 210 will be described below.
第３図は、複合電極材２１−７を多数箇連続して形成し
た複合電極テープ３００である。第３図で（ｂ）は（ａ
）のＡ−Ａ’断面を示す。複合電極テープ３００は、本
実施例では厚さが１２５μｍのポリイミドテープ３０１
に厚さ３５μｍの銅箔（図示せず）をエポキシ系接着剤
で貼り合わせ、スプロケット孔３０３を打ち抜き加工し
た後、ホトエツチング法で銅箔をエツチングして得られ
た。この際、半田メッキ外部引き出しり−ド３０２を残
した。半田メッキ外部引き出しり一部３０２を電極とし
、Ａ。FIG. 3 shows a composite electrode tape 300 in which a large number of composite electrode materials 21-7 are continuously formed. In Figure 3, (b) is (a
) is shown. In this embodiment, the composite electrode tape 300 is a polyimide tape 301 with a thickness of 125 μm.
A copper foil (not shown) having a thickness of 35 μm was bonded to the substrate using an epoxy adhesive, sprocket holes 303 were punched out, and the copper foil was etched using a photo-etching method. At this time, the solder plated external drawer door 302 was left. The solder plated external drawer part 302 is used as an electrode.A.
Ａ′の部分をテープで被覆してマスクし、半田メッキ浴
中で半田層２１２，２１３，２１４を形成した。半田の
組成としては、ｐｂ−８ｎ系、ｐｂ−８ｎ−Ａｇ系、あ
るいはｐｂ、ｓｎ の２層メッキ、さらにｐｂとｐｂ−
８ｎ半田の２層メッキが優れている。The portion A' was masked by covering with tape, and solder layers 212, 213, and 214 were formed in a solder plating bath. Solder compositions include pb-8n system, pb-8n-Ag system, two-layer plating of pb and sn, and pb and pb-
The two-layer plating of 8N solder is excellent.
ＧＴＯ？イリスタ基体２００と複合電極材２１７との接
続は、次のように行なわ扛る。すなわちまずＧＴＯサイ
リスク基体２００を、加熱した支持基体上に置く。次に
ゲート金属電極２０８、カンード金属電極２０９の上方
にスプロケット孔３０３の送りで運ばれてきた複合電極
テープ３００のゲート電極金属箔２０６、カンード電極
金属箔２０７’ｋＧＴＯサイリスタ基体の電極２０８，
２０９と位置合せし、半田層２１４にエリ接続される。GTO? The connection between the iristor base 200 and the composite electrode material 217 is performed as follows. That is, first, the GTO Cyrisk substrate 200 is placed on a heated support substrate. Next, the gate metal electrode 208, the gate electrode metal foil 206 of the composite electrode tape 300 carried by the sprocket hole 303 above the canned metal electrode 209, the canned electrode metal foil 207'kGTO thyristor base electrode 208,
209 and is edge-connected to the solder layer 214.
連続して複数個のＧ Ｔ’ ０サイリスタ基体２００が
接着された複合電極テープ３００は、１箇のＧＴＯサイ
リスタ基体２００毎に切り離した。ＧＴＯサイリスタ基
体２００と一体となった複合電極材２１７は、ゲート電
極支持板２１１、カンード電極支持板２１０と位置合わ
せした後、半田層２１２゜２１３で接続する。The composite electrode tape 300 to which a plurality of G T' 0 thyristor substrates 200 were successively adhered was separated into individual GTO thyristor substrates 200 . The composite electrode material 217 integrated with the GTO thyristor base 200 is aligned with the gate electrode support plate 211 and the cando electrode support plate 210, and then connected through solder layers 212 and 213.
本発明の一実施例によれば次の効果がある。According to one embodiment of the present invention, the following effects can be obtained.
＜１） 複合電極材が可撓性を有しているので、特別
な形状に成型した部材を使用する必要がなく、半導体装
置を生産性良く製造できる。<1) Since the composite electrode material has flexibility, there is no need to use members molded into a special shape, and semiconductor devices can be manufactured with high productivity.
（２）複合電極材のゲート電極金属箔およびカンード電
極金属箔と、ＧＴＯサイリスタ基体の外周部が近接しな
いため、ゲート電極金属箔およびカンード電極金属箔と
Ｇ Ｔ、 ０サイリスタ基体との間で放電等を起こすこ
とがなく、半導体装置の信頼性が向上する。(2) Since the gate electrode metal foil and cando electrode metal foil of the composite electrode material are not close to the outer periphery of the GTO thyristor base, discharge occurs between the gate electrode metal foil and cando electrode metal foil and the GTO thyristor base. etc., and the reliability of the semiconductor device is improved.
第４図は、本発明の一実施例の半導体素子をパッケージ
に組み込んだ例であり、（ｂ）は（ａ）でのＡ−Ｘ断面
である。半導体装置取付は用のｐ ｅ −Ｎ ｉ系の金
属板４０１と銅のヒートシンク兼アノード電極板４０２
を溶接加工して一体構造とし、アノード電極板４０２の
上にＭＯ、、ＳるいはＷ製の金属ディスク４０３が半田
層４０４を介して接合されている。金属ディスク４０３
の上面には、上面にゲート電極メタライズ層４０５とカ
ンード電極メタライズ層４０６が形成され、下面に全面
がＷ′１ ・。FIG. 4 shows an example in which a semiconductor element according to an embodiment of the present invention is assembled into a package, and (b) is a cross section taken along line A-X in (a). A p e -Ni metal plate 401 and a copper heat sink/anode electrode plate 402 are used for mounting semiconductor devices.
are welded to form an integral structure, and a metal disk 403 made of MO, S, or W is joined to the anode electrode plate 402 via a solder layer 404. metal disc 403
A gate electrode metallized layer 405 and a cando electrode metallized layer 406 are formed on the upper surface, and the entire lower surface is covered with W'1.
たけＭＯ等でメタライズされたセラミック製の絶縁基板
４０７、およびＧＴＯサイリスタ基体２００のアノード
電極がそれぞれ半田層４０８を介して接続される。銅線
に銀メツキ加工したゲート電極リード４０９、カンード
電極リード４１０が、半円層を介してそれぞれゲート電
極メタライズ層４０５とカンード電極メタライズ層４０
６に接続されている。A ceramic insulating substrate 407 metallized with bamboo MO or the like and an anode electrode of the GTO thyristor base 200 are connected via a solder layer 408, respectively. A gate electrode lead 409 and a canned electrode lead 410, which are silver-plated copper wires, are connected to a gate electrode metallized layer 405 and a canned electrode metallized layer 40, respectively, via a semicircular layer.
6.
第５図は、本発明の一実施例の半導体素子を第４図と異
なるパッケージに組み込んだ例である。FIG. 5 shows an example in which a semiconductor element according to an embodiment of the present invention is assembled into a package different from that in FIG. 4.
第５図Φ）はＣａ）のＡ−４断面を示す。図において両
面にＮｉなとの電解メッキ加工した銅のヒートシンク板
５０１に、ＷまたはＭＯでメタライズしたアルミナ等の
セラミック製絶縁基板５０２を半田層５０３ｔｌ−介し
て一体化し、絶縁基板５０２の上面のメタライズ領域に
、Ｎｉメッキで両面を被覆した銅板などを用いたゲート
電極板５０４、カンード電極板５０５、および金属ディ
スク５０６が、それぞれ半田層５０７，５０８，５０９
を介して接続されている。金属ディスク５０６の上には
、シリコン基体と熱膨張係数が近く、熱伝導率が比較的
良好なＷまたはＭＯの第２の金属ディスク５１６が半田
層５１１を介して接続されている。FIG. 5 Φ) shows the A-4 cross section of Ca). In the figure, a ceramic insulating substrate 502 made of alumina or the like metalized with W or MO is integrated with a copper heat sink plate 501 electrolytically plated with Ni on both sides via a solder layer 503tl-, and the upper surface of the insulating substrate 502 is metallized. A gate electrode plate 504, a canned electrode plate 505, and a metal disk 506 each using a copper plate coated on both sides with Ni plating are placed in the solder layers 507, 508, and 509, respectively.
connected via. A second metal disk 516 made of W or MO, which has a coefficient of thermal expansion close to that of the silicon substrate and relatively good thermal conductivity, is connected to the metal disk 506 via a solder layer 511 .
上述の実施例では、ＧＴＯサイリスタを用いたが、ダイ
オード、トランジスタ、サイリスタのいずれの半導体装
置に適用できることはいうまでも ・ない。また、複
合電極テープの樹脂部分は半導体装置完成後残存してい
ても、していなくとも良い。In the above embodiment, a GTO thyristor is used, but it goes without saying that the present invention can be applied to any semiconductor device such as a diode, a transistor, or a thyristor. Furthermore, the resin portion of the composite electrode tape may or may not remain after the semiconductor device is completed.
本発明によれば、
（１）半導体基体から電気的に有効に電極リードをとり
出すことができ、かつ半導体基体から外部電極端子への
接続が容易で、半導体装置の製造を容易にすることがで
きる。According to the present invention, (1) electrode leads can be electrically effectively taken out from the semiconductor substrate, and connection from the semiconductor substrate to external electrode terminals is easy, which facilitates the manufacture of semiconductor devices; can.
（２）電気的な接続不良がなく、信頼性の高い半導体装
置が得られる。(2) A highly reliable semiconductor device with no electrical connection defects can be obtained.
（３）短絡事故あるいは放電事故の恐れのない半導体装
置が簡単に得られるという効果がある。(3) There is an effect that a semiconductor device without fear of short-circuit or discharge accidents can be easily obtained.
ケ
第１図は本発明の従来例、第２図ないし第１図は本発明
の実施例を示す図である。
２００・・・サイリスタ基体、２０５・・・キャリヤテ
ープ、２１７・・・複合電極材、３００・・・複合電極
テー愼３図
第５図Fig. 1 shows a conventional example of the present invention, and Figs. 2 to 1 show embodiments of the present invention. 200...Thyristor base, 205...Carrier tape, 217...Composite electrode material, 300...Composite electrode material Figure 3
Claims (1)
導体基体の一生表面に形成された所定の電極膜と、上記
電極膜に接続され電極膜と略同形の部分と、この部分と
一体でありこの部分から上記電極膜の外方へ延びる外部
引出部分とからなる金属箔と、上記金属箔の外部引出部
分の端部に接続された電極端子とを具備し、上記金属箔
が接続された半導体基体の電極膜面よりも、上記金属箔
が接続された電極端子面の方が高くされたことを特徴と
する半導体装置。1. A semiconductor substrate having at least one main surface, a predetermined electrode film formed on the surface of the semiconductor substrate, a part connected to the electrode film and having substantially the same shape as the electrode film, and a part that is integral with this part and has the same shape as the electrode film. A semiconductor substrate to which the metal foil is connected, the metal foil comprising an external lead-out portion extending from the electrode film to the outside of the electrode film, and an electrode terminal connected to an end of the external lead-out portion of the metal foil. A semiconductor device characterized in that an electrode terminal surface to which the metal foil is connected is made higher than an electrode film surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13412381A JPS5835953A (en) | 1981-08-28 | 1981-08-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13412381A JPS5835953A (en) | 1981-08-28 | 1981-08-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5835953A true JPS5835953A (en) | 1983-03-02 |
Family
ID=15120995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13412381A Pending JPS5835953A (en) | 1981-08-28 | 1981-08-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5835953A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5506425A (en) * | 1993-03-31 | 1996-04-09 | Siemens Components, Inc. | Semiconductor device and lead frame combination |
| KR100261959B1 (en) * | 1996-02-01 | 2000-07-15 | 포만 제프리 엘 | Electronic package with strain relief means and method of making |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5341177A (en) * | 1976-09-28 | 1978-04-14 | Nec Corp | Mounting method of electronic parts |
| JPS5366371A (en) * | 1977-10-20 | 1978-06-13 | Fujitsu Ltd | Manufacture for semiconductor device |
-
1981
- 1981-08-28 JP JP13412381A patent/JPS5835953A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5341177A (en) * | 1976-09-28 | 1978-04-14 | Nec Corp | Mounting method of electronic parts |
| JPS5366371A (en) * | 1977-10-20 | 1978-06-13 | Fujitsu Ltd | Manufacture for semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5506425A (en) * | 1993-03-31 | 1996-04-09 | Siemens Components, Inc. | Semiconductor device and lead frame combination |
| KR100261959B1 (en) * | 1996-02-01 | 2000-07-15 | 포만 제프리 엘 | Electronic package with strain relief means and method of making |
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