JPS5835371B2 - semiconductor storage device - Google Patents
semiconductor storage deviceInfo
- Publication number
- JPS5835371B2 JPS5835371B2 JP55004883A JP488380A JPS5835371B2 JP S5835371 B2 JPS5835371 B2 JP S5835371B2 JP 55004883 A JP55004883 A JP 55004883A JP 488380 A JP488380 A JP 488380A JP S5835371 B2 JPS5835371 B2 JP S5835371B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- column
- region
- mos
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 230000015654 memory Effects 0.000 description 18
- 238000000034 method Methods 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
- H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明は半導体記憶装置とくに大容量のＲＯＭ装置等に
関し、その内部寄生容量によって制限されている動作速
度を改善し、更に高速動作のものを得ることを目的とす
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory devices, particularly large-capacity ROM devices, etc., and an object thereof is to improve the operating speed, which is limited by the internal parasitic capacitance, and to obtain an even faster operating device.
従来ＲＯＭ装置は、記憶素子としてダイオードを用いた
ものやその他種々のものがあるが、近年高集積化が可能
なＭＯＳ）ランジスタを用いたものが多く用いられてい
る。Conventional ROM devices include those using diodes as storage elements and various other types, but in recent years, ROM devices using MOS (MOS) transistors, which can be highly integrated, have been increasingly used.
記憶素子の配列方法として、第１図に示すようにＭＯＳ
）ランジスタＱのソースが接地され、ゲートがロウ線を
介してロウアドレス回路に接続され、ドレインがコラム
線にコラムアドレスおよびセンス回路が接続された方式
が一般に用いられてきた。As a method of arranging memory elements, as shown in Fig. 1, MOS
) A system has generally been used in which the source of transistor Q is grounded, the gate is connected to a row address circuit via a row line, and the drain is connected to a column line with a column address and sense circuit.
又、第２図に示すように更に高集積化及び低消費電力化
をはかるため、コラム線とセンス線を設け、トランジス
タのソースをコラム線を介してコラムアドレス回路に、
ドレインをセンス線を介してセンス回路に、ゲートをロ
ウ線を介してロウアドレス回路に接続し、選択すべきコ
ラム線のみを接地する方式も用いられている。In addition, as shown in Figure 2, in order to achieve higher integration and lower power consumption, column lines and sense lines are provided, and the source of the transistor is connected to the column address circuit via the column line.
A method is also used in which the drain is connected to a sense circuit via a sense line, the gate is connected to a row address circuit via a row line, and only the column line to be selected is grounded.
又、スタティックＲＡＭ等では、例えば第１図の記憶用
ＭＯＳトランジスタの所に７リツプフロツプ素子が用い
られ、原理的には記憶用素子が異なるのみで、同様の構
成になっている。In addition, in a static RAM or the like, for example, seven lip-flop elements are used in place of the storage MOS transistor shown in FIG. 1, and the structure is basically the same except that the storage element is different.
ＲＯＭ装置のセンス回路の１例を第３図に示す。An example of a sense circuit of a ROM device is shown in FIG.
この例はＥ／Ｄ型ｎ−チャネルＭＯ８）ランジスタによ
る回路で、非同期動作である。This example is a circuit using an E/D type n-channel MO8 transistor and operates asynchronously.
記憶素子をＭ３として、ロウ線Ｒ３によってＭ３が選択
されているとする。Assume that the memory element is M3 and that M3 is selected by row line R3.
コラム線Ｓ３はトランジスタＱ３１を通じて充電されて
おり、選択されたＭ３によりコラム線Ｓ３を〃Ｏ〃レベ
ルにスル。Column line S3 is charged through transistor Q31, and selected M3 pulls column line S3 to 〃O〃 level.
Ｑ３□・Ｏ３３はインバータ回路であり、コラムＳ３の
レベルが〃０〃、〃Ｉ〃に対応して出力Ｏ８を得る。Q3□・O33 is an inverter circuit, which obtains an output O8 in response to the level of column S3 being "0" or "I".
又、ロウ線Ｒ８′のごとく選択された場所にトランジス
タＭ３がない場合は（Ｍ、 ＝ ｔｔ Ｑ ｔｔと称す
る）Ｓ。Further, if the transistor M3 is not located at the selected location such as the row line R8', then the signal is S (referred to as M, = tt Q tt).
は放電されず、したがって、Ｏ８は〃Ｏ〃となり、Ｍ、
がある場合（Ｍ＝〃■〃と称する）、０３は１／ ■／
／となる。is not discharged, therefore O8 becomes 〃O〃, and M,
If there is (referred to as M=〃■〃), 03 is 1/■/
/becomes.
第４図に第１図の例のメモリ用トランジスタの模式的断
面図を示す。FIG. 4 shows a schematic cross-sectional view of the memory transistor of the example shown in FIG.
ｈ工学導体基板、２１．２３は第１図のトランジスタＭ
３のソースで、２２はドレイン、４１．４２はゲートで
ロウ線に相当する。h Engineering conductor substrate, 21.23 is the transistor M in Fig. 1
3 is the source, 22 is the drain, and 41.42 is the gate, which corresponds to the row line.
３１は薄いゲート絶縁膜、３２は厚いフィールド絶縁膜
である。31 is a thin gate insulating film, and 32 is a thick field insulating film.
５は絶縁膜、６はコラム線となる金属配線である。5 is an insulating film, and 6 is a metal wiring serving as a column line.
この図の例では２１．２３は接地電位に接続されており
、又、２１．２３゜４１．４２は図面と垂直方向すなわ
ちロウ方向に延長されている。In the example shown in this figure, 21.23 is connected to the ground potential, and 21.23° and 41.42 extend in the direction perpendicular to the drawing, that is, in the row direction.
６はコラム方向に延長されていて、他のトランジスタの
ドレインに接続される。6 extends in the column direction and is connected to the drains of other transistors.
メモリの情報は、ゲート絶縁膜の厚さによって定められ
、すなわち、薄いゲート絶縁膜３１の場合にはトランジ
スタＭ３がある状態に対応し、フィールド絶縁膜３２の
場合は記憶素子となるトランジスタがＲ８′のロウ線の
ごとくない状態Ｍ３＝〃Ｏ〃に対応する。The memory information is determined by the thickness of the gate insulating film, that is, in the case of the thin gate insulating film 31, the transistor M3 corresponds to the state, and in the case of the field insulating film 32, the transistor serving as the storage element is R8'. This corresponds to the state M3=〃O〃 which is not like a row line.
ところで、大容量のＲＯＭ、例えば６４にピッ）ＲＯＭ
では２５６０つ×２５６コラムの構成とすれば、コラム
方向、この場合コラム線６には２５６ケの記憶用トラン
ジスタが接続され得るようになるため、大きな寄生容量
ヲ持つととＫｊ、Ｃる。By the way, large capacity ROM (for example 64) ROM
If the configuration is 2560 x 256 columns, 256 storage transistors can be connected in the column direction, in this case to the column line 6, and therefore have a large parasitic capacitance Kj,C.
この寄生容量は例えば、第３図のＣ５で示されているが
、通常１０ＰＦ程度もあり、コラム線の応答速度を遅く
する。This parasitic capacitance, shown for example by C5 in FIG. 3, is usually about 10 PF and slows down the response speed of the column line.
又、メモリ用トランジスタＭ３は集積度の関係で小さな
サイズで構成されているため、大容量のメモリでも同じ
寸法が用いられており、メモリの大容量化によって寄生
容量が増加するにもかかわらず、トランジスタによって
の放電能力は増加しない。Furthermore, since the memory transistor M3 is configured with a small size due to the degree of integration, the same size is used even in large capacity memories, and even though parasitic capacitance increases as memory capacity increases, The discharge capacity by the transistor is not increased.
本発明はこのような検討に鑑み、記憶用トランジスタの
放電能力を、集積度を保ちつつバイポーラトランジスタ
を付加して高めることを特徴とするものである。In view of such considerations, the present invention is characterized by increasing the discharge capacity of a memory transistor by adding a bipolar transistor while maintaining the degree of integration.
第５図ａ −ｅに、本発明の１実施例のＲＯＭの要部の
製造工程を説明する断面図を示す。5a to 5e are cross-sectional views illustrating the manufacturing process of essential parts of a ROM according to an embodiment of the present invention.
第５図ａで１０１はシリコン基板で、例えばＰ型１５〜
２５Ω備のものである。In FIG. 5a, 101 is a silicon substrate, for example P type 15~
It is equipped with 25Ω.
表面に薄いシリコン酸化膜１０２とシリコンナイトライ
ド膜１０３の積層膜を設け、フィールド酸化膜を形成す
る部分にフォトエッチ工程で窓あげする。A laminated film of a thin silicon oxide film 102 and a silicon nitride film 103 is provided on the surface, and a window is formed in a portion where a field oxide film is to be formed by a photoetch process.
次いで、窓あげした部分のシリコンを一部エッチングし
、この窓を通してチャネルストッパとしてのボロンイオ
ンを注入する。Next, a portion of the silicon in the raised window is etched, and boron ions as a channel stopper are implanted through the window.
その後選択状酸化を行ない、フィールド酸化膜１３２を
成長させる。Thereafter, selective oxidation is performed to grow a field oxide film 132.
シリコンナイトライド膜１０３及びシリコン酸化膜１０
２を除去した後、ゲート酸化膜１３１を形成後全面にポ
リシリコン膜を形成し、フォトエッチ工程によりゲート
１４１，１４２を形成する（第５図ｂ）。Silicon nitride film 103 and silicon oxide film 10
2, a gate oxide film 131 is formed, a polysilicon film is formed on the entire surface, and gates 141 and 142 are formed by a photo-etching process (FIG. 5b).
次いで、ゲート１４１，１４２をマスクとして、ゲート
酸化膜を通してイオン注入によりソース・ドレイン領域
１２２及びソース領域１２１，１２３を形成する。Next, using the gates 141 and 142 as masks, ions are implanted through the gate oxide film to form source/drain regions 122 and source regions 121 and 123.
１２３は別のトランジスタ用である。次に全面にＣＶＤ
酸化膜１５０を成長させ、フォトエッチ工程によりドレ
イン領域１２２の上に窓１５１を形成し、窓１５１より
ボロンを拡散してＰ型エミッタ１１０を形成する（第５
図Ｃ）。123 is for another transistor. Next, CVD on the entire surface
An oxide film 150 is grown, a window 151 is formed on the drain region 122 by a photo-etching process, and boron is diffused through the window 151 to form a P-type emitter 110 (fifth
Figure C).
これらのドレイン及びベースとなる領域１２２の拡散深
さと、エミッタとなる領域１１０の拡散深さは、最終的
に適当なバイポーラトランジスタ４ＲＩＥが得られるよ
うに調整する。The diffusion depths of the regions 122 that will become the drain and base and the diffusion depths of the region 110 that will become the emitter are adjusted so that a suitable bipolar transistor 4RIE is finally obtained.
次に更にＣＶＤ酸化膜１５３を成長させ、エミッタへの
窓１５２を形成しく第５図ｄ）、アルミニウムを全面に
蒸着し、フォトエッチ工程によりアルミ配線パターン１
６０を形成する（第５図ｅ）、。Next, a CVD oxide film 153 is further grown to form a window 152 to the emitter (FIG. 5d), aluminum is deposited on the entire surface, and an aluminum wiring pattern 1 is formed by a photoetch process.
60 (Fig. 5e).
ＭＯＳ）ランジスタはメモリ用として必要なときは、ソ
ース１２１、ドレイン１２２０間に薄いゲート酸化膜１
３１を介してゲート１４１を設けることにより作成され
るが、トランジスタが不必要なときは、ソース１２３、
ドレイン１２２間に厚いフィールド酸化膜１３２を介し
てゲート１４２を設げるので、この部分はトランジスタ
として動作しない。When a transistor (MOS) transistor is required for memory use, a thin gate oxide film 1 is placed between the source 121 and drain 1220.
31, but when the transistor is not needed, the source 123,
Since the gate 142 is provided between the drains 122 via the thick field oxide film 132, this portion does not operate as a transistor.
また本発明において、ドレイン１２２はバイポーラトラ
ンジスタのベースとなるので、比較的低い不純物濃度の
方が都合が良いが、その場合、ソース１２１，１２３を
同じ条件で作成するとその直列抵抗弁が重視できない場
合がある。In addition, in the present invention, since the drain 122 becomes the base of the bipolar transistor, it is convenient to have a relatively low impurity concentration, but in that case, if the sources 121 and 123 are created under the same conditions, the series resistance valve may not be important. There is.
このようなときは、ソース１２１，１２３に別の工程で
高濃度の不純物を拡散させて、ソースの直列抵抗を下げ
る方法も適用できる。In such a case, a method can also be applied in which a high concentration impurity is diffused into the sources 121 and 123 in a separate process to lower the series resistance of the sources.
第６図に本発明の詳細な説明する等価回路図を示す。FIG. 6 shows an equivalent circuit diagram explaining the present invention in detail.
図中に示した数字（１０１〜１４２）は第５図ｅの記号
に対応させである。The numbers (101 to 142) shown in the figure correspond to the symbols in FIG. 5e.
今メモリ素子Ｍ６がある場合について説明する。Now, the case where there is memory element M6 will be explained.
今多くのＭＯＳ）ランジスタのゲートに共通接続された
所定のコラ線Ｒ０が選択されて／／ （／／状態になる
とＭＯＳ）ランジスタＭ６はオン状態となり、Ｑ６のベ
ースはｉ６ の電流を流す。Now, a predetermined line R0 commonly connected to the gates of many MOS transistors is selected, and when the // state is reached, MOS transistor M6 is turned on, and the base of Q6 flows a current of i6.
バイポーラトランジスタＱ６の電流増巾率をｉ ｃ、／
ｉｂ＝ ｈＦＥとすると、ｉ ｅ＝ （１＋ｈｙＰ、）
ｉ ｂ となる。The current amplification rate of bipolar transistor Q6 is i c, /
If ib= hFE, i e= (1+hyP,)
It becomes ib.
今ＭＯ８）ランジスタＭ６がオンになって流し得る電流
ｉｂは、Ｑ６によって増巾されて、寄生容量Ｃ６の電荷
をコラム線Ｓ６を介してエミッタ電流１ｅ（ｉｂの１＋
ｈＦＦ、倍）によって放電する。The current ib that can flow when the transistor M6 (MO8) is turned on is amplified by Q6, and the charge of the parasitic capacitance C6 is transferred to the emitter current 1e (1+ of ib) through the column line S6.
hFF, times).
通常バイポーラトランジスタＱ６のｈＦＥは３０程度の
値が容易に得られる。Normally, hFE of the bipolar transistor Q6 can easily have a value of about 30.
したがって、メモリ用ＭＯＳトランジスタＭ６ の寸法
を従来と同じものにしたとしても、これらの寄生容量ｃ
６の放電を十分速くすることができる。Therefore, even if the dimensions of the memory MOS transistor M6 are the same as before, these parasitic capacitances c
6 can be made sufficiently fast.
次にＭ６カ近い場合ニかで説明する。Next, I will explain the case where M6 is close to 2.
この場合バイポーラトランジスタＱ６のベースに’ｔ”
Ｋ、Ｐ ｎジャンクションのリーク電流等に相当する電
流が流れるのみであるので、第３図で示した従来例のよ
ウニ、コラム線Ｓ６は通常プルアップされているので、
このプルアップの電流値をＰｎジャンクションのり一タ
電流分より大きくしておけば問題はない。In this case, 't' at the base of bipolar transistor Q6.
Since only the current corresponding to the leakage current of the K and Pn junctions flows, the column wire S6 is normally pulled up as in the conventional example shown in FIG.
There is no problem if the pull-up current value is made larger than the Pn junction gate current.
なお、第５図ｅの例では、バイポーラトランジスタＱ６
のコレクタに相当する部分は基板１０１で共通にしであ
るが、これらをＰｎで分離してコラム信号で選択するよ
うにもできる。In the example of FIG. 5e, the bipolar transistor Q6
The parts corresponding to the collectors are shared in common on the substrate 101, but they can also be separated by Pn and selected by column signals.
以上述べたように、本発明によれば、従来ＲＯＭ等のメ
モリの大容量化において、コラム線の寄生容量の増加に
もかかわらず、メモリ間ＭＯ８）ランジスタの放電能力
が少なくそのため動作速度が遅くなるといった問題に関
し、コラム線の放電能力をいちじるしく改善し、より高
速度、大容量のメモリを容易に実現できる。As described above, according to the present invention, when increasing the capacity of conventional memories such as ROM, despite the increase in the parasitic capacitance of column lines, the discharge capacity of MO8) transistors between memories is small, and therefore the operation speed is slow. With regard to this problem, it is possible to significantly improve the discharging capacity of column lines and easily realize higher-speed, larger-capacity memories.
第１図、第２図は従来のＲＯＭ装置のメモリ素子の配列
を説明する図、第３図は従来のＲＯＭにおけるメモリ素
子とセンス回路の動作を説明する等価回路図、第４図は
従来メモリ素子（ＭＯＳ）ランジスタ）の断面図、第５
図ａ”−ｅは本発明の１実施例のメモリ素子製造工程を
説明する断面図、第６図は本発明の詳細な説明する等価
回路図である。
Ｍ６・・・・・・ＭＯＳ）ランジスタ、Ｑ６−・・・・
・バイポーラトランジスタ、Ｓ６ ・・・・・・コラム
線、Ｒ６・・・・・・ロウ線、１０１・・・・・・Ｐ型
シリコン基板（コレクタ）、１１０・・・・・・エミッ
タ、１２１．１２３・・・・・・ソース、１２２・・・
・・・ドレイン（ベース）。Figures 1 and 2 are diagrams explaining the arrangement of memory elements in a conventional ROM device, Figure 3 is an equivalent circuit diagram explaining the operation of the memory element and sense circuit in a conventional ROM, and Figure 4 is a diagram explaining the arrangement of memory elements in a conventional ROM device. Cross-sectional view of element (MOS transistor), No. 5
Figures a"-e are cross-sectional views explaining the manufacturing process of a memory element according to one embodiment of the present invention, and Figure 6 is an equivalent circuit diagram explaining the present invention in detail. M6...MOS) transistor , Q6-...
- Bipolar transistor, S6... Column line, R6... Row line, 101... P-type silicon substrate (collector), 110... Emitter, 121. 123...source, 122...
...Drain (base).
Claims (1)
面上に他方の導電型のＭＯＳ）ランジスタを記憶装置の
情報に応じて設けた記憶装置において、前記ＭＯ８）ラ
ンジスタのソースを一方の電位に接続する手段と、前記
ＭＯ８−・ジスタのドレイン領域内に一方の導電型の
を設け、前記第１の領域、ドレイン領 び
第２の領域にてパン糸−ラトランジスタを形成して成る
ことを特徴 する半導体記憶装置。 ２ 第１のデ域、ドレイン領域、第２の領域を夫夫コレ
クタ、ベース、エミッタとすることを特徴とする特許請
求の範囲第１項に記載の半導体記憶装置。[Scope of Claims] 1. A storage device in which a MOS (MOS) transistor of the other conductivity type is provided on one main surface of a semiconductor substrate having a first region of one conductivity type according to information of the storage device, wherein the MO8 ) means for connecting the source of the transistor to one potential;
What is claimed is: 1. A semiconductor memory device characterized in that a breadth-layer transistor is formed in the first region, the drain region, and the second region. 2. The semiconductor memory device according to claim 1, wherein the first region, the drain region, and the second region are used as a collector, a base, and an emitter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55004883A JPS5835371B2 (en) | 1980-01-18 | 1980-01-18 | semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55004883A JPS5835371B2 (en) | 1980-01-18 | 1980-01-18 | semiconductor storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56101770A JPS56101770A (en) | 1981-08-14 |
| JPS5835371B2 true JPS5835371B2 (en) | 1983-08-02 |
Family
ID=11596069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55004883A Expired JPS5835371B2 (en) | 1980-01-18 | 1980-01-18 | semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5835371B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0484990A (en) * | 1990-07-30 | 1992-03-18 | Miyamoto Kk | Housing for machine sewing thread |
| JPH0521875U (en) * | 1991-09-05 | 1993-03-23 | 株式会社品田ミシン商会 | Sewing thread disorder prevention device |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5974666A (en) * | 1982-10-20 | 1984-04-27 | Ricoh Co Ltd | Memory element |
| US4868628A (en) * | 1984-08-22 | 1989-09-19 | Signetics Corporation | CMOS RAM with merged bipolar transistor |
| JPH0831541B2 (en) * | 1989-02-16 | 1996-03-27 | 株式会社東芝 | Semiconductor integrated circuit |
| US5247200A (en) * | 1989-02-16 | 1993-09-21 | Kabushiki Kaisha Toshiba | MOSFET input type BiMOS IC device |
-
1980
- 1980-01-18 JP JP55004883A patent/JPS5835371B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0484990A (en) * | 1990-07-30 | 1992-03-18 | Miyamoto Kk | Housing for machine sewing thread |
| JPH0521875U (en) * | 1991-09-05 | 1993-03-23 | 株式会社品田ミシン商会 | Sewing thread disorder prevention device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56101770A (en) | 1981-08-14 |
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