JPS5834975A - Insulated gate type field effective semiconductor device - Google Patents
Insulated gate type field effective semiconductor deviceInfo
- Publication number
- JPS5834975A JPS5834975A JP56135273A JP13527381A JPS5834975A JP S5834975 A JPS5834975 A JP S5834975A JP 56135273 A JP56135273 A JP 56135273A JP 13527381 A JP13527381 A JP 13527381A JP S5834975 A JPS5834975 A JP S5834975A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- conductivity type
- type
- gate electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
Description
【発明の詳細な説明】
本発明は絶縁ゲート壓電界効果半導体装置に係り、特に
多結晶シリコンゲート電極を有し、そのゲート電極の導
電型が、Ｎ、Ｐ双方の導電型を有する絶縁ゲート型電界
効果半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect semiconductor device, and more particularly to an insulated gate field effect semiconductor device having a polycrystalline silicon gate electrode, the gate electrode having both N and P conductivity types. The present invention relates to a type field effect semiconductor device.
従来、相補型電界効果トランジスタにおいて、Ｎチャン
ネル、Ｐチャンネルトランジスタの閾値電圧（スレッシ
ョールド電圧）は、ウェル濃度。Conventionally, in complementary field effect transistors, the threshold voltage of N-channel and P-channel transistors depends on the well concentration.
基板濃度によって決定する事が多かったが、近年、イオ
ン注入技術の進歩によシゲート電極下のシリコン−シリ
コン酸化物との界面付近へ不純物をイオン注入し、界面
近傍の不純物濃度をコントロールする事により希望する
スレッショールド電圧に定める事ができるようになって
きた。In many cases, it was determined by the substrate concentration, but in recent years, advances in ion implantation technology have made it possible to control the impurity concentration near the interface by implanting impurity ions near the silicon-silicon oxide interface under the silicate electrode. It has become possible to set the desired threshold voltage.
ところで、一般の集積回路において、その回路によって
はトランジスタのスレッショールド電圧が一種類だけで
なく、多種類ある事によシ、回路構成の簡略化、設計の
容易さ等が増す事がある。Incidentally, in general integrated circuits, depending on the circuit, transistors may have not only one type of threshold voltage but many types, which may simplify the circuit configuration and increase ease of design.
この場合、異なったスレッショールド電圧を得る為に前
述したイオン注入技術を用いる事ができるが、その場合
には異なったスレッショールド電圧としたいトランジス
タ部分以外には、イオン注入によって不純物が注入され
ない様に、イオン注入に対してマスクとなる材質（例え
ばフォトレジスト）で覆う必要がある。この様にイオン
注入技術を用いて一部のトランジスタのスレッシ、−ル
ド電圧を変更するには、そ、の製造工程中に前述した必
要以外の部分を徨うパターンを作シ出す為の工程（以下
フォトレジスト工程と称する）及びイオン注入工程の追
加が最低限必要であり、製造工程をより複雑にするとい
う欠点があった。以下、従来技術による相補型電界効果
トランジスタの製造方法の一例を第１図（ａ）〜（ｇ）
Ｋ示し、簡単に′説明する。In this case, the ion implantation technique described above can be used to obtain different threshold voltages, but in that case, impurities are not implanted by ion implantation except in the transistor parts where the different threshold voltages are desired. Similarly, it is necessary to cover it with a material (for example, photoresist) that serves as a mask for ion implantation. In order to change the threshold and voltage of some transistors using ion implantation technology in this way, it is necessary to create a pattern that extends beyond the necessary areas during the manufacturing process ( This method requires at least the addition of a photoresist process (hereinafter referred to as a photoresist process) and an ion implantation process, which has the disadvantage of making the manufacturing process more complicated. An example of a method for manufacturing a complementary field effect transistor according to the prior art is shown in FIGS. 1(a) to 1(g) below.
K is shown and briefly explained.
第１図（ａ） ： Ｎ型シリコン基板１（例えば１０１
４〜１０傭 の不純物濃度）にシリコン熱酸化膜２を設
け、所定の領域の酸化膜を除去し、イオン注入法でＰ型
不純物（例えば、ボロン）を注入し、その後１１００℃
〜１２００℃の高温で熱処理を行ない、比較的深い不純
物領域（Ｐ−ウェル）１３を形成する。FIG. 1(a): N-type silicon substrate 1 (for example, 101
A silicon thermal oxide film 2 is provided at an impurity concentration of 4 to 10 degrees centigrade), the oxide film is removed in a predetermined region, a P-type impurity (for example, boron) is implanted by ion implantation, and then heated at 1100°C.
Heat treatment is performed at a high temperature of ~1200° C. to form a relatively deep impurity region (P-well) 13.
第１図（ｂ）二次にＮチャンネル及びＰチャンネルトラ
ンジスタを形成する領域の酸化膜を除去する。FIG. 1(b) Second, the oxide film in the regions where N-channel and P-channel transistors are to be formed is removed.
第１図（Ｃ）二次に比較的薄いゲート酸化膜４を成長さ
せ、その彼さらに多結晶シリコン５を気相成長法等に依
って成長させ、通常の７オトレジストエ程を通して、ゲ
ート電極となるべき部分と配線として使用する部分を除
いて、弗酸−硝酸の混合液によって除去する。FIG. 1(C) Second, a relatively thin gate oxide film 4 is grown, and then polycrystalline silicon 5 is grown by a vapor phase growth method, etc., and a gate electrode is formed through the usual 7 photoresist process. Remove the parts except for the parts to be used as wiring and the parts to be used as wiring using a mixed solution of hydrofluoric acid and nitric acid.
第１図（ｄ）：次に、フォトレジスト６をＮチャンネル
トランジスタを形成すべき部分を覆うようにして、イオ
ン注入法によってＰ型不純物（例えばボロン）をゲート
電極の多結晶シリコン及びソース・ドレインとなるべき
部分にゲート酸化膜を通して注入し、ゲート電極をＰ型
多結晶シリコン９、及びソース・ドレインとなるＰ型不
純物拡散領域８を形成する。FIG. 1(d): Next, a photoresist 6 is placed to cover the area where an N-channel transistor is to be formed, and a P-type impurity (for example, boron) is added to the polycrystalline silicon of the gate electrode and the source/drain region by ion implantation. The impurity is implanted through the gate oxide film into the portion where the impurity is to be formed, and P-type polycrystalline silicon 9 is used as the gate electrode, and P-type impurity diffusion regions 8 are formed as the source and drain.
第１図（ｅ）：次に前工程とは逆にＰチャンネルトラン
ジスタを形成した部分を７オトレジスト１０で覆い、イ
オン注入法によってＮ型不純物（例えば、リン、ヒ素）
をゲート電極の多結晶シリコン及びソース・ドレインと
なるべき部分にゲート酸化膜を通して注入し、ゲート電
極をＮ型多結晶シリコン１２、及びソース・ドレインと
なるＮ型不純物拡散領域１１を形成する。Figure 1(e): Next, in the opposite direction to the previous step, the part where the P-channel transistor was formed was covered with a 7-photoresist 10, and N-type impurities (for example, phosphorus, arsenic) were added by ion implantation.
is implanted through the gate oxide film into the polycrystalline silicon of the gate electrode and the portions to become the source/drain to form the N-type polycrystalline silicon 12 for the gate electrode and the N-type impurity diffusion regions 11 to become the source/drain.
第１図（ｆ）二次にイオン注入による結晶のダメージを
回復させ、注入した不純物を活性化させる為の熱処理を
行なった後、酸化膜１４を気相成長法などに依って成長
させ、後に配線すべき金属との結合の為の穴１５を所定
の位置に通常のフォトレジスト工程、酸化膜除去工程を
経て設ける。FIG. 1(f) After a heat treatment is performed to recover the damage to the crystal caused by the secondary ion implantation and activate the implanted impurities, an oxide film 14 is grown by vapor phase growth, etc. A hole 15 for bonding with the metal to be wired is provided at a predetermined position through a normal photoresist process and an oxide film removal process.
第１図（ｇ）：最後に金属（例えばアルミニウム）を真
空蒸着法によって形成し所定の配線１６を施す０
以上説明したのが、Ｐウェル中にＮチャンネルトランジ
スタ、基板にＰチャンネルトランジスタを形成する従来
技術の製造方法の一例である。こｏ場合、Ｐ 、Ｎｏ）
ランジスタのスレッショールド電圧は、それぞれ、基板
濃度、Ｐ−ウェル濃度で決定され、Ｐ、Ｎチャンネルで
それぞれ一種類である。ここでそれぞれの導電型のトラ
ンジスタで異なったスレッショールド電圧を得るには、
従来ゲート酸化膜を形成彼、多結晶シリコンを気相成長
する前に、フォトレジスト工程でによって異なったスレ
ッショールド電圧を得たいトランジスタ部分以外をイオ
ン注入に対してマスクとなる物質で覆い、イオン注入を
用いなければならなｔ・つた。このように従来技術にお
いては、同一導電型で異なったスレッショールド電圧を
得るには、少なくとも１回の７オトレジストエ程とイオ
ン注入工程が必要であり、その製造工程数が増加し、よ
シ製造方法を複雑にしてしまうという欠点があった。Figure 1 (g): Finally, a metal (for example, aluminum) is formed by vacuum evaporation and a predetermined wiring 16 is applied.0 What has been explained above is the formation of an N-channel transistor in the P-well and a P-channel transistor in the substrate. This is an example of a conventional manufacturing method. If this is the case, P, No)
The threshold voltage of the transistor is determined by the substrate concentration and the P-well concentration, and is one type for each of the P and N channels. To obtain different threshold voltages for each conductivity type of transistor,
Conventionally, forming a gate oxide film, before vapor-phase growth of polycrystalline silicon, a photoresist process is used to cover areas other than the transistor parts where different threshold voltages are to be obtained with a material that serves as a mask for ion implantation. Injection must be used. In this way, in the prior art, in order to obtain different threshold voltages for the same conductivity type, at least one photoresist process and an ion implantation process are required, which increases the number of manufacturing steps and reduces the manufacturing cost. The drawback was that it made the method complicated.
本発明は、新規な構成の多結晶シリコンゲート電極によ
って容易にスレッシ、−ルド電圧を設定できる絶縁ゲー
ト型電界効果半導体装置の提供を目的とするものである
。An object of the present invention is to provide an insulated gate field effect semiconductor device in which threshold and field voltages can be easily set using a polycrystalline silicon gate electrode having a novel configuration.
本発明の他の目的は、製造工程数の増加する事なく、同
一導電型の異なったスレッシロールド電圧を持つ相補型
電界効果トランジスタを提供する事にある。Another object of the present invention is to provide complementary field effect transistors of the same conductivity type but having different threshold voltages without increasing the number of manufacturing steps.
本発明の特徴は、一導電型基板上に逆導電型のソース、
ドレイン領域が形成され、このソース。A feature of the present invention is that a source of an opposite conductivity type is placed on a substrate of one conductivity type,
A drain region is formed and this source.
ドレイン領域間の前記一導電型基板上に薄い絶縁膜を介
してゲート電極が形成された絶縁ゲート型電界効果半導
体装置において、前記ゲート電極が一導電製領域と逆導
電型領域とを含む多結晶シリコンによって形成されてい
る絶縁ゲート型電界効呆半導体装置にある。そして、こ
の多結晶シリコンゲート電極の少なくともソース、ドレ
イン領域近傍が逆導電型に形成されていることが好まし
い。In an insulated gate field effect semiconductor device in which a gate electrode is formed on the one conductivity type substrate between the drain regions via a thin insulating film, the gate electrode is a polycrystalline material including a one conductivity region and an opposite conductivity type region. This is an insulated gate field effect semiconductor device made of silicon. Preferably, at least the vicinity of the source and drain regions of this polycrystalline silicon gate electrode are formed to have opposite conductivity types.
さらに、この多結晶シリコンゲート電極の中央部が一導
電型に形成され、かつソース、ドレイン領域近傍の端部
が逆導電型に形成されていることが好ましい構造である
。そして、この多結晶シリコンゲート電極の一導電型領
域と逆導電型領域とをオーミック接線することによって
、Ｐｎ接合による影醤を除くことが出来るので、この絶
縁ゲート型電界効果半導体装置は極めて良好なる特性を
示す。そして、このような絶縁ゲート型電界効果半導体
装置は、相補型絶縁ゲート電界効果半導体集積回路装置
に含まれることが好ましい。Furthermore, it is a preferable structure that the central portion of the polycrystalline silicon gate electrode is formed to have one conductivity type, and the end portions near the source and drain regions are formed to be of the opposite conductivity type. By forming an ohmic tangent between the one conductivity type region and the opposite conductivity type region of the polycrystalline silicon gate electrode, it is possible to eliminate the influence caused by the Pn junction, resulting in an extremely good insulated gate field effect semiconductor device. Show characteristics. Preferably, such an insulated gate field effect semiconductor device is included in a complementary insulated gate field effect semiconductor integrated circuit device.
本発明によれば、製造工程数を増加する事なく、同一導
電型の異なったスレッシロールド電圧を持つ相補型電界
効果トランジスタを提供することが出来る。すなわち、
多結晶シリコンをゲート電極とする相補型電界効果トラ
ンジスタにおいて、ゲート電極である多結晶シリコンの
導電型が、ソース、ドレイン端ではソース、ドレインを
形成する拡散層と同一導電型とし、その中間部では逆導
電型とするように、製造工程中の７オトレジストエ程の
パターンを変更するだけで製造工程数を増加する事遊く
、同一導電型の異なったスレッシ、−ルド電圧を得る事
ができる。According to the present invention, complementary field effect transistors of the same conductivity type but having different threshold voltages can be provided without increasing the number of manufacturing steps. That is,
In a complementary field effect transistor that uses polycrystalline silicon as a gate electrode, the conductivity type of the polycrystalline silicon that is the gate electrode is the same conductivity type as the diffusion layer forming the source and drain at the source and drain ends, and By simply changing the pattern of the seven photoresist layers in the manufacturing process so as to create opposite conductivity types, it is possible to increase the number of manufacturing steps and obtain different threshold and negative voltages of the same conductivity type.
次に本発明をよシ判シ易くする為、まず第２図（２Ｉ）
〜（ωを用いて、本発明の一実施例の絶縁ゲート型電界
効果半導体装置の製造方法を工程順に説明する。Next, in order to make the present invention easier to read, first of all, Figure 2 (2I)
~ (Using ω, a method for manufacturing an insulated gate field effect semiconductor device according to an embodiment of the present invention will be explained step by step.
本製造方法では、前述した従来の絶縁ゲート型電界効果
半導体装置の製造方法の一例のうち、第１図（ａ）〜（
Ｃ）に対応する気相成長させた多結晶シリコンをゲート
電極となるべき部分及び配線として使用する部分を残し
て除去する工程迄は第２図（ａ）〜（Ｃ）から明らかな
ように同じである。This manufacturing method is one of the conventional methods for manufacturing an insulated gate field effect semiconductor device as described above.
As is clear from Figures 2 (a) to (C), the steps up to the step of removing the vapor-grown polycrystalline silicon corresponding to C), leaving behind the portions that will become gate electrodes and the portions that will be used as wiring, are the same. It is.
第２図（ｄ）：次に１フオトレジストでＮチャンネルト
ランジスタを形成すべき部分、及びＰチャンネルトラン
ジスタのゲート電極となるべき多結晶シリコンのうち、
ンース、ドレインとなるヘキ端部を除いた中間部分を覆
い、イオン注入法によってＰ型不純物をＰチャンネルト
ランジスタのゲート電極多結晶シリコンの７オトレジス
トで扱われていないソース、ドレインに近い端部、及び
ソース、ドレインとなるべき部分にゲート酸化膜を通し
て注入し、ゲート電極の一部をＰ型多結晶シリコンとし
、ソース、ドレインとなるＰ型不純物拡散領域を形成す
る。 −
第２図（ｅ）二次に前工程とは逆にＰチャンネルトラン
ジスタを形成する部分のうち、前工程で７オトレジスト
を様ったゲート電極の多結晶シリコン部を除く部分を７
オトレジストで榎い、イオン注入法によって、Ｎ型不純
物をフォトレジストで覆われていない多結晶ンリコン、
及び、ソース、ドレインとなるべき部分にゲート酸化膜
を違して注入し、Ｐチャ／ネルトランジスタのゲート電
極の中間部のＮ型多結晶シリコン、Ｎチャンネルトラン
ジスタのＮ型結晶シリコンゲート電極、及び、ソース、
ドレインとなるＮ型不純物拡散領域を形成する。FIG. 2(d): Next, the part where an N-channel transistor is to be formed using one photoresist, and the polycrystalline silicon which is to become the gate electrode of the P-channel transistor.
7. Cover the middle part except for the edges that will become the source and drain, and use ion implantation to inject P-type impurities into the gate electrode of the P-channel transistor. The impurity is implanted through the gate oxide film into the portions to become the sources and drains, and part of the gate electrode is made of P-type polycrystalline silicon, forming P-type impurity diffusion regions that will become the sources and drains. - Figure 2 (e) Second, in contrast to the previous process, out of the parts where the P-channel transistor will be formed, remove the polycrystalline silicon part of the gate electrode that was coated with 7 photoresists in the previous process.
Polycrystalline silicon that is not covered with photoresist is coated with N-type impurities by ion implantation.
Then, a gate oxide film is implanted into the parts that are to become the source and drain, and the N-type polycrystalline silicon in the middle part of the gate electrode of the P-channel/channel transistor, the N-type crystalline silicon gate electrode of the N-channel transistor, and ,sauce,
An N-type impurity diffusion region that will become a drain is formed.
第２図（０：次に通常の製造方法と同様に熱処理を行な
い、金属との結合の為の穴を設ける。FIG. 2 (0: Next, heat treatment is performed in the same manner as in the normal manufacturing method to form holes for bonding with metal.
第２図（ｇ）：最後に金属を蒸着させ、所定の配線を施
す。Figure 2 (g): Finally, metal is deposited and predetermined wiring is provided.
このように本製造方法は、通常の製造工程に対して、何
らの工程の追加なしにそのマスクパターンの変更のみで
達成する事ができる。In this manner, the present manufacturing method can be achieved by simply changing the mask pattern without adding any steps to the normal manufacturing process.
次に本発明の同一導電型で異なったスレッショールド電
圧を得る原理を説明する為、本発明の一実施例のＰチャ
ンネルトランジスタの平面図を第３図（ａ）に示す。こ
のＰチャンネルトランジスタのゲート電極は、ソース、
ドレイン端部ではＰ製条結晶シリコン２１中間部ではＮ
型多結晶シリコン２２となシ、ゲート電極中にＰＮ接合
を生じるのでＰ型多結晶シリコンとＮ型多結晶シリコン
に穴１７を設け、金属１８で互いに接続する。この場合
のこのトランジスタの電気的等価回路は、第３図（ｂ）
に示すように３つのトランジスタの直列接続回路として
表わされる。ところで電界効果トランジスタのスレッシ
、−ルド電圧ｖｔｈは次式で表ΦＭ８ ’半導体基体と
ゲート電極との仕事関数差、
ＱＳ８ ’表面準位密度、
Φｆ ：フェルミ準位、
ＱＢ 二基板の不純物密度、
Ｃｏ ：単位面積当シのゲート容量、
第３図（ｂ）に示されている本発明の一実施例であるＰ
。ｈトランジスタの３分割形（Ｍｌ 、Ｍ２ 。Next, in order to explain the principle of obtaining different threshold voltages with the same conductivity type according to the present invention, a plan view of a P-channel transistor according to an embodiment of the present invention is shown in FIG. 3(a). The gate electrode of this P-channel transistor is the source,
At the end of the drain, P made of strip crystal silicon 21 At the middle part, N
Since a PN junction is formed in the gate electrode with the type polycrystalline silicon 22, a hole 17 is provided in the P-type polycrystalline silicon and the N-type polycrystalline silicon, and they are connected to each other with a metal 18. The electrical equivalent circuit of this transistor in this case is shown in Figure 3(b).
It is expressed as a series connection circuit of three transistors as shown in FIG. By the way, the threshold voltage vth of a field effect transistor is expressed by the following formula: ΦM8' work function difference between semiconductor substrate and gate electrode, QS8' surface state density, Φf: Fermi level, QB impurity density of two substrates, Co : Gate capacitance per unit area, P which is an embodiment of the present invention shown in FIG. 3(b)
. 3-part type of h transistor (Ml, M2.
Ｍ３）トランジスタのうち、Ｍｌ 、Ｍ３とＭ２との違
いは、製造方法からもわかるように上記式（１）の項の
０Ｍ８だけである。この０Ｍ８は又、次式で表わされる
。Among M3) transistors, the only difference between M1, M3, and M2 is 0M8 in the term of the above equation (1), as can be seen from the manufacturing method. This 0M8 is also expressed by the following equation.
０Ｍｇ ＝ΦＭ−Φ８ ・・・・・・式
（２）ゲート電極がＮ型多結晶シリコンであるＭ２の０
Ｍ８は
Φｆｎ〉０
ゲート電極がＰ型多結晶シリコンであるＭｌ。0Mg = ΦM - Φ8 ...Formula (2) 0 of M2 where the gate electrode is N-type polycrystalline silicon
M8 is Ml whose gate electrode is P-type polycrystalline silicon.
Ｍ３の９Ｍｇは
Φｆｏ＜０
Φｓｏ ’ 多結Ｊ＆シリコンのコンダクションバント
端と酸化膜のコンダクションバ
ント端とのポテンシャルエネルギー
差、
Ｅｇ ：コンダクションバンドとバレンシイバンドとの
エネルギー差、
ｑ ：基板電子当りの電荷量、
Φ、 ：シリコンのコンダクションバンド端と酸化膜の
コンダクションバント端
とのポテンシャルエネルギー差、
従って、Ｍ１９Ｍ３とＭ２との０Ｍ８の差がスレッシ、
−ルド電圧の差となる。9Mg of M3 is Φfo<0 Φso' Potential energy difference between the conduction band edge of the multi-connected J&silicon and the conduction band edge of the oxide film, Eg: Energy difference between the conduction band and the valence band, q: Substrate electron Amount of charge per unit, Φ: Potential energy difference between the conduction band edge of silicon and the conduction band edge of oxide film. Therefore, the difference of 0M8 between M19M3 and M2 is the threshold,
– This is the difference in field voltage.
ΦＭ８Ｎ−ΦＭ８Ｐ”Φｆｎ−Φ（、＜０ ”・式
（５）式（５）で示されるように０Ｍｇの差は負であシ
、Ｐチャンネルトランジスタのエンハンスメントトラン
ジスタのスレッショールド電圧は負であるからＭ２のス
レッショールド電圧の絶対値は大きくなシ、従って本発
明の一実施例である第３図（ａ）のようなＰチャンネル
トランジスタのスレッシ、−ルド電圧は、Ｍ２のスレッ
シ璽−ルド電圧となり、通常Ｐチャンネルトランジスタ
よシ約０．６ｖｏｌｔ高いスレッショールド電圧を得る
事ができる。このスレッシ、−ルド電圧は、前述した様
に一切の製造工程の追加なしに得る事ができる。ΦM8N−ΦM8P”Φfn−Φ(,<0 ”・Equation (5) As shown in Equation (5), the difference of 0 Mg is negative, and the threshold voltage of the enhancement transistor of the P-channel transistor is negative. Since the absolute value of the threshold voltage of M2 is large, the threshold voltage of the P-channel transistor as shown in FIG. 3(a) which is an embodiment of the present invention is It is possible to obtain a threshold voltage that is approximately 0.6 volts higher than that of a normal P-channel transistor.This threshold voltage can be obtained without adding any manufacturing steps as described above.
なお、本発明の実施例では、Ｐチャンネルトランジスタ
について説明したが、Ｎチャンネルトランジスタについ
ても同様に実施できる事は轟然である。In the embodiments of the present invention, a P-channel transistor has been described, but it is obvious that the same can be applied to an N-channel transistor.
第１図（ａ）〜（ωは従来の相補型シリコンゲート電界
効果半導体集積回路装置の製造方法を工程順に示す断面
図、第２図（ａ）〜（ｇ）は本発明の一実施例である絶
縁ゲート型電界効果半導体装置を含む相補型シリコンゲ
ート電界効果半導体集積回路装置の製造方法を工程順に
示す断面図、第３図（ａ）は本発明の一実施例であるＰ
チャンネル型の絶縁ゲート型電界効果半導体装置の平面
図、第３図（ｂ）は第３図（ａ）で示すところの半導体
装置の電気的等価回路、である。
なお図において、１・・・・・・Ｎ型シリコン基板、２
・・・・・・酸化膜、４・・・・・・ゲート酸化膜、５
・・・・・・真性多結晶シリコン、６，１０°−−−−
−７オトレジスト、８・・・・・・Ｐ型拡散領域、９．
２１・・・・・・Ｐ型多結晶シリコン、１１・・・・・
・Ｎ型拡散領域、１２，２２・・・・・・Ｎ型多結晶シ
リコン、１３°−°−°−Ｐウェル、１４・°°・°。
気相成長酸化膜、１５．１７・・・・・・コンタクトホ
ール、１６．１８・・・・・°金属配線、である。
第１図
始１図
拍１図
１
第２図
第２図
２１ ２２ ２１
Ｇ
第３図FIGS. 1(a) to (ω) are cross-sectional views showing a conventional complementary silicon gate field-effect semiconductor integrated circuit device manufacturing method in order of process, and FIGS. 2(a) to (g) are one embodiment of the present invention. FIG. 3(a) is a cross-sectional view showing the manufacturing method of a complementary silicon gate field-effect semiconductor integrated circuit device including a certain insulated gate field-effect semiconductor device in order of steps, and FIG. 3(a) is an example of the present invention.
FIG. 3(b), a plan view of a channel type insulated gate field effect semiconductor device, is an electrical equivalent circuit of the semiconductor device shown in FIG. 3(a). In the figure, 1...N-type silicon substrate, 2
...Oxide film, 4...Gate oxide film, 5
...Intrinsic polycrystalline silicon, 6,10°----
-7 Otoresist, 8...P-type diffusion region, 9.
21...P-type polycrystalline silicon, 11...
- N-type diffusion region, 12, 22...N-type polycrystalline silicon, 13°-°-°-P well, 14.°°.°. These are a vapor-phase grown oxide film, 15.17...contact hole, and 16.18...°metal wiring. Figure 1 Start Figure 1 Beat 1 Figure 1 Figure 2 Figure 2 21 22 21 G Figure 3
Claims (5)
領域が形成され、該ソース、ドレイン領域間の前記一導
電型基板上に薄い絶縁膜を介してゲート電極が形成され
た絶縁ゲート型電界効果半導体装置において、前記ゲー
ト電極が一導電型領域と逆導電型領域とを含む多結晶シ
リコンによって形成されていることを特徴とする絶縁ゲ
ート型電界効果半導体装置。(1) An insulated gate type in which source and drain regions of opposite conductivity type are formed on a substrate of one conductivity type, and a gate electrode is formed on the substrate of one conductivity type between the source and drain regions with a thin insulating film interposed therebetween. An insulated gate field effect semiconductor device, wherein the gate electrode is formed of polycrystalline silicon including a region of one conductivity type and a region of opposite conductivity type.
ドレイン領域近傍が逆導電型に形成されていることを特
徴とする特許請求の範囲第（１）項記載の絶縁ゲートｍ
電界効果半導体装置。(2) at least the source of the polycrystalline silicon gate electrode;
The insulated gate m according to claim (1), characterized in that the vicinity of the drain region is formed to have an opposite conductivity type.
Field effect semiconductor device.
形成され、かつソース、ドレイン領域近傍の端部が逆導
電型に形成されていることを特徴とする特許請求の範囲
第（１）項記載の絶縁ゲート型電界効果半導体装置。(3) Claim (1) characterized in that the central portion of the polycrystalline silicon gate electrode is formed to have one conductivity type, and the end portions near the source and drain regions are formed to be of the opposite conductivity type. The insulated gate field effect semiconductor device described in 2.
電型領域とがオーミック接緒されていることを特徴とす
る特許請求の範囲第（３）項記載の船縁ゲート型電界効
果半導体装置。(4) The edge gate type field effect semiconductor device according to claim (3), wherein the one conductivity type region and the opposite conductivity type region of the polycrystalline silicon gate electrode are ohmically connected.
含まｎることを特徴とする特許請求の範囲第（１）項記
載の絶縁ゲート型電界効果半導体装置。(5) The insulated gate field effect semiconductor device according to claim (1), which is included in a complementary insulated gate field effect semiconductor quadrant circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56135273A JPS5834975A (en) | 1981-08-27 | 1981-08-27 | Insulated gate type field effective semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56135273A JPS5834975A (en) | 1981-08-27 | 1981-08-27 | Insulated gate type field effective semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5834975A true JPS5834975A (en) | 1983-03-01 |
Family
ID=15147844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56135273A Pending JPS5834975A (en) | 1981-08-27 | 1981-08-27 | Insulated gate type field effective semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5834975A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61272972A (en) * | 1985-05-28 | 1986-12-03 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1981
- 1981-08-27 JP JP56135273A patent/JPS5834975A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61272972A (en) * | 1985-05-28 | 1986-12-03 | Toshiba Corp | Semiconductor device and manufacture thereof |
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