JPS5847180U - integrated circuit test clip - Google Patents

integrated circuit test clip

Info

Publication number
JPS5847180U
JPS5847180U JP13896481U JP13896481U JPS5847180U JP S5847180 U JPS5847180 U JP S5847180U JP 13896481 U JP13896481 U JP 13896481U JP 13896481 U JP13896481 U JP 13896481U JP S5847180 U JPS5847180 U JP S5847180U
Authority
JP
Japan
Prior art keywords
integrated circuit
test clip
circuit test
clip
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13896481U
Other languages
Japanese (ja)
Inventor
「えび」沢　宏
菊田　一
Original Assignee
日豊通信工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日豊通信工業株式会社 filed Critical 日豊通信工業株式会社
Priority to JP13896481U priority Critical patent/JPS5847180U/en
Publication of JPS5847180U publication Critical patent/JPS5847180U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の集積回路のテストクリップを用いた図、
第２図は本考案による集積回路のテストクリップを示す
図である。 符号の説明、１・・・・・・プリント基板、２・・・・
・・被試験集積回路、３・・・・・・テストクリップ、
４・・・・・・触子、５・・・・・・出力端子、６・・
・・・・引出線、７・・・・・・バッファ集積回路。Figure 1 is a diagram using a conventional integrated circuit test clip.
FIG. 2 is a diagram showing an integrated circuit test clip according to the present invention. Explanation of symbols, 1...Printed circuit board, 2...
...Integrated circuit under test, 3...Test clip,
4...Toucher, 5...Output terminal, 6...
... Leader line, 7 ... Buffer integrated circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 集積回路のテストクリップの触子と出力端子の間にバッ
ファ集積回路を組込み接続を行ったことを特徴とする集
積回路のテストクリップ。1. A test clip for an integrated circuit, characterized in that a buffer integrated circuit is embedded and connected between a contact of the test clip and an output terminal.
JP13896481U 1981-09-21 1981-09-21 integrated circuit test clip Pending JPS5847180U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13896481U JPS5847180U (en) 1981-09-21 1981-09-21 integrated circuit test clip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13896481U JPS5847180U (en) 1981-09-21 1981-09-21 integrated circuit test clip

Publications (1)

Publication Number Publication Date
JPS5847180U true JPS5847180U (en) 1983-03-30

Family

ID=29932174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13896481U Pending JPS5847180U (en) 1981-09-21 1981-09-21 integrated circuit test clip

Country Status (1)

Country Link
JP (1) JPS5847180U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61196081A (en) * 1985-02-26 1986-08-30 株式会社大井製作所 Door lock apparatus with actuator
JPS63140476U (en) * 1987-03-06 1988-09-16

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61196081A (en) * 1985-02-26 1986-08-30 株式会社大井製作所 Door lock apparatus with actuator
JPH0466981B2 (en) * 1985-02-26 1992-10-26 Oi Seisakusho Co Ltd
JPS63140476U (en) * 1987-03-06 1988-09-16

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