JPS583416B2 - tuned circuit - Google Patents
tuned circuitInfo
- Publication number
- JPS583416B2 JPS583416B2 JP52127891A JP12789177A JPS583416B2 JP S583416 B2 JPS583416 B2 JP S583416B2 JP 52127891 A JP52127891 A JP 52127891A JP 12789177 A JP12789177 A JP 12789177A JP S583416 B2 JPS583416 B2 JP S583416B2
- Authority
- JP
- Japan
- Prior art keywords
- tuning circuit
- variable capacitance
- circuit
- tuning
- capacitance diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Description
【発明の詳細な説明】
本発明は同調回路に関し、その目的とするところは広帯
域にわたり安定した同調がとれる同調回路を提供するに
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tuning circuit, and an object thereof is to provide a tuning circuit that can achieve stable tuning over a wide band.
従来、ＶＨＦチューナに用いられている同調回路は第１
図に示すように入力端子１からの信号をＩＦフィルタ２
、入力同調回路３を通して高周波増幅用のトランジスタ
Ｔｒに入力し、該トランジスタＴｒの出力をコイルＬ１
，Ｌ３、スイッチングダイオードＤ４ 、可変容量ダイ
オードＤ１から成る並列同調回路、および、コイルＬ２
，Ｌ４、スイッチングダイオードＤ５、可変容量ダイオ
ードＤ２から成る並列同調回路に入力し、該同調回烙に
おいて所望の信号を選択して混合回路４に入力する。Conventionally, the tuning circuit used in VHF tuners is
As shown in the figure, the signal from input terminal 1 is passed through IF filter 2.
, is inputted to a transistor Tr for high frequency amplification through the input tuning circuit 3, and the output of the transistor Tr is inputted to a coil L1.
, L3, a parallel tuned circuit consisting of a switching diode D4, a variable capacitance diode D1, and a coil L2.
, L4, a switching diode D5, and a variable capacitance diode D2.A desired signal is selected in the tuned circuit and inputted to the mixing circuit 4.
該混合回路４には局部発振回路５からの発振信号が加え
られ、ＩＦ信号をＩＦ同調回路により取出し次段に出力
する。An oscillation signal from a local oscillation circuit 5 is applied to the mixing circuit 4, and an IF signal is extracted by an IF tuning circuit and output to the next stage.
前記同調回路はスイッチングダイオードＤ４、Ｄ５によ
りコイルＬ３、Ｌ４を必要により短絡してハイバンド、
ローバンドの切換えを行い、該スイッチングダイオード
Ｄ４，Ｄ５は常時端子９からトランジスタ動作用電圧が
順方向に印加され、また、必要に応じ端子１１からスイ
ッチング電圧が逆方向に印加されてオン・オフする。The tuning circuit short-circuits the coils L3 and L4 as necessary by switching diodes D4 and D5 to provide a high band,
Low band switching is performed, and the switching diodes D4 and D5 are always applied with a transistor operating voltage in the forward direction from the terminal 9, and are turned on and off by being applied with a switching voltage in the reverse direction from the terminal 11 as necessary.
なお、Ｒ１〜Ｒ３はトランジスタＴｒのバイアス抵抗、
Ｃ１，Ｃ４ ，Ｃ９は結合用コンデンサ、Ｃ２は中和用
コンデンサ、Ｃ３，Ｃ５〜Ｃ８，Ｃ１０は直流阻止用コ
ンデンサ、８はＡＧＣ電圧供給用端子、１０は同調電圧
供給用端子である。Note that R1 to R3 are bias resistances of the transistor Tr,
C1, C4, and C9 are coupling capacitors, C2 is a neutralizing capacitor, C3, C5 to C8, and C10 are DC blocking capacitors, 8 is an AGC voltage supply terminal, and 10 is a tuning voltage supply terminal.
このような従来の同調回路においては負荷となる混合回
路４側のインピーダンスを同調回路からみると、同調回
路と混合回路４とを結合するコンデンサＣ９が数ＰＦと
小容量であるために低周波領域において第３図に実線で
示すように著しく増加する。In such a conventional tuning circuit, when looking at the impedance on the side of the mixing circuit 4, which is a load, from the tuning circuit, the capacitor C9 that couples the tuning circuit and the mixing circuit 4 has a small capacity of several PF, so it is difficult to operate in the low frequency region. As shown by the solid line in FIG. 3, the amount increases significantly.
従って、同調回路の負荷Ｑが増加して損失が同調回路内
で発生するため、バンド内の低域における性能が悪化す
る。Therefore, the load Q of the tuning circuit increases and loss occurs within the tuning circuit, resulting in deterioration of performance in the low range within the band.
例えば第４図、第５図に点線で示すように利得および雑
音指数の悪化が著しい。For example, as shown by the dotted lines in FIGS. 4 and 5, the gain and noise figure are significantly deteriorated.
このように受信帯域が比較的広い例えばオーストラリア
、ヨーロッパ等におけるチューナではバンド内の低域に
おいて性能が悪化する欠点があった。As described above, tuners in Australia, Europe, etc., which have a relatively wide reception band, have the disadvantage that performance deteriorates in the low range of the band.
本発明は上記欠点を解消したものでその実施例を第２図
に示して説明する。The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described with reference to FIG. 2.
従来例と同一部分には同一符号を記し、相違する部分に
ついて詳述すると、１次側の同調回路はコイルＬ１，Ｌ
３を直列に接続し、該コイルＬ３に並列にスイッチング
ダイオードＤ４を接続し、前記コイルＬ１、Ｌ３に並列
に可変容量ダイオードＤ１を設けて並列同調回路を成す
。The same parts as in the conventional example are given the same reference numerals, and the different parts are explained in detail.The primary side tuning circuit includes coils L1 and L.
3 are connected in series, a switching diode D4 is connected in parallel to the coil L3, and a variable capacitance diode D1 is provided in parallel to the coils L1 and L3 to form a parallel tuned circuit.
Ｃ５，Ｃ６は直流阻止コンデンサである。C5 and C6 are DC blocking capacitors.
２次側の同調回路はコイルＬ２，Ｌ４を直列に接続し、
該コイルＬ４にスイッチングダイオードＤ５を並列に接
続し、前記コイルＬ２，Ｌ４に並列に可変容量ダイオー
ドＤ２を接続し、コンデンサＣ８，Ｃ９に並列に可変容
量ダイオードＤ３を接続し、可変容量ダイオードＤ２、
Ｄ３のカソード側に同調電圧を印加して容量を同一方向
に増減するように構成される。The secondary side tuning circuit connects coils L2 and L4 in series,
A switching diode D5 is connected in parallel to the coil L4, a variable capacitance diode D2 is connected in parallel to the coils L2 and L4, a variable capacitance diode D3 is connected in parallel to the capacitors C8 and C9, and a variable capacitance diode D2,
A tuning voltage is applied to the cathode side of D3 to increase or decrease the capacitance in the same direction.
上述のように同調回路と同調回路の負荷となる混合回路
４とをコンデンサＣ９と可変容量ダイオードＤ３とで結
合しているので高周波数領域における可変容量ダイオー
ドＤ３の容量値は小さく、同調回路からみた混合回路４
側のインピーダンスは従来例とあまり変わらないが、低
周波数領域における可変容量ダイオートＤ３の容量値は
大きく、同調回路からみた混合回路４側のインピーダン
スは第３図に点線で示すように増加が少なく、従って同
調回路の負荷Ｑが従来例ほど増加せず、同調回路の損失
が抑制され、バンド内の低域における性能が改善される
。As mentioned above, since the tuning circuit and the mixing circuit 4 serving as the load of the tuning circuit are coupled by the capacitor C9 and the variable capacitance diode D3, the capacitance value of the variable capacitance diode D3 in the high frequency region is small, and from the perspective of the tuning circuit. Mixing circuit 4
The impedance on the mixed circuit 4 side is not much different from that of the conventional example, but the capacitance value of the variable capacitance diode D3 in the low frequency region is large, and the impedance on the mixing circuit 4 side seen from the tuning circuit does not increase much as shown by the dotted line in Fig. 3. Therefore, the load Q of the tuning circuit does not increase as much as in the conventional example, the loss of the tuning circuit is suppressed, and the performance in the low range within the band is improved.
例えば第４図、第５図に利得、雑音指数を実線にて示す
ように、バンド内の低域、すなわち、ハイバンドの低域
であるチャンネル７、６、５Ａ、およびローバンドの低
域であるチャンネル２、１において特性が非常に良くな
ったことが認められる。For example, as shown in Figures 4 and 5, the gain and noise figure are shown by solid lines in the low range of the band, that is, the low range of channels 7, 6, and 5A of the high band, and the low range of the low band. It can be seen that the characteristics of channels 2 and 1 have improved significantly.
（実験はオーストラリアで使用されるチューナで行った
。(The experiment was conducted with a tuner used in Australia.
）叙上のように本発明は可変容量ダイオードＤ３を同調
回路のインピーダンスが低域において増加しないように
設けてあるので、バンド内の低域において、負荷、利得
、雑音指数等の諸特性が非常に良くなり、特に広帯域の
チューナに使用して特性の良いチューナを提供できる等
のきわめて大きな効果を奏す。) As mentioned above, in the present invention, the variable capacitance diode D3 is provided so that the impedance of the tuning circuit does not increase in the low range, so various characteristics such as load, gain, noise figure, etc. are significantly reduced in the low range of the band. In particular, it can be used in a broadband tuner to provide a tuner with good characteristics.
第１図は従来の同調回路を示す回路図、第２図は本発明
による実施例を示す回路図、第３図、第４図、第５図は
従来例を点線で実施例を実線で同調同路の特性を示すグ
ラフである。
Ｄ１ 〜Ｄ３・・・・・・可変容量ダイオード、Ｄ４，
Ｄ５・・・・・・スイッチングダイオード、Ｌ１ 〜
Ｌ４・・・・・・コイル、Ｃ５〜Ｃ８・・・・・・直流
阻止用コンデンサ、Ｃ４、Ｃ９・・・・・・結合コンデ
ンサ、１０・・・・・・同調電圧供給端子、１１・・・
・・・スイッチング電圧供給端子。Fig. 1 is a circuit diagram showing a conventional tuning circuit, Fig. 2 is a circuit diagram showing an embodiment according to the present invention, and Figs. 3, 4, and 5 show the conventional example as a dotted line and the embodiment as a solid line. It is a graph showing the characteristics of the same path. D1 ~ D3... Variable capacitance diode, D4,
D5...Switching diode, L1 ~
L4... Coil, C5-C8... DC blocking capacitor, C4, C9... Coupling capacitor, 10... Tuning voltage supply terminal, 11...・
...Switching voltage supply terminal.
Claims (1)
、コイルと可変容量ダイオードとからなる可変周波数並
列同調回路と、受信周波数が低くなるに従ってインピー
ダンスが増加する負荷回路との間を他の可変容量ダイオ
ードで結合し、該２個の可変容量ダイオードの容量を同
一方向に増減して広帯域にわたって同調を取るようにし
たことを特徴とする同調回路。1. In a VHF tuner used for television, a variable frequency parallel tuning circuit consisting of a coil and a variable capacitance diode is coupled with a load circuit whose impedance increases as the receiving frequency becomes lower, using another variable capacitance diode, A tuning circuit characterized in that the capacitances of the two variable capacitance diodes are increased or decreased in the same direction to achieve tuning over a wide band.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52127891A JPS583416B2 (en) | 1977-10-25 | 1977-10-25 | tuned circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52127891A JPS583416B2 (en) | 1977-10-25 | 1977-10-25 | tuned circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5460801A JPS5460801A (en) | 1979-05-16 |
| JPS583416B2 true JPS583416B2 (en) | 1983-01-21 |
Family
ID=14971206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52127891A Expired JPS583416B2 (en) | 1977-10-25 | 1977-10-25 | tuned circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS583416B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS514822A (en) * | 1974-06-28 | 1976-01-16 | Nisso Master Builders Kk | PUREKYASUTOTETSUKINKONKURIITONO HASHIRA * HARIBUZAINO SETSUGOHOHO |
-
1977
- 1977-10-25 JP JP52127891A patent/JPS583416B2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS514822A (en) * | 1974-06-28 | 1976-01-16 | Nisso Master Builders Kk | PUREKYASUTOTETSUKINKONKURIITONO HASHIRA * HARIBUZAINO SETSUGOHOHO |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5460801A (en) | 1979-05-16 |
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